mirror of
https://github.com/reactos/reactos.git
synced 2024-06-30 01:42:30 +00:00
Remove useless files
svn path=/trunk/; revision=31055
This commit is contained in:
Hervé Poussineau
parent
72fbf8e8eb
commit
d709944d3b
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@ -1,24 +0,0 @@
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/* $Id: ipi.c 23907 2006-09-04 05:52:23Z arty $
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*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS kernel
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* FILE: hal/halx86/generic/ipi.c
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* PURPOSE: Miscellaneous hardware functions
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* PROGRAMMER: Eric Kohl (ekohl@rz-online.de)
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*/
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/* INCLUDES *****************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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/* FUNCTIONS ****************************************************************/
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VOID STDCALL
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HalRequestIpi(ULONG ProcessorNo)
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{
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DPRINT("HalRequestIpi(ProcessorNo %lu)\n", ProcessorNo);
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}
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/* EOF */
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@ -1,547 +0,0 @@
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/* $Id: kdbg.c 23907 2006-09-04 05:52:23Z arty $
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*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS kernel
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* FILE: ntoskrnl/hal/x86/kdbg.c
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* PURPOSE: Serial i/o functions for the kernel debugger.
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* PROGRAMMER: Emanuele Aliberti
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* Eric Kohl
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* UPDATE HISTORY:
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* Created 05/09/99
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*/
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/* INCLUDES *****************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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#define DEFAULT_BAUD_RATE 19200
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/* MACROS *******************************************************************/
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#define SER_RBR(x) ((x)+0)
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#define SER_THR(x) ((x)+0)
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#define SER_DLL(x) ((x)+0)
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#define SER_IER(x) ((x)+1)
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#define SR_IER_ERDA 0x01
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#define SR_IER_ETHRE 0x02
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#define SR_IER_ERLSI 0x04
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#define SR_IER_EMS 0x08
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#define SR_IER_ALL 0x0F
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#define SER_DLM(x) ((x)+1)
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#define SER_IIR(x) ((x)+2)
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#define SER_FCR(x) ((x)+2)
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#define SR_FCR_ENABLE_FIFO 0x01
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#define SR_FCR_CLEAR_RCVR 0x02
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#define SR_FCR_CLEAR_XMIT 0x04
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#define SER_LCR(x) ((x)+3)
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#define SR_LCR_CS5 0x00
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#define SR_LCR_CS6 0x01
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#define SR_LCR_CS7 0x02
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#define SR_LCR_CS8 0x03
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#define SR_LCR_ST1 0x00
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#define SR_LCR_ST2 0x04
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#define SR_LCR_PNO 0x00
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#define SR_LCR_POD 0x08
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#define SR_LCR_PEV 0x18
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#define SR_LCR_PMK 0x28
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#define SR_LCR_PSP 0x38
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#define SR_LCR_BRK 0x40
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#define SR_LCR_DLAB 0x80
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#define SER_MCR(x) ((x)+4)
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#define SR_MCR_DTR 0x01
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#define SR_MCR_RTS 0x02
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#define SR_MCR_OUT1 0x04
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#define SR_MCR_OUT2 0x08
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#define SR_MCR_LOOP 0x10
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#define SER_LSR(x) ((x)+5)
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#define SR_LSR_DR 0x01
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#define SR_LSR_TBE 0x20
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#define SER_MSR(x) ((x)+6)
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#define SR_MSR_CTS 0x10
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#define SR_MSR_DSR 0x20
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#define SER_SCR(x) ((x)+7)
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/* GLOBAL VARIABLES *********************************************************/
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#define KdComPortInUse _KdComPortInUse
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ULONG KdComPortInUse = 0;
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/* STATIC VARIABLES *********************************************************/
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static ULONG ComPort = 0;
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static ULONG BaudRate = 0;
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static PUCHAR PortBase = (PUCHAR)0;
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/* The com port must only be initialized once! */
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static BOOLEAN PortInitialized = FALSE;
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/* STATIC FUNCTIONS *********************************************************/
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static BOOLEAN
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KdpDoesComPortExist (PUCHAR BaseAddress)
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{
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BOOLEAN found;
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UCHAR mcr;
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UCHAR msr;
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found = FALSE;
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/* save Modem Control Register (MCR) */
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mcr = READ_PORT_UCHAR (SER_MCR(BaseAddress));
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/* enable loop mode (set Bit 4 of the MCR) */
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WRITE_PORT_UCHAR (SER_MCR(BaseAddress), 0x10);
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/* clear all modem output bits */
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WRITE_PORT_UCHAR (SER_MCR(BaseAddress), 0x10);
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/* read the Modem Status Register */
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msr = READ_PORT_UCHAR (SER_MSR(BaseAddress));
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/*
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* the upper nibble of the MSR (modem output bits) must be
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* equal to the lower nibble of the MCR (modem input bits)
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*/
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if ((msr & 0xF0) == 0x00)
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{
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/* set all modem output bits */
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WRITE_PORT_UCHAR (SER_MCR(BaseAddress), 0x1F);
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/* read the Modem Status Register */
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msr = READ_PORT_UCHAR (SER_MSR(BaseAddress));
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/*
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* the upper nibble of the MSR (modem output bits) must be
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* equal to the lower nibble of the MCR (modem input bits)
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*/
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if ((msr & 0xF0) == 0xF0)
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{
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/*
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* setup a resonable state for the port:
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* enable fifo and clear recieve/transmit buffers
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*/
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WRITE_PORT_UCHAR (SER_FCR(BaseAddress),
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(SR_FCR_ENABLE_FIFO | SR_FCR_CLEAR_RCVR | SR_FCR_CLEAR_XMIT));
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WRITE_PORT_UCHAR (SER_FCR(BaseAddress), 0);
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READ_PORT_UCHAR (SER_RBR(BaseAddress));
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WRITE_PORT_UCHAR (SER_IER(BaseAddress), 0);
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found = TRUE;
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}
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}
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/* restore MCR */
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WRITE_PORT_UCHAR (SER_MCR(BaseAddress), mcr);
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return (found);
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}
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/* FUNCTIONS ****************************************************************/
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/* HAL.KdPortInitialize */
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BOOLEAN
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STDCALL
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KdPortInitialize (
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PKD_PORT_INFORMATION PortInformation,
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ULONG Unknown1,
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ULONG Unknown2
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)
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{
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ULONG BaseArray[5] = {0, 0x3F8, 0x2F8, 0x3E8, 0x2E8};
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char buffer[80];
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ULONG divisor;
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UCHAR lcr;
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if (PortInitialized == FALSE)
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{
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if (PortInformation->BaudRate != 0)
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{
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BaudRate = PortInformation->BaudRate;
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}
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else
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{
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BaudRate = DEFAULT_BAUD_RATE;
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}
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if (PortInformation->ComPort == 0)
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{
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if (KdpDoesComPortExist ((PUCHAR)BaseArray[2]))
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{
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PortBase = (PUCHAR)BaseArray[2];
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ComPort = 2;
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PortInformation->BaseAddress = (ULONG)PortBase;
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PortInformation->ComPort = ComPort;
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#ifndef NDEBUG
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sprintf (buffer,
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"\nSerial port COM%ld found at 0x%lx\n",
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ComPort,
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(ULONG)PortBase);
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HalDisplayString (buffer);
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#endif /* NDEBUG */
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}
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else if (KdpDoesComPortExist ((PUCHAR)BaseArray[1]))
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{
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PortBase = (PUCHAR)BaseArray[1];
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ComPort = 1;
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PortInformation->BaseAddress = (ULONG)PortBase;
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PortInformation->ComPort = ComPort;
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#ifndef NDEBUG
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sprintf (buffer,
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"\nSerial port COM%ld found at 0x%lx\n",
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ComPort,
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(ULONG)PortBase);
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HalDisplayString (buffer);
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#endif /* NDEBUG */
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}
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else
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{
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sprintf (buffer,
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"\nKernel Debugger: No COM port found!!!\n\n");
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HalDisplayString (buffer);
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return FALSE;
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}
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}
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else
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{
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if (KdpDoesComPortExist ((PUCHAR)BaseArray[PortInformation->ComPort]))
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{
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PortBase = (PUCHAR)BaseArray[PortInformation->ComPort];
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ComPort = PortInformation->ComPort;
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PortInformation->BaseAddress = (ULONG)PortBase;
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#ifndef NDEBUG
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sprintf (buffer,
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"\nSerial port COM%ld found at 0x%lx\n",
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ComPort,
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(ULONG)PortBase);
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HalDisplayString (buffer);
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#endif /* NDEBUG */
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}
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else
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{
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sprintf (buffer,
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"\nKernel Debugger: No serial port found!!!\n\n");
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HalDisplayString (buffer);
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return FALSE;
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}
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}
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PortInitialized = TRUE;
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}
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/*
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* set baud rate and data format (8N1)
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*/
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/* turn on DTR and RTS */
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WRITE_PORT_UCHAR (SER_MCR(PortBase), SR_MCR_DTR | SR_MCR_RTS);
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/* set DLAB */
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lcr = READ_PORT_UCHAR (SER_LCR(PortBase)) | SR_LCR_DLAB;
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WRITE_PORT_UCHAR (SER_LCR(PortBase), lcr);
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/* set baud rate */
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divisor = 115200 / BaudRate;
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WRITE_PORT_UCHAR (SER_DLL(PortBase), (UCHAR)(divisor & 0xff));
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WRITE_PORT_UCHAR (SER_DLM(PortBase), (UCHAR)((divisor >> 8) & 0xff));
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/* reset DLAB and set 8N1 format */
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WRITE_PORT_UCHAR (SER_LCR(PortBase),
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SR_LCR_CS8 | SR_LCR_ST1 | SR_LCR_PNO);
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/* read junk out of the RBR */
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lcr = READ_PORT_UCHAR (SER_RBR(PortBase));
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/*
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* set global info
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*/
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KdComPortInUse = (ULONG)PortBase;
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/*
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* print message to blue screen
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*/
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sprintf (buffer,
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"\nKernel Debugger: COM%ld (Port 0x%lx) BaudRate %ld\n\n",
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ComPort,
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(ULONG)PortBase,
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BaudRate);
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HalDisplayString (buffer);
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return TRUE;
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}
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/* HAL.KdPortInitializeEx */
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BOOLEAN
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STDCALL
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KdPortInitializeEx (
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PKD_PORT_INFORMATION PortInformation,
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ULONG Unknown1,
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ULONG Unknown2
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)
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{
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ULONG BaseArray[5] = {0, 0x3F8, 0x2F8, 0x3E8, 0x2E8};
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PUCHAR ComPortBase;
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char buffer[80];
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ULONG divisor;
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UCHAR lcr;
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if (PortInformation->BaudRate == 0)
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{
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PortInformation->BaudRate = DEFAULT_BAUD_RATE;
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}
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if (PortInformation->ComPort == 0)
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{
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return FALSE;
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}
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else
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{
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if (KdpDoesComPortExist ((PUCHAR)BaseArray[PortInformation->ComPort]))
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{
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ComPortBase = (PUCHAR)BaseArray[PortInformation->ComPort];
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PortInformation->BaseAddress = (ULONG)ComPortBase;
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#ifndef NDEBUG
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sprintf (buffer,
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"\nSerial port COM%ld found at 0x%lx\n",
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PortInformation->ComPort,
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(ULONG)ComPortBase];
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HalDisplayString (buffer);
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#endif /* NDEBUG */
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}
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else
|
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{
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sprintf (buffer,
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"\nKernel Debugger: Serial port not found!!!\n\n");
|
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HalDisplayString (buffer);
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return FALSE;
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}
|
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}
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|
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/*
|
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* set baud rate and data format (8N1)
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*/
|
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|
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/* turn on DTR and RTS */
|
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WRITE_PORT_UCHAR (SER_MCR(ComPortBase), SR_MCR_DTR | SR_MCR_RTS);
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|
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/* set DLAB */
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lcr = READ_PORT_UCHAR (SER_LCR(ComPortBase)) | SR_LCR_DLAB;
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WRITE_PORT_UCHAR (SER_LCR(ComPortBase), lcr);
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|
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/* set baud rate */
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divisor = 115200 / PortInformation->BaudRate;
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WRITE_PORT_UCHAR (SER_DLL(ComPortBase), (UCHAR)(divisor & 0xff));
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WRITE_PORT_UCHAR (SER_DLM(ComPortBase), (UCHAR)((divisor >> 8) & 0xff));
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|
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/* reset DLAB and set 8N1 format */
|
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WRITE_PORT_UCHAR (SER_LCR(ComPortBase),
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SR_LCR_CS8 | SR_LCR_ST1 | SR_LCR_PNO);
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|
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/* read junk out of the RBR */
|
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lcr = READ_PORT_UCHAR (SER_RBR(ComPortBase));
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#ifndef NDEBUG
|
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|
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/*
|
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* print message to blue screen
|
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*/
|
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sprintf (buffer,
|
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"\nKernel Debugger: COM%ld (Port 0x%lx) BaudRate %ld\n\n",
|
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PortInformation->ComPort,
|
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(ULONG)ComPortBase,
|
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PortInformation->BaudRate);
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|
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HalDisplayString (buffer);
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|
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#endif /* NDEBUG */
|
||||
|
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return TRUE;
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}
|
||||
|
||||
|
||||
/* HAL.KdPortGetByte */
|
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BOOLEAN
|
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STDCALL
|
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KdPortGetByte (
|
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PUCHAR ByteRecieved
|
||||
)
|
||||
{
|
||||
if (PortInitialized == FALSE)
|
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return FALSE;
|
||||
|
||||
if ((READ_PORT_UCHAR (SER_LSR(PortBase)) & SR_LSR_DR))
|
||||
{
|
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*ByteRecieved = READ_PORT_UCHAR (SER_RBR(PortBase));
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
/* HAL.KdPortGetByteEx */
|
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BOOLEAN
|
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STDCALL
|
||||
KdPortGetByteEx (
|
||||
PKD_PORT_INFORMATION PortInformation,
|
||||
PUCHAR ByteRecieved
|
||||
)
|
||||
{
|
||||
PUCHAR ComPortBase = (PUCHAR)PortInformation->BaseAddress;
|
||||
|
||||
if ((READ_PORT_UCHAR (SER_LSR(ComPortBase)) & SR_LSR_DR))
|
||||
{
|
||||
*ByteRecieved = READ_PORT_UCHAR (SER_RBR(ComPortBase));
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
/* HAL.KdPortPollByte */
|
||||
BOOLEAN
|
||||
STDCALL
|
||||
KdPortPollByte (
|
||||
PUCHAR ByteRecieved
|
||||
)
|
||||
{
|
||||
if (PortInitialized == FALSE)
|
||||
return FALSE;
|
||||
|
||||
while ((READ_PORT_UCHAR (SER_LSR(PortBase)) & SR_LSR_DR) == 0)
|
||||
;
|
||||
|
||||
*ByteRecieved = READ_PORT_UCHAR (SER_RBR(PortBase));
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
/* HAL.KdPortPollByteEx */
|
||||
BOOLEAN
|
||||
STDCALL
|
||||
KdPortPollByteEx (
|
||||
PKD_PORT_INFORMATION PortInformation,
|
||||
PUCHAR ByteRecieved
|
||||
)
|
||||
{
|
||||
PUCHAR ComPortBase = (PUCHAR)PortInformation->BaseAddress;
|
||||
|
||||
while ((READ_PORT_UCHAR (SER_LSR(ComPortBase)) & SR_LSR_DR) == 0)
|
||||
;
|
||||
|
||||
*ByteRecieved = READ_PORT_UCHAR (SER_RBR(ComPortBase));
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* HAL.KdPortPutByte */
|
||||
VOID
|
||||
STDCALL
|
||||
KdPortPutByte (
|
||||
UCHAR ByteToSend
|
||||
)
|
||||
{
|
||||
if (PortInitialized == FALSE)
|
||||
return;
|
||||
|
||||
while ((READ_PORT_UCHAR (SER_LSR(PortBase)) & SR_LSR_TBE) == 0)
|
||||
;
|
||||
|
||||
WRITE_PORT_UCHAR (SER_THR(PortBase), ByteToSend);
|
||||
}
|
||||
|
||||
/* HAL.KdPortPutByteEx */
|
||||
VOID
|
||||
STDCALL
|
||||
KdPortPutByteEx (
|
||||
PKD_PORT_INFORMATION PortInformation,
|
||||
UCHAR ByteToSend
|
||||
)
|
||||
{
|
||||
PUCHAR ComPortBase = (PUCHAR)PortInformation->BaseAddress;
|
||||
|
||||
while ((READ_PORT_UCHAR (SER_LSR(ComPortBase)) & SR_LSR_TBE) == 0)
|
||||
;
|
||||
|
||||
WRITE_PORT_UCHAR (SER_THR(ComPortBase), ByteToSend);
|
||||
}
|
||||
|
||||
|
||||
/* HAL.KdPortRestore */
|
||||
VOID
|
||||
STDCALL
|
||||
KdPortRestore (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
/* HAL.KdPortSave */
|
||||
VOID
|
||||
STDCALL
|
||||
KdPortSave (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
/* HAL.KdPortDisableInterrupts */
|
||||
BOOLEAN
|
||||
STDCALL
|
||||
KdPortDisableInterrupts()
|
||||
{
|
||||
UCHAR ch;
|
||||
|
||||
if (PortInitialized == FALSE)
|
||||
return FALSE;
|
||||
|
||||
ch = READ_PORT_UCHAR (SER_MCR (PortBase));
|
||||
ch &= (~(SR_MCR_OUT1 | SR_MCR_OUT2));
|
||||
WRITE_PORT_UCHAR (SER_MCR (PortBase), ch);
|
||||
|
||||
ch = READ_PORT_UCHAR (SER_IER (PortBase));
|
||||
ch &= (~SR_IER_ALL);
|
||||
WRITE_PORT_UCHAR (SER_IER (PortBase), ch);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
/* HAL.KdPortEnableInterrupts */
|
||||
BOOLEAN
|
||||
STDCALL
|
||||
KdPortEnableInterrupts()
|
||||
{
|
||||
UCHAR ch;
|
||||
|
||||
if (PortInitialized == FALSE)
|
||||
return FALSE;
|
||||
|
||||
ch = READ_PORT_UCHAR (SER_IER (PortBase));
|
||||
ch &= (~SR_IER_ALL);
|
||||
ch |= SR_IER_ERDA;
|
||||
WRITE_PORT_UCHAR (SER_IER (PortBase), ch);
|
||||
|
||||
ch = READ_PORT_UCHAR (SER_MCR (PortBase));
|
||||
ch &= (~SR_MCR_LOOP);
|
||||
ch |= (SR_MCR_OUT1 | SR_MCR_OUT2);
|
||||
WRITE_PORT_UCHAR (SER_MCR (PortBase), ch);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
|
|
@ -1,79 +0,0 @@
|
|||
/*
|
||||
* ReactOS kernel
|
||||
* Copyright (C) 2002 ReactOS Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
/* $Id: mca.c 23907 2006-09-04 05:52:23Z arty $
|
||||
*
|
||||
* COPYRIGHT: See COPYING in the top level directory
|
||||
* PROJECT: ReactOS kernel
|
||||
* FILE: hal/halx86/mca.c
|
||||
* PURPOSE: Interfaces to the MicroChannel bus
|
||||
* PROGRAMMER: Eric Kohl (ekohl@rz-online.de)
|
||||
*/
|
||||
|
||||
/*
|
||||
* TODO:
|
||||
* What Adapter ID is read from an empty slot?
|
||||
*/
|
||||
|
||||
/* INCLUDES *****************************************************************/
|
||||
|
||||
#include <hal.h>
|
||||
#define NDEBUG
|
||||
#include <debug.h>
|
||||
|
||||
/* FUNCTIONS ****************************************************************/
|
||||
|
||||
ULONG STDCALL
|
||||
HalpGetMicroChannelData(PBUS_HANDLER BusHandler,
|
||||
ULONG BusNumber,
|
||||
ULONG SlotNumber,
|
||||
PVOID Buffer,
|
||||
ULONG Offset,
|
||||
ULONG Length)
|
||||
{
|
||||
PCM_MCA_POS_DATA PosData = (PCM_MCA_POS_DATA)Buffer;
|
||||
|
||||
DPRINT("HalpGetMicroChannelData() called.\n");
|
||||
DPRINT(" BusNumber %lu\n", BusNumber);
|
||||
DPRINT(" SlotNumber %lu\n", SlotNumber);
|
||||
DPRINT(" Offset 0x%lx\n", Offset);
|
||||
DPRINT(" Length 0x%lx\n", Length);
|
||||
|
||||
if ((BusNumber != 0) ||
|
||||
(SlotNumber == 0) || (SlotNumber > 8) ||
|
||||
(Length < sizeof(CM_MCA_POS_DATA)))
|
||||
return(0);
|
||||
|
||||
/* Enter Setup-Mode for given slot */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x96, (UCHAR)(((UCHAR)(SlotNumber - 1) & 0x07) | 0x08));
|
||||
|
||||
/* Read POS data */
|
||||
PosData->AdapterId = (READ_PORT_UCHAR((PUCHAR)0x101) << 8) +
|
||||
READ_PORT_UCHAR((PUCHAR)0x100);
|
||||
PosData->PosData1 = READ_PORT_UCHAR((PUCHAR)0x102);
|
||||
PosData->PosData2 = READ_PORT_UCHAR((PUCHAR)0x103);
|
||||
PosData->PosData3 = READ_PORT_UCHAR((PUCHAR)0x104);
|
||||
PosData->PosData4 = READ_PORT_UCHAR((PUCHAR)0x105);
|
||||
|
||||
/* Leave Setup-Mode for given slot */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x96, (UCHAR)((UCHAR)(SlotNumber - 1) & 0x07));
|
||||
|
||||
return(sizeof(CM_MCA_POS_DATA));
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
|
|
@ -1,121 +0,0 @@
|
|||
/* $Id: pwroff.c 23907 2006-09-04 05:52:23Z arty $
|
||||
*
|
||||
* FILE : reactos/hal/x86/apm.c
|
||||
* DESCRIPTION: Turn CPU off...
|
||||
* PROJECT : ReactOS Operating System
|
||||
* AUTHOR : D. Lindauer (July 11 1997)
|
||||
* NOTE : This program is public domain
|
||||
* REVISIONS :
|
||||
* 1999-12-26
|
||||
*/
|
||||
|
||||
#define APM_FUNCTION_AVAILABLE 0x5300
|
||||
#define APM_FUNCTION_CONNREAL 0x5301
|
||||
#define APM_FUNCTION_POWEROFF 0x5307
|
||||
#define APM_FUNCTION_ENABLECPU 0x530d
|
||||
#define APM_FUNCTION_ENABLEAPM 0x530e
|
||||
|
||||
#define APM_DEVICE_BIOS 0
|
||||
#define APM_DEVICE_ALL 1
|
||||
|
||||
#define APM_MODE_DISABLE 0
|
||||
#define APM_MODE_ENABLE 1
|
||||
|
||||
|
||||
|
||||
#if defined(__GNUC__)
|
||||
|
||||
nopm db 'No power management functionality',10,13,'$'
|
||||
errmsg db 'Power management error',10,13,'$'
|
||||
wrongver db 'Need APM version 1.1 or better',10,13,'$'
|
||||
;
|
||||
; Entry point
|
||||
;
|
||||
go:
|
||||
mov dx,offset nopm
|
||||
jc error
|
||||
cmp ax,101h ; See if version 1.1 or greater
|
||||
mov dx,offset wrongver
|
||||
jc error
|
||||
|
||||
mov [ver],ax
|
||||
mov ax,5301h ; Do a real mode connection
|
||||
mov bx,0 ; device = BIOS
|
||||
int 15h
|
||||
jnc noconerr
|
||||
|
||||
cmp ah,2 ; Pass if already connected
|
||||
mov dx,offset errmsg ; else error
|
||||
jnz error
|
||||
noconerr:
|
||||
mov ax,530eh ; Enable latest version of APM
|
||||
mov bx,0 ; device = BIOS
|
||||
mov cx,[ver] ; version
|
||||
int 15h
|
||||
mov dx,offset errmsg
|
||||
jc error
|
||||
|
||||
mov ax,530dh ; Now engage and enable CPU management
|
||||
mov bx,1 ; device = all
|
||||
mov cx,1 ; enable
|
||||
int 15h
|
||||
mov dx,offset errmsg
|
||||
jc error
|
||||
|
||||
mov ax,530fh
|
||||
mov bx,1 ; device = ALL
|
||||
mov cx,1 ; enable
|
||||
int 15h
|
||||
mov dx,offset errmsg
|
||||
jc error
|
||||
|
||||
mov dx,offset errmsg
|
||||
error:
|
||||
call print
|
||||
mov ax,4c01h
|
||||
int 21h
|
||||
int 3
|
||||
end start
|
||||
|
||||
|
||||
BOOLEAN
|
||||
ApmCall (
|
||||
DWORD Function,
|
||||
DWORD Device,
|
||||
DWORD Mode
|
||||
)
|
||||
{
|
||||
/* AX <== Function */
|
||||
/* BX <== Device */
|
||||
/* CX <== Mode */
|
||||
__asm__("int 21\n"); /* 0x15 */
|
||||
}
|
||||
|
||||
#elif defined(_MSC_VER)
|
||||
#else
|
||||
#error Unknown compiler for inline assembler
|
||||
#endif
|
||||
|
||||
|
||||
BOOLEAN
|
||||
HalPowerOff (VOID)
|
||||
{
|
||||
ApmCall (
|
||||
APM_FUNCTION_AVAILABLE,
|
||||
APM_DEVICE_BIOS,
|
||||
0
|
||||
);
|
||||
ApmCall (
|
||||
APM_FUNCTION_ENABLEAPM,
|
||||
);
|
||||
/* Shutdown CPU */
|
||||
ApmCall (
|
||||
APM_FUNCTION_POWEROFF,
|
||||
APM_DEVICE_ALL,
|
||||
3
|
||||
);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
/* EOF */
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/* $Id: resource.c 23907 2006-09-04 05:52:23Z arty $
|
||||
*
|
||||
* COPYRIGHT: See COPYING in the top level directory
|
||||
* PROJECT: ReactOS kernel
|
||||
* FILE: hal/halx86/generic/resource.c
|
||||
* PURPOSE: Miscellaneous resource functions
|
||||
* PROGRAMMER: Eric Kohl (ekohl@rz-online.de)
|
||||
*/
|
||||
|
||||
/* INCLUDES *****************************************************************/
|
||||
|
||||
#include <hal.h>
|
||||
#define NDEBUG
|
||||
#include <debug.h>
|
||||
|
||||
|
||||
/* FUNCTIONS ****************************************************************/
|
||||
|
||||
VOID STDCALL
|
||||
HalReportResourceUsage(VOID)
|
||||
{
|
||||
/*
|
||||
* FIXME: Report all resources used by hal.
|
||||
* Calls IoReportHalResourceUsage()
|
||||
*/
|
||||
|
||||
/* Initialize PCI bus. */
|
||||
HalpInitPciBus ();
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
/* $Id: sysbus.c 23907 2006-09-04 05:52:23Z arty $
|
||||
*
|
||||
* COPYRIGHT: See COPYING in the top level directory
|
||||
* PROJECT: ReactOS kernel
|
||||
* FILE: ntoskrnl/hal/sysbus.c
|
||||
* PURPOSE: System bus handler functions
|
||||
* PROGRAMMER: Eric Kohl (ekohl@rz-online.de)
|
||||
* UPDATE HISTORY:
|
||||
* 09/04/2000 Created
|
||||
*/
|
||||
|
||||
/* INCLUDES *****************************************************************/
|
||||
|
||||
#include <hal.h>
|
||||
#define NDEBUG
|
||||
#include <debug.h>
|
||||
|
||||
|
||||
/* FUNCTIONS ****************************************************************/
|
||||
|
||||
ULONG STDCALL
|
||||
HalpGetSystemInterruptVector(PVOID BusHandler,
|
||||
ULONG BusNumber,
|
||||
ULONG BusInterruptLevel,
|
||||
ULONG BusInterruptVector,
|
||||
PKIRQL Irql,
|
||||
PKAFFINITY Affinity)
|
||||
{
|
||||
ULONG Vector = IRQ2VECTOR(BusInterruptVector);
|
||||
*Irql = VECTOR2IRQL(Vector);
|
||||
*Affinity = 0xFFFFFFFF;
|
||||
return Vector;
|
||||
}
|
||||
|
||||
|
||||
BOOLEAN STDCALL
|
||||
HalpTranslateSystemBusAddress(PBUS_HANDLER BusHandler,
|
||||
ULONG BusNumber,
|
||||
PHYSICAL_ADDRESS BusAddress,
|
||||
PULONG AddressSpace,
|
||||
PPHYSICAL_ADDRESS TranslatedAddress)
|
||||
{
|
||||
ULONG BaseAddress = 0;
|
||||
|
||||
if (*AddressSpace == 0)
|
||||
{
|
||||
/* memory space */
|
||||
|
||||
}
|
||||
else if (*AddressSpace == 1)
|
||||
{
|
||||
/* io space */
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* other */
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
TranslatedAddress->QuadPart = BusAddress.QuadPart + BaseAddress;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
/*
|
||||
* FILE: hal/halx86/generic/timer.S
|
||||
* COPYRIGHT: See COPYING in the top level directory
|
||||
* PURPOSE: System Timer Interrupt and Management
|
||||
* PROGRAMMER: Alex Ionescu (alex@relsoft.net)
|
||||
*/
|
||||
|
||||
/* INCLUDES ******************************************************************/
|
||||
|
||||
#include <asm.h>
|
||||
#include <internal/i386/asmmacro.S>
|
||||
.intel_syntax noprefix
|
||||
|
||||
/* FUNCTIONS *****************************************************************/
|
||||
|
||||
.globl _HalpClockInterrupt@0
|
||||
.func HalpClockInterrupt@0
|
||||
_HalpClockInterrupt@0:
|
||||
|
||||
/* Enter trap */
|
||||
INT_PROLOG Hci, DoPushFakeErrorCode
|
||||
|
||||
/* Push vector and make stack for IRQL */
|
||||
push 0x30
|
||||
sub esp, 4
|
||||
|
||||
/* Begin the interrupt */
|
||||
push esp
|
||||
push 0x30
|
||||
push CLOCK2_LEVEL
|
||||
call _HalBeginSystemInterrupt@12
|
||||
|
||||
/* Check if it's spurious */
|
||||
or al, al
|
||||
jz Spurious
|
||||
|
||||
/* Do a tick */
|
||||
mov eax, 100000
|
||||
jmp _KeUpdateSystemTime@0
|
||||
|
||||
Spurious:
|
||||
|
||||
/* Exit the interrupt */
|
||||
add esp, 8
|
||||
mov esi, $
|
||||
jmp _Kei386EoiHelper@0
|
||||
.endfunc
|
||||
|
||||
|
|
@ -1,102 +0,0 @@
|
|||
/*
|
||||
* COPYRIGHT: See COPYING in the top level directory
|
||||
* PROJECT: ReactOS kernel
|
||||
* FILE: ntoskrnl/hal/x86/time.c
|
||||
* PURPOSE: Getting time information
|
||||
* UPDATE HISTORY:
|
||||
*/
|
||||
|
||||
/* INCLUDES *****************************************************************/
|
||||
|
||||
#include <hal.h>
|
||||
#define NDEBUG
|
||||
#include <debug.h>
|
||||
|
||||
|
||||
/* MACROS and CONSTANTS ******************************************************/
|
||||
|
||||
/* macro BCD_INT : convert bcd to int */
|
||||
#define BCD_INT(bcd) (((bcd & 0xf0) >> 4) * 10 + (bcd &0x0f))
|
||||
|
||||
/* macro INT_BCD : convert int to bcd */
|
||||
#define INT_BCD(int) (((int / 10) << 4) + (int % 10))
|
||||
|
||||
|
||||
#define RTC_REGISTER_A 0x0A
|
||||
#define RTC_REG_A_UIP 0x80 /* Update In Progress bit */
|
||||
|
||||
#define RTC_REGISTER_B 0x0B
|
||||
|
||||
#define RTC_REGISTER_CENTURY 0x32
|
||||
|
||||
/* GLOBALS ******************************************************************/
|
||||
|
||||
/* FUNCTIONS *****************************************************************/
|
||||
|
||||
BOOLEAN STDCALL
|
||||
HalQueryRealTimeClock(PTIME_FIELDS Time)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
VOID STDCALL
|
||||
HalSetRealTimeClock(PTIME_FIELDS Time)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
BOOLEAN STDCALL
|
||||
HalGetEnvironmentVariable(PCH Name,
|
||||
USHORT ValueLength,
|
||||
PCH Value)
|
||||
{
|
||||
strncpy(Value, "TRUE", ValueLength);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
BOOLEAN STDCALL
|
||||
HalSetEnvironmentVariable(PCH Name,
|
||||
PCH Value)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
ULONG STDCALL
|
||||
HalpGetCmosData(PBUS_HANDLER BusHandler,
|
||||
ULONG BusNumber,
|
||||
ULONG SlotNumber,
|
||||
PVOID Buffer,
|
||||
ULONG Offset,
|
||||
ULONG Length)
|
||||
{
|
||||
DPRINT("HalpGetCmosData() called.\n");
|
||||
DPRINT(" BusNumber %lu\n", BusNumber);
|
||||
DPRINT(" SlotNumber %lu\n", SlotNumber);
|
||||
DPRINT(" Offset 0x%lx\n", Offset);
|
||||
DPRINT(" Length 0x%lx\n", Length);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
ULONG STDCALL
|
||||
HalpSetCmosData(PBUS_HANDLER BusHandler,
|
||||
ULONG BusNumber,
|
||||
ULONG SlotNumber,
|
||||
PVOID Buffer,
|
||||
ULONG Offset,
|
||||
ULONG Length)
|
||||
{
|
||||
DPRINT("HalpSetCmosData() called.\n");
|
||||
DPRINT(" BusNumber %lu\n", BusNumber);
|
||||
DPRINT(" SlotNumber %lu\n", SlotNumber);
|
||||
DPRINT(" Offset 0x%lx\n", Offset);
|
||||
DPRINT(" Length 0x%lx\n", Length);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
|
|
@ -1,570 +0,0 @@
|
|||
/* $Id$
|
||||
*
|
||||
* COPYRIGHT: See COPYING in the top level directory
|
||||
* PROJECT: ReactOS kernel
|
||||
* FILE: ntoskrnl/hal/x86/irql.c
|
||||
* PURPOSE: Implements IRQLs
|
||||
* PROGRAMMER: David Welch (welch@cwcom.net)
|
||||
*/
|
||||
|
||||
/* INCLUDES *****************************************************************/
|
||||
|
||||
#include <hal.h>
|
||||
#define NDEBUG
|
||||
#include <debug.h>
|
||||
|
||||
/* GLOBALS ******************************************************************/
|
||||
|
||||
/*
|
||||
* FIXME: Use EISA_CONTROL STRUCTURE INSTEAD OF HARD-CODED OFFSETS
|
||||
*/
|
||||
|
||||
typedef union
|
||||
{
|
||||
USHORT both;
|
||||
struct
|
||||
{
|
||||
UCHAR master;
|
||||
UCHAR slave;
|
||||
};
|
||||
}
|
||||
PIC_MASK;
|
||||
|
||||
/*
|
||||
* PURPOSE: - Mask for HalEnableSystemInterrupt and HalDisableSystemInterrupt
|
||||
* - At startup enable timer and cascade
|
||||
*/
|
||||
#if defined(__GNUC__)
|
||||
static PIC_MASK pic_mask = {.both = 0xFFFA};
|
||||
#else
|
||||
static PIC_MASK pic_mask = { 0xFFFA };
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* PURPOSE: Mask for disabling of acknowledged interrupts
|
||||
*/
|
||||
#if defined(__GNUC__)
|
||||
static PIC_MASK pic_mask_intr = {.both = 0x0000};
|
||||
#else
|
||||
static PIC_MASK pic_mask_intr = { 0 };
|
||||
#endif
|
||||
|
||||
static ULONG HalpPendingInterruptCount[NR_IRQS];
|
||||
|
||||
#define DIRQL_TO_IRQ(x) (PROFILE_LEVEL - x)
|
||||
#define IRQ_TO_DIRQL(x) (PROFILE_LEVEL - x)
|
||||
|
||||
#ifdef _MSC_VER
|
||||
|
||||
#define KiInterruptDispatch2(x, y)
|
||||
|
||||
#else
|
||||
|
||||
VOID STDCALL
|
||||
KiInterruptDispatch2 (ULONG Irq, KIRQL old_level);
|
||||
|
||||
#endif
|
||||
|
||||
/* FUNCTIONS ****************************************************************/
|
||||
|
||||
#undef KeGetCurrentIrql
|
||||
KIRQL STDCALL KeGetCurrentIrql (VOID)
|
||||
/*
|
||||
* PURPOSE: Returns the current irq level
|
||||
* RETURNS: The current irq level
|
||||
*/
|
||||
{
|
||||
return(KeGetPcr()->Irql);
|
||||
}
|
||||
|
||||
VOID NTAPI HalpInitPICs(VOID)
|
||||
{
|
||||
memset(HalpPendingInterruptCount, 0, sizeof(HalpPendingInterruptCount));
|
||||
|
||||
/* Initialization sequence */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x20, 0x11);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa0, 0x11);
|
||||
/* Start of hardware irqs (0x24) */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, IRQ_BASE);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, IRQ_BASE + 8);
|
||||
/* 8259-1 is master */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, 0x4);
|
||||
/* 8259-2 is slave */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x2);
|
||||
/* 8086 mode */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, 0x1);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0x1);
|
||||
/* Enable interrupts */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, 0xFF);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, 0xFF);
|
||||
|
||||
/* We can now enable interrupts */
|
||||
_enable();
|
||||
}
|
||||
|
||||
VOID HalpEndSystemInterrupt(KIRQL Irql)
|
||||
/*
|
||||
* FUNCTION: Enable all irqs with higher priority.
|
||||
*/
|
||||
{
|
||||
const USHORT mask[] =
|
||||
{
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x8000, 0xc000, 0xe000, 0xf000,
|
||||
0xf800, 0xfc00, 0xfe00, 0xff00, 0xff80, 0xffc0, 0xffe0, 0xfff0,
|
||||
0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
|
||||
};
|
||||
|
||||
/* Interrupts should be disable while enabling irqs of both pics */
|
||||
_disable();
|
||||
|
||||
pic_mask_intr.both &= mask[Irql];
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
|
||||
|
||||
/* restore ints */
|
||||
_enable();
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt30(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x30");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt31(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x31");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt32(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x32");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt33(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x33");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt34(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x34");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt35(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x35");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt36(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x36");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt37(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x37");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt38(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x38");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt39(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x39");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt3A(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x3A");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt3B(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x3B");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt3C(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x3C");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt3D(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x3D");
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt3E(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x3E");
|
||||
while (TRUE);
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpHardwareInt3F(VOID)
|
||||
{
|
||||
__asm__ __volatile__ ("int $0x3F");
|
||||
}
|
||||
|
||||
|
||||
typedef VOID (*PHARDWARE_INT)(VOID);
|
||||
|
||||
PHARDWARE_INT HalpHardwareInt[NR_IRQS] =
|
||||
{
|
||||
HalpHardwareInt30,
|
||||
HalpHardwareInt31,
|
||||
HalpHardwareInt32,
|
||||
HalpHardwareInt33,
|
||||
HalpHardwareInt34,
|
||||
HalpHardwareInt35,
|
||||
HalpHardwareInt36,
|
||||
HalpHardwareInt37,
|
||||
HalpHardwareInt38,
|
||||
HalpHardwareInt39,
|
||||
HalpHardwareInt3A,
|
||||
HalpHardwareInt3B,
|
||||
HalpHardwareInt3C,
|
||||
HalpHardwareInt3D,
|
||||
HalpHardwareInt3E,
|
||||
HalpHardwareInt3F
|
||||
};
|
||||
|
||||
VOID
|
||||
HalpExecuteIrqs(KIRQL NewIrql)
|
||||
{
|
||||
ULONG IrqLimit, i;
|
||||
IrqLimit = min(PROFILE_LEVEL - NewIrql, NR_IRQS);
|
||||
|
||||
/*
|
||||
* For each irq if there have been any deferred interrupts then now
|
||||
* dispatch them.
|
||||
*/
|
||||
for (i = 0; i < IrqLimit; i++)
|
||||
{
|
||||
if (HalpPendingInterruptCount[i] > 0)
|
||||
{
|
||||
KeGetPcr()->Irql = (KIRQL)IRQ_TO_DIRQL(i);
|
||||
|
||||
while (HalpPendingInterruptCount[i] > 0)
|
||||
{
|
||||
/*
|
||||
* For each deferred interrupt execute all the handlers at DIRQL.
|
||||
*/
|
||||
HalpPendingInterruptCount[i]--;
|
||||
HalpHardwareInt[i]();
|
||||
}
|
||||
//KeGetPcr()->Irql--;
|
||||
//HalpEndSystemInterrupt(KeGetPcr()->Irql);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
HalpLowerIrql(KIRQL NewIrql)
|
||||
{
|
||||
if (NewIrql >= PROFILE_LEVEL)
|
||||
{
|
||||
KeGetPcr()->Irql = NewIrql;
|
||||
return;
|
||||
}
|
||||
HalpExecuteIrqs(NewIrql);
|
||||
if (NewIrql >= DISPATCH_LEVEL)
|
||||
{
|
||||
KeGetPcr()->Irql = NewIrql;
|
||||
return;
|
||||
}
|
||||
KeGetPcr()->Irql = DISPATCH_LEVEL;
|
||||
if (((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST])
|
||||
{
|
||||
((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST] = FALSE;
|
||||
KiDispatchInterrupt();
|
||||
}
|
||||
KeGetPcr()->Irql = APC_LEVEL;
|
||||
if (NewIrql == APC_LEVEL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
if (KeGetCurrentThread() != NULL &&
|
||||
KeGetCurrentThread()->ApcState.KernelApcPending)
|
||||
{
|
||||
KiDeliverApc(KernelMode, NULL, NULL);
|
||||
}
|
||||
KeGetPcr()->Irql = PASSIVE_LEVEL;
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KfLowerIrql
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Restores the irq level on the current processor
|
||||
*
|
||||
* ARGUMENTS
|
||||
* NewIrql = Irql to lower to
|
||||
*
|
||||
* RETURN VALUE
|
||||
* None
|
||||
*
|
||||
* NOTES
|
||||
* Uses fastcall convention
|
||||
*/
|
||||
VOID FASTCALL
|
||||
KfLowerIrql (KIRQL NewIrql)
|
||||
{
|
||||
DPRINT("KfLowerIrql(NewIrql %d)\n", NewIrql);
|
||||
|
||||
if (NewIrql > KeGetPcr()->Irql)
|
||||
{
|
||||
DbgPrint ("(%s:%d) NewIrql %x CurrentIrql %x\n",
|
||||
__FILE__, __LINE__, NewIrql, KeGetPcr()->Irql);
|
||||
KEBUGCHECK(0);
|
||||
for(;;);
|
||||
}
|
||||
|
||||
HalpLowerIrql(NewIrql);
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KfRaiseIrql
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Raises the hardware priority (irql)
|
||||
*
|
||||
* ARGUMENTS
|
||||
* NewIrql = Irql to raise to
|
||||
*
|
||||
* RETURN VALUE
|
||||
* previous irq level
|
||||
*
|
||||
* NOTES
|
||||
* Uses fastcall convention
|
||||
*/
|
||||
|
||||
KIRQL FASTCALL
|
||||
KfRaiseIrql (KIRQL NewIrql)
|
||||
{
|
||||
KIRQL OldIrql;
|
||||
|
||||
DPRINT("KfRaiseIrql(NewIrql %d)\n", NewIrql);
|
||||
|
||||
if (NewIrql < KeGetPcr()->Irql)
|
||||
{
|
||||
DbgPrint ("%s:%d CurrentIrql %x NewIrql %x\n",
|
||||
__FILE__,__LINE__,KeGetPcr()->Irql,NewIrql);
|
||||
KEBUGCHECK (0);
|
||||
for(;;);
|
||||
}
|
||||
|
||||
OldIrql = KeGetPcr()->Irql;
|
||||
KeGetPcr()->Irql = NewIrql;
|
||||
return OldIrql;
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KeRaiseIrqlToDpcLevel
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Raises the hardware priority (irql) to DISPATCH level
|
||||
*
|
||||
* ARGUMENTS
|
||||
* None
|
||||
*
|
||||
* RETURN VALUE
|
||||
* Previous irq level
|
||||
*
|
||||
* NOTES
|
||||
* Calls KfRaiseIrql
|
||||
*/
|
||||
|
||||
KIRQL STDCALL
|
||||
KeRaiseIrqlToDpcLevel (VOID)
|
||||
{
|
||||
return KfRaiseIrql (DISPATCH_LEVEL);
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************
|
||||
* NAME EXPORTED
|
||||
* KeRaiseIrqlToSynchLevel
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Raises the hardware priority (irql) to CLOCK2 level
|
||||
*
|
||||
* ARGUMENTS
|
||||
* None
|
||||
*
|
||||
* RETURN VALUE
|
||||
* Previous irq level
|
||||
*
|
||||
* NOTES
|
||||
* Calls KfRaiseIrql
|
||||
*/
|
||||
|
||||
KIRQL STDCALL
|
||||
KeRaiseIrqlToSynchLevel (VOID)
|
||||
{
|
||||
return KfRaiseIrql (DISPATCH_LEVEL);
|
||||
}
|
||||
|
||||
|
||||
BOOLEAN STDCALL
|
||||
HalBeginSystemInterrupt (KIRQL Irql,
|
||||
ULONG Vector,
|
||||
PKIRQL OldIrql)
|
||||
{
|
||||
ULONG irq;
|
||||
if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
|
||||
{
|
||||
return(FALSE);
|
||||
}
|
||||
irq = Vector - IRQ_BASE;
|
||||
pic_mask_intr.both |= ((1 << irq) & 0xfffe); // do not disable the timer interrupt
|
||||
|
||||
if (irq < 8)
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x20, 0x20);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
|
||||
/* Send EOI to the PICs */
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x20,0x20);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa0,0x20);
|
||||
}
|
||||
#if 0
|
||||
if (KeGetPcr()->Irql >= Irql)
|
||||
{
|
||||
HalpPendingInterruptCount[irq]++;
|
||||
return(FALSE);
|
||||
}
|
||||
#endif
|
||||
*OldIrql = KeGetPcr()->Irql;
|
||||
KeGetPcr()->Irql = Irql;
|
||||
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
|
||||
VOID STDCALL HalEndSystemInterrupt (KIRQL Irql, ULONG Unknown2)
|
||||
/*
|
||||
* FUNCTION: Finish a system interrupt and restore the specified irq level.
|
||||
*/
|
||||
{
|
||||
HalpLowerIrql(Irql);
|
||||
HalpEndSystemInterrupt(Irql);
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
STDCALL
|
||||
HalDisableSystemInterrupt(
|
||||
ULONG Vector,
|
||||
KIRQL Irql)
|
||||
{
|
||||
ULONG irq;
|
||||
|
||||
if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
|
||||
return FALSE;
|
||||
|
||||
irq = Vector - IRQ_BASE;
|
||||
pic_mask.both |= (1 << irq);
|
||||
if (irq < 8)
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.slave));
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
BOOLEAN
|
||||
STDCALL
|
||||
HalEnableSystemInterrupt(
|
||||
ULONG Vector,
|
||||
KIRQL Irql,
|
||||
KINTERRUPT_MODE InterruptMode)
|
||||
{
|
||||
ULONG irq;
|
||||
|
||||
if (Vector < IRQ_BASE || Vector >= IRQ_BASE + NR_IRQS)
|
||||
return FALSE;
|
||||
|
||||
irq = Vector - IRQ_BASE;
|
||||
pic_mask.both &= ~(1 << irq);
|
||||
if (irq < 8)
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0x21, (UCHAR)(pic_mask.master|pic_mask_intr.master));
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xa1, (UCHAR)(pic_mask.slave|pic_mask_intr.slave));
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
VOID FASTCALL
|
||||
HalRequestSoftwareInterrupt(
|
||||
IN KIRQL Request)
|
||||
{
|
||||
switch (Request)
|
||||
{
|
||||
case APC_LEVEL:
|
||||
((PKIPCR)KeGetPcr())->HalReserved[HAL_APC_REQUEST] = TRUE;
|
||||
break;
|
||||
|
||||
case DISPATCH_LEVEL:
|
||||
((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST] = TRUE;
|
||||
break;
|
||||
|
||||
default:
|
||||
KEBUGCHECK(0);
|
||||
}
|
||||
}
|
||||
|
||||
VOID FASTCALL
|
||||
HalClearSoftwareInterrupt(
|
||||
IN KIRQL Request)
|
||||
{
|
||||
switch (Request)
|
||||
{
|
||||
case APC_LEVEL:
|
||||
((PKIPCR)KeGetPcr())->HalReserved[HAL_APC_REQUEST] = FALSE;
|
||||
break;
|
||||
|
||||
case DISPATCH_LEVEL:
|
||||
((PKIPCR)KeGetPcr())->HalReserved[HAL_DPC_REQUEST] = FALSE;
|
||||
break;
|
||||
|
||||
default:
|
||||
KEBUGCHECK(0);
|
||||
}
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
Loading…
Reference in a new issue