- Add initial support for TI OMAP3530 (last commit said OMAP3450, this was incorrect), an ARM Cortex-A8 based SoC.

- This gets us booting to FreeLDR with some serial output.
  - The entire MMU code needs a rewrite.

svn path=/trunk/; revision=41983

reactos/boot/freeldr/freeldr/arch/arm/boot.s

@@ -10,7 +10,6 @@
     .include "ntoskrnl/include/internal/arm/kxarm.h"
     .include "ntoskrnl/include/internal/arm/ksarm.h"
 
-    .section startup
     NESTED_ENTRY _start
     PROLOG_END _start
     
@@ -45,7 +44,7 @@
     //
     // Okay, now give us a stack
     //
-    ldr sp, L_BootStackEnd
+    //ldr sp, L_BootStackEnd
 
     //
     // Go ahead and call the C initialization code
@@ -60,13 +59,6 @@ L_BootStackEnd:
 L_ArmInit:
     .long ArmInit
 
-	.align 4
-.global BootStack
-BootStack:
-	.space 0x4000
-BootStackEnd:
-    .long 0
-
 .section pagedata
 .global TranslationTableStart
 TranslationTableStart:

reactos/boot/freeldr/freeldr/arch/arm/macharm.c

@@ -12,6 +12,8 @@
 
 /* GLOBALS ********************************************************************/
 
+UCHAR BootStack[0x4000];
+PUCHAR BootStackEnd = &BootStack[0x3FFF];
 PARM_BOARD_CONFIGURATION_BLOCK ArmBoardBlock;
 ULONG BootDrive, BootPartition;
 VOID ArmPrepareForReactOS(IN BOOLEAN Setup);
@@ -40,7 +42,8 @@ ArmInit(IN PARM_BOARD_CONFIGURATION_BLOCK BootContext)
     // This should probably go away once we support more boards
     //
     ASSERT((ArmBoardBlock->BoardType == MACH_TYPE_FEROCEON) ||
-           (ArmBoardBlock->BoardType == MACH_TYPE_VERSATILE_PB));
+           (ArmBoardBlock->BoardType == MACH_TYPE_VERSATILE_PB) ||
+           (ArmBoardBlock->BoardType == MACH_TYPE_OMAP3_BEAGLE));
 
     //
     // Save data required for memory initialization
@@ -169,10 +172,25 @@ MachInit(IN PCCH CommandLine)
             MachVtbl.ConsGetCh = ArmVersaGetCh;
             break;
             
+        //
+        // Check for TI OMAP3 boards
+        // For now that means only Beagle, but ZOOM and others should be ok too
+        //
+        case MACH_TYPE_OMAP3_BEAGLE:
+            
+            //
+            // These boards use a UART16550
+            //
+            ArmOmap3SerialInit(115200);
+            MachVtbl.ConsPutChar = ArmOmap3PutChar;
+            MachVtbl.ConsKbHit = ArmOmap3KbHit;
+            MachVtbl.ConsGetCh = ArmOmap3GetCh;
+            break;
+            
         default:
             ASSERT(FALSE);
     }
-    
+        
     //
     // Setup generic ARM routines for all boards
     //

reactos/boot/freeldr/freeldr/arch/arm/omapuart.c

@@ -0,0 +1,162 @@
+/*
+ * PROJECT:         ReactOS Boot Loader
+ * LICENSE:         BSD - See COPYING.ARM in the top level directory
+ * FILE:            boot/freeldr/arch/arm/omapuart.c
+ * PURPOSE:         Implements code for TI OMAP3 boards using the 16550 UART
+ * PROGRAMMERS:     ReactOS Portable Systems Group
+ */
+
+/* INCLUDES *******************************************************************/
+
+#include <freeldr.h>
+
+/* GLOBALS ********************************************************************/
+
+//
+// UART Registers
+//
+#define UART0_RHR   (ArmBoardBlock->UartRegisterBase + 0x00)
+#define UART0_THR   UART0_RHR
+#define UART0_IER   (ArmBoardBlock->UartRegisterBase + 0x04)
+#define UART0_FCR   (ArmBoardBlock->UartRegisterBase + 0x08)
+#define UART0_LCR   (ArmBoardBlock->UartRegisterBase + 0x0C)
+#define UART0_MCR   (ArmBoardBlock->UartRegisterBase + 0x10)
+#define UART0_LSR   (ArmBoardBlock->UartRegisterBase + 0x14)
+#define UART0_MDR1  (ArmBoardBlock->UartRegisterBase + 0x20)
+
+//
+// When we enable the divisor latch
+//
+#define UART0_DLL   UART0_RHR
+#define UART0_DLH   UART0_IER
+
+//
+// FCR Values
+//
+#define FCR_FIFO_EN 0x01
+#define FCR_RXSR    0x02
+#define FCR_TXSR    0x04
+
+//
+// LCR Values
+//
+#define LCR_WLS_8   0x03
+#define LCR_1_STB   0x00
+#define LCR_DIVL_EN 0x80
+#define LCR_NO_PAR  0x00
+
+//
+// LSR Values
+//
+#define LSR_DR      0x01
+#define LSR_THRE    0x20
+
+//
+// MCR Values
+//
+#define MCR_DTR     0x01
+#define MCR_RTS     0x02
+
+//
+// MDR1 Modes
+//
+#define MDR1_UART16X            1
+#define MDR1_SIR                2
+#define MDR1_UART16X_AUTO_BAUD  3
+#define MDR1_UART13X            4
+#define MDR1_MIR                5
+#define MDR1_FIR                6
+#define MDR1_CIR                7
+#define MDR1_DISABLE            8
+
+/* FUNCTIONS ******************************************************************/
+
+VOID
+ArmOmap3SerialInit(IN ULONG Baudrate)
+{
+    ULONG BaudClock;
+    
+    //
+    // Calculate baudrate clock divider to set the baud rate
+    //
+    BaudClock = (ArmBoardBlock->ClockRate / 16) / Baudrate;
+    
+    //
+    // Disable serial port
+    //
+    WRITE_REGISTER_UCHAR(UART0_MDR1, MDR1_DISABLE);
+    
+    //
+    // Disable interrupts
+    //
+    WRITE_REGISTER_UCHAR(UART0_IER, 0);
+    
+    //
+    // Set the baud rate to 115200 bps
+    //
+    WRITE_REGISTER_UCHAR(UART0_LCR, LCR_DIVL_EN);
+    WRITE_REGISTER_UCHAR(UART0_DLL, BaudClock);
+    WRITE_REGISTER_UCHAR(UART0_DLH, (BaudClock >> 8) & 0xFF);
+    
+    //
+    // Setup loopback
+    //
+    WRITE_REGISTER_UCHAR(UART0_MCR, MCR_DTR | MCR_RTS);
+    
+    //
+    // Set 8 bits for data, 1 stop bit, no parity
+    //
+    WRITE_REGISTER_UCHAR(UART0_LCR, LCR_WLS_8 | LCR_1_STB | LCR_NO_PAR);
+    
+    //
+    // Clear and enable FIFO
+    //
+    WRITE_REGISTER_UCHAR(UART0_FCR, FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
+    
+    //
+    // Enable serial port
+    //
+    WRITE_REGISTER_UCHAR(UART0_MDR1, MDR1_UART16X);
+}
+
+VOID
+ArmOmap3PutChar(IN INT Char)
+{
+    //
+    // Properly support new-lines
+    //
+    if (Char == '\n') ArmOmap3PutChar('\r');
+    
+    //
+    // Wait for ready
+    //
+    while ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_THRE) == 0);
+    
+    //
+    // Send the character
+    //
+    WRITE_REGISTER_UCHAR(UART0_THR, Char);
+}
+
+INT
+ArmOmap3GetCh(VOID)
+{
+    //
+    // Wait for ready
+    //
+    while ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_DR) == 0);
+    
+    //
+    // Read the character
+    //
+    return READ_REGISTER_UCHAR(UART0_RHR);
+}
+
+BOOLEAN
+ArmOmap3KbHit(VOID)
+{
+    //
+    // Return if something is ready
+    //
+    return ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_DR) != 0);
+}

reactos/boot/freeldr/freeldr/freeldr_arch.rbuild

@@ -69,10 +69,11 @@
 		</directory>
 		<directory name="arm">
 			<if property="ARCH" value="arm">
-				<file>boot.s</file>
+				<file first="true">boot.s</file>
 				<file>ferouart.c</file>
 				<file>loader.c</file>
 				<file>macharm.c</file>
+				<file>omapuart.c</file>
 				<file>versuart.c</file>
 			</if>
 		</directory>

reactos/boot/freeldr/freeldr/include/arch/arm/hardware.h

@@ -25,6 +25,12 @@
 //
 #define MACH_TYPE_VERSATILE_PB 387
 
+//
+// TI Beagle Board, OMAP3530 SoC
+// qemu-system-arm -M beagle, Beagle Board
+//
+#define MACH_TYPE_OMAP3_BEAGLE 1546
+
 //
 // Compatible boot-loaders should return us this information
 //
@@ -105,6 +111,18 @@ ArmFeroGetCh(VOID);
 BOOLEAN
 ArmFeroKbHit(VOID);
 
+VOID
+ArmOmap3SerialInit(IN ULONG Baudrate);
+
+VOID
+ArmOmap3PutChar(IN INT Char);
+
+INT
+ArmOmap3GetCh(VOID);
+
+BOOLEAN
+ArmOmap3KbHit(VOID);
+
 VOID
 ArmVersaSerialInit(IN ULONG Baudrate);
 

reactos/boot/freeldr/freeldr/machine.c

@@ -169,10 +169,10 @@ static const MEMORY_DESCRIPTOR_INT MemoryDescriptors[] =
     { { MemoryFirmwareTemporary, 0x90, 0x10 }, 5, }, // Disk read buffer for int 13h. DISKREADBUFFER
     { { MemoryFirmwarePermanent, 0xA0, 0x60 }, 6, }, // ROM / Video
     { { MemorySpecialMemory, 0xFFF, 1 }, 7, }, // unusable memory
-#elif __arm__
+#elif __arm__ // This needs to be done per-platform specific way
-    { { MemoryFirmwarePermanent, 0x00, 1 }, 0, }, // arm exception handlers
+    { { MemoryLoadedProgram, 0x80000, 32 }, 0, }, // X-Loader + OmapLdr
-    { { MemoryFirmwareTemporary, 0x01, 7 }, 1, }, // arm board block + freeldr stack + cmdline
+    { { MemoryLoadedProgram, 0x81000, 128 }, 1, }, // FreeLDR
-    { { MemoryLoadedProgram, 0x08, 0x70 }, 2, }, // freeldr image (roughly max. 0x64 pages)
+    { { MemoryFirmwareTemporary, 0x80500, 4096 }, 2, }, // Video Buffer
 #endif
 };
 MEMORY_DESCRIPTOR*