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- Add initial support for TI OMAP3530 (last commit said OMAP3450, this was incorrect), an ARM Cortex-A8 based SoC.
- This gets us booting to FreeLDR with some serial output. - The entire MMU code needs a rewrite. svn path=/trunk/; revision=41983
This commit is contained in:
ReactOS Portable Systems Group
parent
4c1ac0d33e
commit
cc98ebfe87
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@ -10,7 +10,6 @@
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.include "ntoskrnl/include/internal/arm/kxarm.h"
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.include "ntoskrnl/include/internal/arm/ksarm.h"
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.section startup
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NESTED_ENTRY _start
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PROLOG_END _start
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@ -45,7 +44,7 @@
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//
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// Okay, now give us a stack
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//
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ldr sp, L_BootStackEnd
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//ldr sp, L_BootStackEnd
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//
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// Go ahead and call the C initialization code
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@ -60,13 +59,6 @@ L_BootStackEnd:
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L_ArmInit:
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.long ArmInit
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.align 4
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.global BootStack
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BootStack:
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.space 0x4000
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BootStackEnd:
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.long 0
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.section pagedata
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.global TranslationTableStart
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TranslationTableStart:
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@ -12,6 +12,8 @@
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/* GLOBALS ********************************************************************/
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UCHAR BootStack[0x4000];
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PUCHAR BootStackEnd = &BootStack[0x3FFF];
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PARM_BOARD_CONFIGURATION_BLOCK ArmBoardBlock;
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ULONG BootDrive, BootPartition;
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VOID ArmPrepareForReactOS(IN BOOLEAN Setup);
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@ -40,7 +42,8 @@ ArmInit(IN PARM_BOARD_CONFIGURATION_BLOCK BootContext)
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// This should probably go away once we support more boards
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//
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ASSERT((ArmBoardBlock->BoardType == MACH_TYPE_FEROCEON) ||
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(ArmBoardBlock->BoardType == MACH_TYPE_VERSATILE_PB));
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(ArmBoardBlock->BoardType == MACH_TYPE_VERSATILE_PB) ||
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(ArmBoardBlock->BoardType == MACH_TYPE_OMAP3_BEAGLE));
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//
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// Save data required for memory initialization
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@ -169,10 +172,25 @@ MachInit(IN PCCH CommandLine)
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MachVtbl.ConsGetCh = ArmVersaGetCh;
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break;
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//
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// Check for TI OMAP3 boards
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// For now that means only Beagle, but ZOOM and others should be ok too
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//
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case MACH_TYPE_OMAP3_BEAGLE:
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//
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// These boards use a UART16550
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//
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ArmOmap3SerialInit(115200);
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MachVtbl.ConsPutChar = ArmOmap3PutChar;
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MachVtbl.ConsKbHit = ArmOmap3KbHit;
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MachVtbl.ConsGetCh = ArmOmap3GetCh;
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break;
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default:
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ASSERT(FALSE);
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}
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//
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// Setup generic ARM routines for all boards
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//
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162
reactos/boot/freeldr/freeldr/arch/arm/omapuart.c
Normal file
162
reactos/boot/freeldr/freeldr/arch/arm/omapuart.c
Normal file
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@ -0,0 +1,162 @@
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/*
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* PROJECT: ReactOS Boot Loader
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: boot/freeldr/arch/arm/omapuart.c
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* PURPOSE: Implements code for TI OMAP3 boards using the 16550 UART
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <freeldr.h>
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/* GLOBALS ********************************************************************/
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//
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// UART Registers
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//
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#define UART0_RHR (ArmBoardBlock->UartRegisterBase + 0x00)
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#define UART0_THR UART0_RHR
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#define UART0_IER (ArmBoardBlock->UartRegisterBase + 0x04)
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#define UART0_FCR (ArmBoardBlock->UartRegisterBase + 0x08)
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#define UART0_LCR (ArmBoardBlock->UartRegisterBase + 0x0C)
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#define UART0_MCR (ArmBoardBlock->UartRegisterBase + 0x10)
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#define UART0_LSR (ArmBoardBlock->UartRegisterBase + 0x14)
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#define UART0_MDR1 (ArmBoardBlock->UartRegisterBase + 0x20)
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//
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// When we enable the divisor latch
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//
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#define UART0_DLL UART0_RHR
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#define UART0_DLH UART0_IER
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//
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// FCR Values
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//
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#define FCR_FIFO_EN 0x01
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#define FCR_RXSR 0x02
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#define FCR_TXSR 0x04
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//
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// LCR Values
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//
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#define LCR_WLS_8 0x03
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#define LCR_1_STB 0x00
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#define LCR_DIVL_EN 0x80
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#define LCR_NO_PAR 0x00
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//
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// LSR Values
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//
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#define LSR_DR 0x01
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#define LSR_THRE 0x20
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//
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// MCR Values
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//
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#define MCR_DTR 0x01
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#define MCR_RTS 0x02
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//
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// MDR1 Modes
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//
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#define MDR1_UART16X 1
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#define MDR1_SIR 2
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#define MDR1_UART16X_AUTO_BAUD 3
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#define MDR1_UART13X 4
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#define MDR1_MIR 5
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#define MDR1_FIR 6
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#define MDR1_CIR 7
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#define MDR1_DISABLE 8
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/* FUNCTIONS ******************************************************************/
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VOID
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ArmOmap3SerialInit(IN ULONG Baudrate)
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{
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ULONG BaudClock;
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//
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// Calculate baudrate clock divider to set the baud rate
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//
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BaudClock = (ArmBoardBlock->ClockRate / 16) / Baudrate;
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//
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// Disable serial port
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//
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WRITE_REGISTER_UCHAR(UART0_MDR1, MDR1_DISABLE);
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//
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// Disable interrupts
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//
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WRITE_REGISTER_UCHAR(UART0_IER, 0);
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//
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// Set the baud rate to 115200 bps
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//
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WRITE_REGISTER_UCHAR(UART0_LCR, LCR_DIVL_EN);
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WRITE_REGISTER_UCHAR(UART0_DLL, BaudClock);
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WRITE_REGISTER_UCHAR(UART0_DLH, (BaudClock >> 8) & 0xFF);
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//
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// Setup loopback
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//
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WRITE_REGISTER_UCHAR(UART0_MCR, MCR_DTR | MCR_RTS);
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//
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// Set 8 bits for data, 1 stop bit, no parity
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//
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WRITE_REGISTER_UCHAR(UART0_LCR, LCR_WLS_8 | LCR_1_STB | LCR_NO_PAR);
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//
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// Clear and enable FIFO
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//
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WRITE_REGISTER_UCHAR(UART0_FCR, FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
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//
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// Enable serial port
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//
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WRITE_REGISTER_UCHAR(UART0_MDR1, MDR1_UART16X);
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}
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VOID
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ArmOmap3PutChar(IN INT Char)
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{
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//
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// Properly support new-lines
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//
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if (Char == '\n') ArmOmap3PutChar('\r');
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//
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// Wait for ready
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//
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while ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_THRE) == 0);
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//
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// Send the character
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//
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WRITE_REGISTER_UCHAR(UART0_THR, Char);
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}
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INT
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ArmOmap3GetCh(VOID)
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{
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//
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// Wait for ready
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//
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while ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_DR) == 0);
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//
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// Read the character
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//
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return READ_REGISTER_UCHAR(UART0_RHR);
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}
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BOOLEAN
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ArmOmap3KbHit(VOID)
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{
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//
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// Return if something is ready
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//
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return ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_DR) != 0);
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}
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@ -69,10 +69,11 @@
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</directory>
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<directory name="arm">
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<if property="ARCH" value="arm">
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<file>boot.s</file>
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<file first="true">boot.s</file>
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<file>ferouart.c</file>
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<file>loader.c</file>
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<file>macharm.c</file>
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<file>omapuart.c</file>
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<file>versuart.c</file>
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</if>
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</directory>
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@ -25,6 +25,12 @@
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//
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#define MACH_TYPE_VERSATILE_PB 387
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//
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// TI Beagle Board, OMAP3530 SoC
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// qemu-system-arm -M beagle, Beagle Board
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//
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#define MACH_TYPE_OMAP3_BEAGLE 1546
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//
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// Compatible boot-loaders should return us this information
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//
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@ -105,6 +111,18 @@ ArmFeroGetCh(VOID);
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BOOLEAN
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ArmFeroKbHit(VOID);
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VOID
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ArmOmap3SerialInit(IN ULONG Baudrate);
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VOID
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ArmOmap3PutChar(IN INT Char);
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INT
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ArmOmap3GetCh(VOID);
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BOOLEAN
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ArmOmap3KbHit(VOID);
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VOID
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ArmVersaSerialInit(IN ULONG Baudrate);
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@ -169,10 +169,10 @@ static const MEMORY_DESCRIPTOR_INT MemoryDescriptors[] =
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{ { MemoryFirmwareTemporary, 0x90, 0x10 }, 5, }, // Disk read buffer for int 13h. DISKREADBUFFER
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{ { MemoryFirmwarePermanent, 0xA0, 0x60 }, 6, }, // ROM / Video
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{ { MemorySpecialMemory, 0xFFF, 1 }, 7, }, // unusable memory
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#elif __arm__
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{ { MemoryFirmwarePermanent, 0x00, 1 }, 0, }, // arm exception handlers
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{ { MemoryFirmwareTemporary, 0x01, 7 }, 1, }, // arm board block + freeldr stack + cmdline
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{ { MemoryLoadedProgram, 0x08, 0x70 }, 2, }, // freeldr image (roughly max. 0x64 pages)
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#elif __arm__ // This needs to be done per-platform specific way
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{ { MemoryLoadedProgram, 0x80000, 32 }, 0, }, // X-Loader + OmapLdr
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{ { MemoryLoadedProgram, 0x81000, 128 }, 1, }, // FreeLDR
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{ { MemoryFirmwareTemporary, 0x80500, 4096 }, 2, }, // Video Buffer
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#endif
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};
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MEMORY_DESCRIPTOR*
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