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[FAST486]
Implement opcode 0xDE (New instructions: FADDP, FMULP, FCOMPP, FSUBRP, FSUBP, FDIVRP and FDIVP). Fix a bug in the 0xD8/0xDC opcode handler. svn path=/trunk/; revision=65934
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@ -423,6 +423,13 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeD8DC)
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#ifndef FAST486_NO_FPU
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if (FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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{
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/* Invalid operation */
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State->FpuStatus.Ie = TRUE;
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return;
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}
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if (ModRegRm.Memory)
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{
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/* Load the source operand from memory */
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@ -459,28 +466,35 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeD8DC)
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}
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SourceOperand = &MemoryData;
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/* The destination operand is ST0 */
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DestOperand = &FPU_ST(0);
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}
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else
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{
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/* Load the source operand from an FPU register */
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SourceOperand = &FPU_ST(ModRegRm.SecondRegister);
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if (FPU_GET_TAG(ModRegRm.SecondRegister) == FPU_TAG_EMPTY)
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{
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/* Invalid operation */
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State->FpuStatus.Ie = TRUE;
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return;
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}
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}
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/* The destination operand is always ST0 */
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DestOperand = &FPU_ST(0);
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if (Opcode == 0xDC)
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{
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/* The source operand is ST0 */
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SourceOperand = &FPU_ST(0);
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if (FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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{
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/* Invalid operation */
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State->FpuStatus.Ie = TRUE;
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return;
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/* Load the destination operand from an FPU register */
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DestOperand = &FPU_ST(ModRegRm.SecondRegister);
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}
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else
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{
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/* Load the source operand from an FPU register */
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SourceOperand = &FPU_ST(ModRegRm.SecondRegister);
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/* The destination operand is ST0 */
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DestOperand = &FPU_ST(0);
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}
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}
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/* Check the operation */
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@ -912,6 +926,8 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDE)
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{
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FAST486_MOD_REG_RM ModRegRm;
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BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
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PFAST486_FPU_DATA_REG SourceOperand, DestOperand;
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BOOLEAN PopStack = FALSE;
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/* Get the operands */
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if (!Fast486ParseModRegRm(State, AddressSize, &ModRegRm))
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@ -923,10 +939,117 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDE)
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FPU_CHECK();
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#ifndef FAST486_NO_FPU
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// TODO: NOT IMPLEMENTED
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UNIMPLEMENTED;
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#else
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/* Do nothing */
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if (FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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{
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/* Invalid operation */
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State->FpuStatus.Ie = TRUE;
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return;
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}
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if (ModRegRm.Memory)
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{
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SHORT Value;
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FAST486_FPU_DATA_REG MemoryData;
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/* Load the source operand from memory */
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if (!Fast486ReadModrmWordOperands(State, &ModRegRm, NULL, (PUSHORT)&Value))
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{
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/* Exception occurred */
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return;
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}
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Fast486FpuFromInteger(State, (LONGLONG)Value, &MemoryData);
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SourceOperand = &MemoryData;
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/* The destination operand is ST0 */
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DestOperand = &FPU_ST(0);
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}
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else
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{
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/* FCOMPP check */
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if ((ModRegRm.Register == 3) && (ModRegRm.SecondRegister != 1))
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{
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/* Invalid */
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Fast486Exception(State, FAST486_EXCEPTION_UD);
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return;
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}
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/* The source operand is ST0 */
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SourceOperand = &FPU_ST(0);
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/* Load the destination operand from a register */
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DestOperand = &FPU_ST(ModRegRm.SecondRegister);
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if (FPU_GET_TAG(ModRegRm.SecondRegister) == FPU_TAG_EMPTY)
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{
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/* Invalid operation */
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State->FpuStatus.Ie = TRUE;
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return;
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}
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PopStack = TRUE;
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}
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/* Check the operation */
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switch (ModRegRm.Register)
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{
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/* FIADD / FADDP */
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case 0:
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{
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Fast486FpuAdd(State, DestOperand, SourceOperand, DestOperand);
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break;
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}
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/* FIMUL / FMULP */
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case 1:
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{
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Fast486FpuMultiply(State, DestOperand, SourceOperand, DestOperand);
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break;
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}
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/* FICOM / FCOMP */
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case 2:
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/* FICOMP / FCOMPP */
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case 3:
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{
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Fast486FpuCompare(State, DestOperand, SourceOperand);
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if (ModRegRm.Register == 3) Fast486FpuPop(State);
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break;
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}
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/* FISUB / FSUBRP */
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case 4:
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{
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Fast486FpuSubtract(State, DestOperand, SourceOperand, DestOperand);
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break;
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}
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/* FISUBR / FSUBP */
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case 5:
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{
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Fast486FpuSubtract(State, SourceOperand, DestOperand, DestOperand);
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break;
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}
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/* FIDIV / FDIVRP */
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case 6:
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{
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Fast486FpuDivide(State, DestOperand, SourceOperand, DestOperand);
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break;
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}
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/* FIDIVR / FDIVP */
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case 7:
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{
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Fast486FpuDivide(State, SourceOperand, DestOperand, DestOperand);
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break;
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}
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}
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if (PopStack) Fast486FpuPop(State);
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#endif
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}
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