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- Convert the members of PCI_COMMON_HEADER into a #define to avoid inheritance on C++, which would render the type a non-POD, causing compilation errors.

Browse source 
- IoInitializeDpcRequest expects PIO_DPC_ROUTINE as 2nd parameter, fix callers.
- While FILE_CHARACTERISTIC_PNP_DEVICE is defined in the DDK/WDK, _SYSTEM_INFORMATION_CLASS is not, fix include guards in ntddk_ex.h
- add InterlockedBitTestAndSet64 and InterlockedBitTestAndReset64 for amd64
- Fix definition of NLS_MB_CODE_PAGE_TAG for gcc
- Fix parameters of DMA inline functions
- remove duplicate IoAllocateAdapterChannel
- Everything compiles again -> Amine, your turn :)

svn path=/branches/header-work/; revision=45858
This commit is contained in:
Timo Kreuzer 2010-03-05 04:03:34 +00:00
parent 7ff52a15bf
commit c76dfd5cb8
4 changed files with 104 additions and 146 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/base/beep/beep.c
View file

@ -393,7 +393,7 @@ DriverEntry(IN PDRIVER_OBJECT DriverObject,
DeviceExtension = DeviceObject->DeviceExtension; DeviceExtension = DeviceObject->DeviceExtension;
DeviceExtension->ReferenceCount = 0; DeviceExtension->ReferenceCount = 0;
DeviceExtension->TimerActive = FALSE; DeviceExtension->TimerActive = FALSE;
IoInitializeDpcRequest(DeviceObject, BeepDPC); IoInitializeDpcRequest(DeviceObject, (PIO_DPC_ROUTINE)BeepDPC);
KeInitializeTimer(&DeviceExtension->Timer); KeInitializeTimer(&DeviceExtension->Timer);
ExInitializeFastMutex(&DeviceExtension->Mutex); ExInitializeFastMutex(&DeviceExtension->Mutex);

2
drivers/storage/floppy/floppy.c
View file

@ -972,7 +972,7 @@ static BOOLEAN NTAPI AddControllers(PDRIVER_OBJECT DriverObject)
} }
/* 3e: Set up the DPC */ /* 3e: Set up the DPC */
IoInitializeDpcRequest(gControllerInfo[i].DriveInfo[j].DeviceObject, DpcForIsr); IoInitializeDpcRequest(gControllerInfo[i].DriveInfo[j].DeviceObject, (PIO_DPC_ROUTINE)DpcForIsr);
/* 3f: Point the device extension at our DriveInfo struct */ /* 3f: Point the device extension at our DriveInfo struct */
gControllerInfo[i].DriveInfo[j].DeviceObject->DeviceExtension = &gControllerInfo[i].DriveInfo[j]; gControllerInfo[i].DriveInfo[j].DeviceObject->DeviceExtension = &gControllerInfo[i].DriveInfo[j];

4
drivers/storage/ide/uniata/ntddk_ex.h
View file

@ -8,8 +8,8 @@
#endif #endif
#ifndef FILE_CHARACTERISTIC_PNP_DEVICE // DDK 2003 #ifndef FILE_CHARACTERISTIC_PNP_DEVICE // DDK 2003
#define FILE_CHARACTERISTIC_PNP_DEVICE 0x00000800 #define FILE_CHARACTERISTIC_PNP_DEVICE 0x00000800
#endif // !FILE_CHARACTERISTIC_PNP_DEVICE
typedef enum _SYSTEM_INFORMATION_CLASS { typedef enum _SYSTEM_INFORMATION_CLASS {
SystemBasicInformation, SystemBasicInformation,
@ -127,8 +127,6 @@ typedef enum _SYSTEM_INFORMATION_CLASS {
#endif //__REACTOS__ #endif //__REACTOS__
} SYSTEM_INFORMATION_CLASS; } SYSTEM_INFORMATION_CLASS;
#endif // !FILE_CHARACTERISTIC_PNP_DEVICE
NTSYSAPI NTSYSAPI
NTSTATUS NTSTATUS

242
include/ddk/wdm.h
View file

@ -68,6 +68,7 @@ struct _DEVICE_DESCRIPTION;
struct _SCATTER_GATHER_LIST; struct _SCATTER_GATHER_LIST;
struct _DRIVE_LAYOUT_INFORMATION; struct _DRIVE_LAYOUT_INFORMATION;
struct _COMPRESSED_DATA_INFO; struct _COMPRESSED_DATA_INFO;
struct _IO_RESOURCE_DESCRIPTOR;
/* Structures not exposed to drivers */ /* Structures not exposed to drivers */
typedef struct _OBJECT_TYPE *POBJECT_TYPE; typedef struct _OBJECT_TYPE *POBJECT_TYPE;
@ -133,7 +134,6 @@ InterlockedBitTestAndReset(IN LONG volatile *Base,
#endif #endif
#define BitScanForward _BitScanForward #define BitScanForward _BitScanForward
#define BitScanReverse _BitScanReverse #define BitScanReverse _BitScanReverse
#define BitTest _bittest #define BitTest _bittest
@ -143,6 +143,11 @@ InterlockedBitTestAndReset(IN LONG volatile *Base,
#define InterlockedBitTestAndSet _interlockedbittestandset #define InterlockedBitTestAndSet _interlockedbittestandset
#define InterlockedBitTestAndReset _interlockedbittestandreset #define InterlockedBitTestAndReset _interlockedbittestandreset
#ifdef _M_AMD64
#define InterlockedBitTestAndSet64 _interlockedbittestandset64
#define InterlockedBitTestAndReset64 _interlockedbittestandreset64
#endif
#if !defined(__INTERLOCKED_DECLARED) #if !defined(__INTERLOCKED_DECLARED)
#define __INTERLOCKED_DECLARED #define __INTERLOCKED_DECLARED
@ -1364,21 +1369,6 @@ ProbeForWrite(
#error Unsupported Architecture #error Unsupported Architecture
#endif #endif
#ifdef _NTSYSTEM_
#define NLS_MB_CODE_PAGE_TAG NlsMbCodePageTag
#define NLS_MB_OEM_CODE_PAGE_TAG NlsMbOemCodePageTag
#else
#define NLS_MB_CODE_PAGE_TAG (*NlsMbCodePageTag)
#define NLS_MB_OEM_CODE_PAGE_TAG (*NlsMbOemCodePageTag)
#endif /* _NTSYSTEM_ */
extern BOOLEAN NLS_MB_CODE_PAGE_TAG;
extern BOOLEAN NLS_MB_OEM_CODE_PAGE_TAG;
/****************************************************************************** /******************************************************************************
* Memory manager Types * * Memory manager Types *
@ -3568,7 +3558,7 @@ NTSYSAPI
ULONGLONG ULONGLONG
NTAPI NTAPI
RtlIoDecodeMemIoResource ( RtlIoDecodeMemIoResource (
IN PIO_RESOURCE_DESCRIPTOR Descriptor, IN struct _IO_RESOURCE_DESCRIPTOR *Descriptor,
OUT PULONGLONG Alignment OPTIONAL, OUT PULONGLONG Alignment OPTIONAL,
OUT PULONGLONG MinimumAddress OPTIONAL, OUT PULONGLONG MinimumAddress OPTIONAL,
OUT PULONGLONG MaximumAddress OPTIONAL); OUT PULONGLONG MaximumAddress OPTIONAL);
@ -3577,7 +3567,7 @@ NTSYSAPI
NTSTATUS NTSTATUS
NTAPI NTAPI
RtlIoEncodeMemIoResource( RtlIoEncodeMemIoResource(
IN PIO_RESOURCE_DESCRIPTOR Descriptor, IN struct _IO_RESOURCE_DESCRIPTOR *Descriptor,
IN UCHAR Type, IN UCHAR Type,
IN ULONGLONG Length, IN ULONGLONG Length,
IN ULONGLONG Alignment, IN ULONGLONG Alignment,
@ -3910,7 +3900,6 @@ RtlCheckBit(
******************************************************************************/ ******************************************************************************/
/* PCI_COMMON_CONFIG.Command */ /* PCI_COMMON_CONFIG.Command */
#define PCI_ENABLE_IO_SPACE 0x0001 #define PCI_ENABLE_IO_SPACE 0x0001
#define PCI_ENABLE_MEMORY_SPACE 0x0002 #define PCI_ENABLE_MEMORY_SPACE 0x0002
#define PCI_ENABLE_BUS_MASTER 0x0004 #define PCI_ENABLE_BUS_MASTER 0x0004
@ -3924,7 +3913,6 @@ RtlCheckBit(
#define PCI_DISABLE_LEVEL_INTERRUPT 0x0400 #define PCI_DISABLE_LEVEL_INTERRUPT 0x0400
/* PCI_COMMON_CONFIG.Status */ /* PCI_COMMON_CONFIG.Status */
#define PCI_STATUS_INTERRUPT_PENDING 0x0008 #define PCI_STATUS_INTERRUPT_PENDING 0x0008
#define PCI_STATUS_CAPABILITIES_LIST 0x0010 #define PCI_STATUS_CAPABILITIES_LIST 0x0010
#define PCI_STATUS_66MHZ_CAPABLE 0x0020 #define PCI_STATUS_66MHZ_CAPABLE 0x0020
@ -3939,7 +3927,6 @@ RtlCheckBit(
#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000 #define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
/* PCI_COMMON_CONFIG.HeaderType */ /* PCI_COMMON_CONFIG.HeaderType */
#define PCI_MULTIFUNCTION 0x80 #define PCI_MULTIFUNCTION 0x80
#define PCI_DEVICE_TYPE 0x00 #define PCI_DEVICE_TYPE 0x00
#define PCI_BRIDGE_TYPE 0x01 #define PCI_BRIDGE_TYPE 0x01
@ -3952,7 +3939,6 @@ RtlCheckBit(
((((PPCI_COMMON_CONFIG) (PciData))->HeaderType & PCI_MULTIFUNCTION) != 0) ((((PPCI_COMMON_CONFIG) (PciData))->HeaderType & PCI_MULTIFUNCTION) != 0)
/* PCI device classes */ /* PCI device classes */
#define PCI_CLASS_PRE_20 0x00 #define PCI_CLASS_PRE_20 0x00
#define PCI_CLASS_MASS_STORAGE_CTLR 0x01 #define PCI_CLASS_MASS_STORAGE_CTLR 0x01
#define PCI_CLASS_NETWORK_CTLR 0x02 #define PCI_CLASS_NETWORK_CTLR 0x02
@ -3973,12 +3959,10 @@ RtlCheckBit(
#define PCI_CLASS_DATA_ACQ_SIGNAL_PROC 0x11 #define PCI_CLASS_DATA_ACQ_SIGNAL_PROC 0x11
/* PCI device subclasses for class 0 */ /* PCI device subclasses for class 0 */
#define PCI_SUBCLASS_PRE_20_NON_VGA 0x00 #define PCI_SUBCLASS_PRE_20_NON_VGA 0x00
#define PCI_SUBCLASS_PRE_20_VGA 0x01 #define PCI_SUBCLASS_PRE_20_VGA 0x01
/* PCI device subclasses for class 1 (mass storage controllers)*/ /* PCI device subclasses for class 1 (mass storage controllers)*/
#define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00 #define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00
#define PCI_SUBCLASS_MSC_IDE_CTLR 0x01 #define PCI_SUBCLASS_MSC_IDE_CTLR 0x01
#define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02 #define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02
@ -3987,7 +3971,6 @@ RtlCheckBit(
#define PCI_SUBCLASS_MSC_OTHER 0x80 #define PCI_SUBCLASS_MSC_OTHER 0x80
/* PCI device subclasses for class 2 (network controllers)*/ /* PCI device subclasses for class 2 (network controllers)*/
#define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00 #define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00
#define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01 #define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01
#define PCI_SUBCLASS_NET_FDDI_CTLR 0x02 #define PCI_SUBCLASS_NET_FDDI_CTLR 0x02
@ -3996,27 +3979,23 @@ RtlCheckBit(
#define PCI_SUBCLASS_NET_OTHER 0x80 #define PCI_SUBCLASS_NET_OTHER 0x80
/* PCI device subclasses for class 3 (display controllers)*/ /* PCI device subclasses for class 3 (display controllers)*/
#define PCI_SUBCLASS_VID_VGA_CTLR 0x00 #define PCI_SUBCLASS_VID_VGA_CTLR 0x00
#define PCI_SUBCLASS_VID_XGA_CTLR 0x01 #define PCI_SUBCLASS_VID_XGA_CTLR 0x01
#define PCI_SUBCLASS_VID_3D_CTLR 0x02 #define PCI_SUBCLASS_VID_3D_CTLR 0x02
#define PCI_SUBCLASS_VID_OTHER 0x80 #define PCI_SUBCLASS_VID_OTHER 0x80
/* PCI device subclasses for class 4 (multimedia device)*/ /* PCI device subclasses for class 4 (multimedia device)*/
#define PCI_SUBCLASS_MM_VIDEO_DEV 0x00 #define PCI_SUBCLASS_MM_VIDEO_DEV 0x00
#define PCI_SUBCLASS_MM_AUDIO_DEV 0x01 #define PCI_SUBCLASS_MM_AUDIO_DEV 0x01
#define PCI_SUBCLASS_MM_TELEPHONY_DEV 0x02 #define PCI_SUBCLASS_MM_TELEPHONY_DEV 0x02
#define PCI_SUBCLASS_MM_OTHER 0x80 #define PCI_SUBCLASS_MM_OTHER 0x80
/* PCI device subclasses for class 5 (memory controller)*/ /* PCI device subclasses for class 5 (memory controller)*/
#define PCI_SUBCLASS_MEM_RAM 0x00 #define PCI_SUBCLASS_MEM_RAM 0x00
#define PCI_SUBCLASS_MEM_FLASH 0x01 #define PCI_SUBCLASS_MEM_FLASH 0x01
#define PCI_SUBCLASS_MEM_OTHER 0x80 #define PCI_SUBCLASS_MEM_OTHER 0x80
/* PCI device subclasses for class 6 (bridge device)*/ /* PCI device subclasses for class 6 (bridge device)*/
#define PCI_SUBCLASS_BR_HOST 0x00 #define PCI_SUBCLASS_BR_HOST 0x00
#define PCI_SUBCLASS_BR_ISA 0x01 #define PCI_SUBCLASS_BR_ISA 0x01
#define PCI_SUBCLASS_BR_EISA 0x02 #define PCI_SUBCLASS_BR_EISA 0x02
@ -4029,7 +4008,6 @@ RtlCheckBit(
#define PCI_SUBCLASS_BR_OTHER 0x80 #define PCI_SUBCLASS_BR_OTHER 0x80
/* PCI device subclasses for class C (serial bus controller)*/ /* PCI device subclasses for class C (serial bus controller)*/
#define PCI_SUBCLASS_SB_IEEE1394 0x00 #define PCI_SUBCLASS_SB_IEEE1394 0x00
#define PCI_SUBCLASS_SB_ACCESS 0x01 #define PCI_SUBCLASS_SB_ACCESS 0x01
#define PCI_SUBCLASS_SB_SSA 0x02 #define PCI_SUBCLASS_SB_SSA 0x02
@ -4081,13 +4059,11 @@ RtlCheckBit(
#define IO_TYPE_CSQ_EX 3 #define IO_TYPE_CSQ_EX 3
/* IO_RESOURCE_DESCRIPTOR.Option */ /* IO_RESOURCE_DESCRIPTOR.Option */
#define IO_RESOURCE_PREFERRED 0x01 #define IO_RESOURCE_PREFERRED 0x01
#define IO_RESOURCE_DEFAULT 0x02 #define IO_RESOURCE_DEFAULT 0x02
#define IO_RESOURCE_ALTERNATIVE 0x08 #define IO_RESOURCE_ALTERNATIVE 0x08
/* DEVICE_OBJECT.Flags */ /* DEVICE_OBJECT.Flags */
#define DO_VERIFY_VOLUME 0x00000002 #define DO_VERIFY_VOLUME 0x00000002
#define DO_BUFFERED_IO 0x00000004 #define DO_BUFFERED_IO 0x00000004
#define DO_EXCLUSIVE 0x00000008 #define DO_EXCLUSIVE 0x00000008
@ -4100,7 +4076,6 @@ RtlCheckBit(
#define DO_POWER_INRUSH 0x00004000 #define DO_POWER_INRUSH 0x00004000
/* DEVICE_OBJECT.Characteristics */ /* DEVICE_OBJECT.Characteristics */
#define FILE_REMOVABLE_MEDIA 0x00000001 #define FILE_REMOVABLE_MEDIA 0x00000001
#define FILE_READ_ONLY_DEVICE 0x00000002 #define FILE_READ_ONLY_DEVICE 0x00000002
#define FILE_FLOPPY_DISKETTE 0x00000004 #define FILE_FLOPPY_DISKETTE 0x00000004
@ -4115,7 +4090,6 @@ RtlCheckBit(
#define FILE_CHARACTERISTIC_WEBDAV_DEVICE 0x00002000 #define FILE_CHARACTERISTIC_WEBDAV_DEVICE 0x00002000
/* DEVICE_OBJECT.AlignmentRequirement */ /* DEVICE_OBJECT.AlignmentRequirement */
#define FILE_BYTE_ALIGNMENT 0x00000000 #define FILE_BYTE_ALIGNMENT 0x00000000
#define FILE_WORD_ALIGNMENT 0x00000001 #define FILE_WORD_ALIGNMENT 0x00000001
#define FILE_LONG_ALIGNMENT 0x00000003 #define FILE_LONG_ALIGNMENT 0x00000003
@ -4128,7 +4102,6 @@ RtlCheckBit(
#define FILE_512_BYTE_ALIGNMENT 0x000001ff #define FILE_512_BYTE_ALIGNMENT 0x000001ff
/* DEVICE_OBJECT.DeviceType */ /* DEVICE_OBJECT.DeviceType */
#define DEVICE_TYPE ULONG #define DEVICE_TYPE ULONG
#define FILE_DEVICE_BEEP 0x00000001 #define FILE_DEVICE_BEEP 0x00000001
@ -4328,91 +4301,94 @@ typedef struct _SHARE_ACCESS {
ULONG SharedDelete; ULONG SharedDelete;
} SHARE_ACCESS, *PSHARE_ACCESS; } SHARE_ACCESS, *PSHARE_ACCESS;
typedef struct _PCI_COMMON_HEADER { /* While MS WDK uses inheritance in C++, we cannot do this with gcc, as
USHORT VendorID; inheritance, even from a struct renders the type non-POD. So we use
USHORT DeviceID; this hack */
USHORT Command; #define PCI_COMMON_HEADER_MEMBERS \
USHORT Status; USHORT VendorID; \
UCHAR RevisionID; USHORT DeviceID; \
UCHAR ProgIf; USHORT Command; \
UCHAR SubClass; USHORT Status; \
UCHAR BaseClass; UCHAR RevisionID; \
UCHAR CacheLineSize; UCHAR ProgIf; \
UCHAR LatencyTimer; UCHAR SubClass; \
UCHAR HeaderType; UCHAR BaseClass; \
UCHAR BIST; UCHAR CacheLineSize; \
union { UCHAR LatencyTimer; \
struct _PCI_HEADER_TYPE_0 { UCHAR HeaderType; \
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES]; UCHAR BIST; \
ULONG CIS; union { \
USHORT SubVendorID; struct _PCI_HEADER_TYPE_0 { \
USHORT SubSystemID; ULONG BaseAddresses[PCI_TYPE0_ADDRESSES]; \
ULONG ROMBaseAddress; ULONG CIS; \
UCHAR CapabilitiesPtr; USHORT SubVendorID; \
UCHAR Reserved1[3]; USHORT SubSystemID; \
ULONG Reserved2; ULONG ROMBaseAddress; \
UCHAR InterruptLine; UCHAR CapabilitiesPtr; \
UCHAR InterruptPin; UCHAR Reserved1[3]; \
UCHAR MinimumGrant; ULONG Reserved2; \
UCHAR MaximumLatency; UCHAR InterruptLine; \
} type0; UCHAR InterruptPin; \
struct _PCI_HEADER_TYPE_1 { UCHAR MinimumGrant; \
ULONG BaseAddresses[PCI_TYPE1_ADDRESSES]; UCHAR MaximumLatency; \
UCHAR PrimaryBus; } type0; \
UCHAR SecondaryBus; struct _PCI_HEADER_TYPE_1 { \
UCHAR SubordinateBus; ULONG BaseAddresses[PCI_TYPE1_ADDRESSES]; \
UCHAR SecondaryLatency; UCHAR PrimaryBus; \
UCHAR IOBase; UCHAR SecondaryBus; \
UCHAR IOLimit; UCHAR SubordinateBus; \
USHORT SecondaryStatus; UCHAR SecondaryLatency; \
USHORT MemoryBase; UCHAR IOBase; \
USHORT MemoryLimit; UCHAR IOLimit; \
USHORT PrefetchBase; USHORT SecondaryStatus; \
USHORT PrefetchLimit; USHORT MemoryBase; \
ULONG PrefetchBaseUpper32; USHORT MemoryLimit; \
ULONG PrefetchLimitUpper32; USHORT PrefetchBase; \
USHORT IOBaseUpper16; USHORT PrefetchLimit; \
USHORT IOLimitUpper16; ULONG PrefetchBaseUpper32; \
UCHAR CapabilitiesPtr; ULONG PrefetchLimitUpper32; \
UCHAR Reserved1[3]; USHORT IOBaseUpper16; \
ULONG ROMBaseAddress; USHORT IOLimitUpper16; \
UCHAR InterruptLine; UCHAR CapabilitiesPtr; \
UCHAR InterruptPin; UCHAR Reserved1[3]; \
USHORT BridgeControl; ULONG ROMBaseAddress; \
} type1; UCHAR InterruptLine; \
struct _PCI_HEADER_TYPE_2 { UCHAR InterruptPin; \
ULONG SocketRegistersBaseAddress; USHORT BridgeControl; \
UCHAR CapabilitiesPtr; } type1; \
UCHAR Reserved; struct _PCI_HEADER_TYPE_2 { \
USHORT SecondaryStatus; ULONG SocketRegistersBaseAddress; \
UCHAR PrimaryBus; UCHAR CapabilitiesPtr; \
UCHAR SecondaryBus; UCHAR Reserved; \
UCHAR SubordinateBus; USHORT SecondaryStatus; \
UCHAR SecondaryLatency; UCHAR PrimaryBus; \
struct { UCHAR SecondaryBus; \
ULONG Base; UCHAR SubordinateBus; \
ULONG Limit; UCHAR SecondaryLatency; \
} Range[PCI_TYPE2_ADDRESSES-1]; struct { \
UCHAR InterruptLine; ULONG Base; \
UCHAR InterruptPin; ULONG Limit; \
USHORT BridgeControl; } Range[PCI_TYPE2_ADDRESSES-1]; \
} type2; UCHAR InterruptLine; \
UCHAR InterruptPin; \
USHORT BridgeControl; \
} type2; \
} u; } u;
typedef struct _PCI_COMMON_HEADER {
PCI_COMMON_HEADER_MEMBERS
} PCI_COMMON_HEADER, *PPCI_COMMON_HEADER; } PCI_COMMON_HEADER, *PPCI_COMMON_HEADER;
#ifdef __cplusplus #ifdef __cplusplus
typedef struct _PCI_COMMON_CONFIG {
typedef struct _PCI_COMMON_CONFIG : PCI_COMMON_HEADER { PCI_COMMON_HEADER_MEMBERS
UCHAR DeviceSpecific[192]; UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG; } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
#else #else
typedef struct _PCI_COMMON_CONFIG { typedef struct _PCI_COMMON_CONFIG {
PCI_COMMON_HEADER DUMMYSTRUCTNAME; PCI_COMMON_HEADER DUMMYSTRUCTNAME;
UCHAR DeviceSpecific[192]; UCHAR DeviceSpecific[192];
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG; } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
#endif #endif
typedef enum _CREATE_FILE_TYPE { typedef enum _CREATE_FILE_TYPE {
@ -6714,7 +6690,7 @@ WRITE_REGISTER_USHORT(
FORCEINLINE FORCEINLINE
NTSTATUS NTSTATUS
IoAllocateAdapterChannel( IoAllocateAdapterChannel(
IN PADAPTER_OBJECT AdapterObject, IN PDMA_ADAPTER DmaAdapter,
IN PDEVICE_OBJECT DeviceObject, IN PDEVICE_OBJECT DeviceObject,
IN ULONG NumberOfMapRegisters, IN ULONG NumberOfMapRegisters,
IN PDRIVER_CONTROL ExecutionRoutine, IN PDRIVER_CONTROL ExecutionRoutine,
@ -6734,7 +6710,7 @@ IoAllocateAdapterChannel(
FORCEINLINE FORCEINLINE
BOOLEAN BOOLEAN
IoFlushAdapterBuffers( IoFlushAdapterBuffers(
IN PADAPTER_OBJECT AdapterObject, IN PDMA_ADAPTER DmaAdapter,
IN PMDL Mdl, IN PMDL Mdl,
IN PVOID MapRegisterBase, IN PVOID MapRegisterBase,
IN PVOID CurrentVa, IN PVOID CurrentVa,
@ -6749,13 +6725,13 @@ IoFlushAdapterBuffers(
MapRegisterBase, MapRegisterBase,
CurrentVa, CurrentVa,
Length, Length,
WriteToDevice ); WriteToDevice);
} }
FORCEINLINE FORCEINLINE
VOID VOID
IoFreeAdapterChannel( IoFreeAdapterChannel(
IN PADAPTER_OBJECT AdapterObject) IN PDMA_ADAPTER DmaAdapter)
{ {
PFREE_ADAPTER_CHANNEL FreeAdapterChannel; PFREE_ADAPTER_CHANNEL FreeAdapterChannel;
FreeAdapterChannel = *(DmaAdapter)->DmaOperations->FreeAdapterChannel; FreeAdapterChannel = *(DmaAdapter)->DmaOperations->FreeAdapterChannel;
@ -6766,7 +6742,7 @@ IoFreeAdapterChannel(
FORCEINLINE FORCEINLINE
VOID VOID
IoFreeMapRegisters( IoFreeMapRegisters(
IN PADAPTER_OBJECT AdapterObject, IN PDMA_ADAPTER DmaAdapter,
IN PVOID MapRegisterBase, IN PVOID MapRegisterBase,
IN ULONG NumberOfMapRegisters) IN ULONG NumberOfMapRegisters)
{ {
@ -6850,33 +6826,6 @@ IoAcquireRemoveLockEx(
} \ } \
} }
#if defined(USE_DMA_MACROS) && !defined(_NTHAL_) && (defined(_NTDDK_) || defined(_NTDRIVER_)) || defined(_WDM_INCLUDED_)
FORCEINLINE
NTSTATUS
IoAllocateAdapterChannel(
IN PDMA_ADAPTER DmaAdapter,
IN PDEVICE_OBJECT DeviceObject,
IN ULONG NumberOfMapRegisters,
IN PDRIVER_CONTROL ExecutionRoutine,
IN PVOID Context)
{
PALLOCATE_ADAPTER_CHANNEL allocateAdapterChannel;
NTSTATUS status;
allocateAdapterChannel = *(DmaAdapter)->DmaOperations->AllocateAdapterChannel;
ASSERT( allocateAdapterChannel != NULL );
status = allocateAdapterChannel( DmaAdapter,
DeviceObject,
NumberOfMapRegisters,
ExecutionRoutine,
Context );
return status;
}
#endif
#if (NTDDI_VERSION >= NTDDI_WIN2K) #if (NTDDI_VERSION >= NTDDI_WIN2K)
NTKERNELAPI NTKERNELAPI
@ -9122,6 +9071,17 @@ typedef struct _QUOTA_LIMITS {
#define QUOTA_LIMITS_HARDWS_MAX_DISABLE 0x00000008 #define QUOTA_LIMITS_HARDWS_MAX_DISABLE 0x00000008
#define QUOTA_LIMITS_USE_DEFAULT_LIMITS 0x00000010 #define QUOTA_LIMITS_USE_DEFAULT_LIMITS 0x00000010
/* HACK HACK HACK - GCC (or perhaps LD) is messing this up */
#if defined(_NTSYSTEM_) || defined(__GNUC__)
#define NLS_MB_CODE_PAGE_TAG NlsMbCodePageTag
#define NLS_MB_OEM_CODE_PAGE_TAG NlsMbOemCodePageTag
#else
#define NLS_MB_CODE_PAGE_TAG (*NlsMbCodePageTag)
#define NLS_MB_OEM_CODE_PAGE_TAG (*NlsMbOemCodePageTag)
#endif /* _NT_SYSTEM */
extern BOOLEAN NTSYSAPI NLS_MB_CODE_PAGE_TAG;
extern BOOLEAN NTSYSAPI NLS_MB_OEM_CODE_PAGE_TAG;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif