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[DDK}
Add a number of PCI related types to ntddk.h svn path=/trunk/; revision=47553
This commit is contained in:
Timo Kreuzer
parent
9d059198bb
commit
c3179d84ef
1 changed files with 712 additions and 65 deletions
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@ -322,6 +322,718 @@ typedef struct _ARBITER_INTERFACE {
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ULONG Flags;
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} ARBITER_INTERFACE, *PARBITER_INTERFACE;
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typedef enum _RESOURCE_TRANSLATION_DIRECTION {
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TranslateChildToParent,
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TranslateParentToChild
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} RESOURCE_TRANSLATION_DIRECTION;
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typedef NTSTATUS
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(NTAPI *PTRANSLATE_RESOURCE_HANDLER)(
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IN OUT PVOID Context OPTIONAL,
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IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source,
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IN RESOURCE_TRANSLATION_DIRECTION Direction,
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IN ULONG AlternativesCount OPTIONAL,
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IN IO_RESOURCE_DESCRIPTOR Alternatives[],
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IN PDEVICE_OBJECT PhysicalDeviceObject,
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OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target);
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typedef NTSTATUS
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(NTAPI *PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER)(
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IN OUT PVOID Context OPTIONAL,
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IN PIO_RESOURCE_DESCRIPTOR Source,
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IN PDEVICE_OBJECT PhysicalDeviceObject,
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OUT PULONG TargetCount,
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OUT PIO_RESOURCE_DESCRIPTOR *Target);
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typedef struct _TRANSLATOR_INTERFACE {
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USHORT Size;
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USHORT Version;
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PVOID Context;
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PINTERFACE_REFERENCE InterfaceReference;
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PINTERFACE_DEREFERENCE InterfaceDereference;
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PTRANSLATE_RESOURCE_HANDLER TranslateResources;
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PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER TranslateResourceRequirements;
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} TRANSLATOR_INTERFACE, *PTRANSLATOR_INTERFACE;
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typedef struct _PCI_AGP_CAPABILITY {
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PCI_CAPABILITIES_HEADER Header;
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USHORT Minor:4;
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USHORT Major:4;
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USHORT Rsvd1:8;
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struct _PCI_AGP_STATUS {
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ULONG Rate:3;
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ULONG Agp3Mode:1;
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ULONG FastWrite:1;
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ULONG FourGB:1;
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ULONG HostTransDisable:1;
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ULONG Gart64:1;
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ULONG ITA_Coherent:1;
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ULONG SideBandAddressing:1;
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ULONG CalibrationCycle:3;
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ULONG AsyncRequestSize:3;
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ULONG Rsvd1:1;
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ULONG Isoch:1;
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ULONG Rsvd2:6;
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ULONG RequestQueueDepthMaximum:8;
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} AGPStatus;
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struct _PCI_AGP_COMMAND {
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ULONG Rate:3;
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ULONG Rsvd1:1;
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ULONG FastWriteEnable:1;
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ULONG FourGBEnable:1;
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ULONG Rsvd2:1;
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ULONG Gart64:1;
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ULONG AGPEnable:1;
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ULONG SBAEnable:1;
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ULONG CalibrationCycle:3;
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ULONG AsyncReqSize:3;
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ULONG Rsvd3:8;
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ULONG RequestQueueDepth:8;
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} AGPCommand;
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} PCI_AGP_CAPABILITY, *PPCI_AGP_CAPABILITY;
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typedef enum _EXTENDED_AGP_REGISTER {
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IsochStatus,
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AgpControl,
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ApertureSize,
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AperturePageSize,
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GartLow,
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GartHigh,
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IsochCommand
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} EXTENDED_AGP_REGISTER, *PEXTENDED_AGP_REGISTER;
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typedef struct _PCI_AGP_ISOCH_STATUS {
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ULONG ErrorCode:2;
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ULONG Rsvd1:1;
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ULONG Isoch_L:3;
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ULONG Isoch_Y:2;
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ULONG Isoch_N:8;
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ULONG Rsvd2:16;
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} PCI_AGP_ISOCH_STATUS, *PPCI_AGP_ISOCH_STATUS;
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typedef struct _PCI_AGP_CONTROL {
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ULONG Rsvd1:7;
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ULONG GTLB_Enable:1;
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ULONG AP_Enable:1;
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ULONG CAL_Disable:1;
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ULONG Rsvd2:22;
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} PCI_AGP_CONTROL, *PPCI_AGP_CONTROL;
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typedef struct _PCI_AGP_APERTURE_PAGE_SIZE {
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USHORT PageSizeMask:11;
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USHORT Rsvd1:1;
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USHORT PageSizeSelect:4;
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} PCI_AGP_APERTURE_PAGE_SIZE, *PPCI_AGP_APERTURE_PAGE_SIZE;
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typedef struct _PCI_AGP_ISOCH_COMMAND {
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USHORT Rsvd1:6;
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USHORT Isoch_Y:2;
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USHORT Isoch_N:8;
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} PCI_AGP_ISOCH_COMMAND, *PPCI_AGP_ISOCH_COMMAND;
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typedef struct PCI_AGP_EXTENDED_CAPABILITY {
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PCI_AGP_ISOCH_STATUS IsochStatus;
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PCI_AGP_CONTROL AgpControl;
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USHORT ApertureSize;
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PCI_AGP_APERTURE_PAGE_SIZE AperturePageSize;
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ULONG GartLow;
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ULONG GartHigh;
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PCI_AGP_ISOCH_COMMAND IsochCommand;
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} PCI_AGP_EXTENDED_CAPABILITY, *PPCI_AGP_EXTENDED_CAPABILITY;
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#define PCI_AGP_RATE_1X 0x1
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#define PCI_AGP_RATE_2X 0x2
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#define PCI_AGP_RATE_4X 0x4
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#define PCIX_MODE_CONVENTIONAL_PCI 0x0
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#define PCIX_MODE1_66MHZ 0x1
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#define PCIX_MODE1_100MHZ 0x2
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#define PCIX_MODE1_133MHZ 0x3
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#define PCIX_MODE2_266_66MHZ 0x9
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#define PCIX_MODE2_266_100MHZ 0xA
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#define PCIX_MODE2_266_133MHZ 0xB
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#define PCIX_MODE2_533_66MHZ 0xD
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#define PCIX_MODE2_533_100MHZ 0xE
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#define PCIX_MODE2_533_133MHZ 0xF
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#define PCIX_VERSION_MODE1_ONLY 0x0
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#define PCIX_VERSION_MODE2_ECC 0x1
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#define PCIX_VERSION_DUAL_MODE_ECC 0x2
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typedef struct _PCIX_BRIDGE_CAPABILITY {
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PCI_CAPABILITIES_HEADER Header;
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union {
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struct {
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USHORT Bus64Bit:1;
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USHORT Bus133MHzCapable:1;
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USHORT SplitCompletionDiscarded:1;
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USHORT UnexpectedSplitCompletion:1;
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USHORT SplitCompletionOverrun:1;
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USHORT SplitRequestDelayed:1;
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USHORT BusModeFrequency:4;
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USHORT Rsvd:2;
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USHORT Version:2;
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USHORT Bus266MHzCapable:1;
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USHORT Bus533MHzCapable:1;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
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} SecondaryStatus;
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union {
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struct {
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ULONG FunctionNumber:3;
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ULONG DeviceNumber:5;
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ULONG BusNumber:8;
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ULONG Device64Bit:1;
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ULONG Device133MHzCapable:1;
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ULONG SplitCompletionDiscarded:1;
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ULONG UnexpectedSplitCompletion:1;
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ULONG SplitCompletionOverrun:1;
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ULONG SplitRequestDelayed:1;
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ULONG Rsvd:7;
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ULONG DIMCapable:1;
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ULONG Device266MHzCapable:1;
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ULONG Device533MHzCapable:1;
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} DUMMYSTRUCTNAME;
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ULONG AsULONG;
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} BridgeStatus;
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USHORT UpstreamSplitTransactionCapacity;
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USHORT UpstreamSplitTransactionLimit;
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USHORT DownstreamSplitTransactionCapacity;
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USHORT DownstreamSplitTransactionLimit;
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union {
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struct {
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ULONG SelectSecondaryRegisters:1;
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ULONG ErrorPresentInOtherBank:1;
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ULONG AdditionalCorrectableError:1;
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ULONG AdditionalUncorrectableError:1;
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ULONG ErrorPhase:3;
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ULONG ErrorCorrected:1;
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ULONG Syndrome:8;
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ULONG ErrorFirstCommand:4;
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ULONG ErrorSecondCommand:4;
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ULONG ErrorUpperAttributes:4;
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ULONG ControlUpdateEnable:1;
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ULONG Rsvd:1;
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ULONG DisableSingleBitCorrection:1;
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ULONG EccMode:1;
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} DUMMYSTRUCTNAME;
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ULONG AsULONG;
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} EccControlStatus;
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ULONG EccFirstAddress;
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ULONG EccSecondAddress;
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ULONG EccAttribute;
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} PCIX_BRIDGE_CAPABILITY, *PPCIX_BRIDGE_CAPABILITY;
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typedef struct _PCI_SUBSYSTEM_IDS_CAPABILITY {
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PCI_CAPABILITIES_HEADER Header;
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USHORT Reserved;
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USHORT SubVendorID;
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USHORT SubSystemID;
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} PCI_SUBSYSTEM_IDS_CAPABILITY, *PPCI_SUBSYSTEM_IDS_CAPABILITY;
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#define OSC_FIRMWARE_FAILURE 0x02
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#define OSC_UNRECOGNIZED_UUID 0x04
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#define OSC_UNRECOGNIZED_REVISION 0x08
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#define OSC_CAPABILITIES_MASKED 0x10
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#define PCI_ROOT_BUS_OSC_METHOD_CAPABILITY_REVISION 0x01
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typedef struct _PCI_ROOT_BUS_OSC_SUPPORT_FIELD {
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union {
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struct {
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ULONG ExtendedConfigOpRegions:1;
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ULONG ActiveStatePowerManagement:1;
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ULONG ClockPowerManagement:1;
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ULONG SegmentGroups:1;
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ULONG MessageSignaledInterrupts:1;
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ULONG WindowsHardwareErrorArchitecture:1;
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ULONG Reserved:26;
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} DUMMYSTRUCTNAME;
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ULONG AsULONG;
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} u;
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} PCI_ROOT_BUS_OSC_SUPPORT_FIELD, *PPCI_ROOT_BUS_OSC_SUPPORT_FIELD;
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typedef struct _PCI_ROOT_BUS_OSC_CONTROL_FIELD {
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union {
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struct {
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ULONG ExpressNativeHotPlug:1;
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ULONG ShpcNativeHotPlug:1;
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ULONG ExpressNativePME:1;
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ULONG ExpressAdvancedErrorReporting:1;
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ULONG ExpressCapabilityStructure:1;
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ULONG Reserved:27;
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} DUMMYSTRUCTNAME;
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ULONG AsULONG;
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} u;
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} PCI_ROOT_BUS_OSC_CONTROL_FIELD, *PPCI_ROOT_BUS_OSC_CONTROL_FIELD;
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typedef enum _PCI_HARDWARE_INTERFACE {
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PciConventional,
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PciXMode1,
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PciXMode2,
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PciExpress
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} PCI_HARDWARE_INTERFACE, *PPCI_HARDWARE_INTERFACE;
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typedef enum {
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BusWidth32Bits,
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BusWidth64Bits
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} PCI_BUS_WIDTH;
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typedef struct _PCI_ROOT_BUS_HARDWARE_CAPABILITY {
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PCI_HARDWARE_INTERFACE SecondaryInterface;
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struct {
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BOOLEAN BusCapabilitiesFound;
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ULONG CurrentSpeedAndMode;
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ULONG SupportedSpeedsAndModes;
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BOOLEAN DeviceIDMessagingCapable;
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PCI_BUS_WIDTH SecondaryBusWidth;
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} DUMMYSTRUCTNAME;
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PCI_ROOT_BUS_OSC_SUPPORT_FIELD OscFeatureSupport;
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PCI_ROOT_BUS_OSC_CONTROL_FIELD OscControlRequest;
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PCI_ROOT_BUS_OSC_CONTROL_FIELD OscControlGranted;
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} PCI_ROOT_BUS_HARDWARE_CAPABILITY, *PPCI_ROOT_BUS_HARDWARE_CAPABILITY;
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typedef union _PCI_EXPRESS_CAPABILITIES_REGISTER {
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struct {
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USHORT CapabilityVersion:4;
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USHORT DeviceType:4;
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USHORT SlotImplemented:1;
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USHORT InterruptMessageNumber:5;
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USHORT Rsvd:2;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
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} PCI_EXPRESS_CAPABILITIES_REGISTER, *PPCI_EXPRESS_CAPABILITIES_REGISTER;
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typedef union _PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER {
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struct {
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ULONG MaxPayloadSizeSupported:3;
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ULONG PhantomFunctionsSupported:2;
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ULONG ExtendedTagSupported:1;
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ULONG L0sAcceptableLatency:3;
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ULONG L1AcceptableLatency:3;
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ULONG Undefined:3;
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ULONG RoleBasedErrorReporting:1;
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ULONG Rsvd1:2;
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ULONG CapturedSlotPowerLimit:8;
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ULONG CapturedSlotPowerLimitScale:2;
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ULONG Rsvd2:4;
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} DUMMYSTRUCTNAME;
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ULONG AsULONG;
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} PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER, *PPCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER;
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#define PCI_EXPRESS_AER_DEVICE_CONTROL_MASK 0x07;
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typedef union _PCI_EXPRESS_DEVICE_CONTROL_REGISTER {
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struct {
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USHORT CorrectableErrorEnable:1;
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USHORT NonFatalErrorEnable:1;
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USHORT FatalErrorEnable:1;
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USHORT UnsupportedRequestErrorEnable:1;
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USHORT EnableRelaxedOrder:1;
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USHORT MaxPayloadSize:3;
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USHORT ExtendedTagEnable:1;
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USHORT PhantomFunctionsEnable:1;
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USHORT AuxPowerEnable:1;
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USHORT NoSnoopEnable:1;
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USHORT MaxReadRequestSize:3;
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USHORT BridgeConfigRetryEnable:1;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
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} PCI_EXPRESS_DEVICE_CONTROL_REGISTER, *PPCI_EXPRESS_DEVICE_CONTROL_REGISTER;
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#define PCI_EXPRESS_AER_DEVICE_STATUS_MASK 0x0F;
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typedef union _PCI_EXPRESS_DEVICE_STATUS_REGISTER {
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struct {
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USHORT CorrectableErrorDetected:1;
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USHORT NonFatalErrorDetected:1;
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USHORT FatalErrorDetected:1;
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USHORT UnsupportedRequestDetected:1;
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USHORT AuxPowerDetected:1;
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USHORT TransactionsPending:1;
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USHORT Rsvd:10;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
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} PCI_EXPRESS_DEVICE_STATUS_REGISTER, *PPCI_EXPRESS_DEVICE_STATUS_REGISTER;
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typedef union _PCI_EXPRESS_LINK_CAPABILITIES_REGISTER {
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struct {
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ULONG MaximumLinkSpeed:4;
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ULONG MaximumLinkWidth:6;
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ULONG ActiveStatePMSupport:2;
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ULONG L0sExitLatency:3;
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ULONG L1ExitLatency:3;
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ULONG ClockPowerManagement:1;
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ULONG SurpriseDownErrorReportingCapable:1;
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ULONG DataLinkLayerActiveReportingCapable:1;
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ULONG Rsvd:3;
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ULONG PortNumber:8;
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} DUMMYSTRUCTNAME;
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ULONG AsULONG;
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} PCI_EXPRESS_LINK_CAPABILITIES_REGISTER, *PPCI_EXPRESS_LINK_CAPABILITIES_REGISTER;
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typedef union _PCI_EXPRESS_LINK_CONTROL_REGISTER {
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struct {
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USHORT ActiveStatePMControl:2;
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USHORT Rsvd1:1;
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USHORT ReadCompletionBoundary:1;
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USHORT LinkDisable:1;
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USHORT RetrainLink:1;
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USHORT CommonClockConfig:1;
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USHORT ExtendedSynch:1;
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USHORT EnableClockPowerManagement:1;
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USHORT Rsvd2:7;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
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} PCI_EXPRESS_LINK_CONTROL_REGISTER, *PPCI_EXPRESS_LINK_CONTROL_REGISTER;
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typedef union _PCI_EXPRESS_LINK_STATUS_REGISTER {
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struct {
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USHORT LinkSpeed:4;
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USHORT LinkWidth:6;
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USHORT Undefined:1;
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USHORT LinkTraining:1;
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USHORT SlotClockConfig:1;
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USHORT DataLinkLayerActive:1;
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USHORT Rsvd:2;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
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} PCI_EXPRESS_LINK_STATUS_REGISTER, *PPCI_EXPRESS_LINK_STATUS_REGISTER;
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typedef union _PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER {
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struct {
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ULONG AttentionButtonPresent:1;
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ULONG PowerControllerPresent:1;
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ULONG MRLSensorPresent:1;
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ULONG AttentionIndicatorPresent:1;
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ULONG PowerIndicatorPresent:1;
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ULONG HotPlugSurprise:1;
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ULONG HotPlugCapable:1;
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ULONG SlotPowerLimit:8;
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ULONG SlotPowerLimitScale:2;
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ULONG ElectromechanicalLockPresent:1;
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ULONG NoCommandCompletedSupport:1;
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ULONG PhysicalSlotNumber:13;
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} DUMMYSTRUCTNAME;
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ULONG AsULONG;
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} PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_SLOT_CAPABILITIES_REGISTER;
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typedef union _PCI_EXPRESS_SLOT_CONTROL_REGISTER {
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struct {
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USHORT AttentionButtonEnable:1;
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USHORT PowerFaultDetectEnable:1;
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USHORT MRLSensorEnable:1;
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USHORT PresenceDetectEnable:1;
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USHORT CommandCompletedEnable:1;
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USHORT HotPlugInterruptEnable:1;
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USHORT AttentionIndicatorControl:2;
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USHORT PowerIndicatorControl:2;
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USHORT PowerControllerControl:1;
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USHORT ElectromechanicalLockControl:1;
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USHORT DataLinkStateChangeEnable:1;
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USHORT Rsvd:3;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
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} PCI_EXPRESS_SLOT_CONTROL_REGISTER, *PPCI_EXPRESS_SLOT_CONTROL_REGISTER;
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typedef union _PCI_EXPRESS_SLOT_STATUS_REGISTER {
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struct {
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USHORT AttentionButtonPressed:1;
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USHORT PowerFaultDetected:1;
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USHORT MRLSensorChanged:1;
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USHORT PresenceDetectChanged:1;
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USHORT CommandCompleted:1;
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USHORT MRLSensorState:1;
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USHORT PresenceDetectState:1;
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USHORT ElectromechanicalLockEngaged:1;
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USHORT DataLinkStateChanged:1;
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USHORT Rsvd:7;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
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} PCI_EXPRESS_SLOT_STATUS_REGISTER, *PPCI_EXPRESS_SLOT_STATUS_REGISTER;
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typedef union _PCI_EXPRESS_ROOT_CONTROL_REGISTER {
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struct {
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USHORT CorrectableSerrEnable:1;
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USHORT NonFatalSerrEnable:1;
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USHORT FatalSerrEnable:1;
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USHORT PMEInterruptEnable:1;
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USHORT CRSSoftwareVisibilityEnable:1;
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USHORT Rsvd:11;
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} DUMMYSTRUCTNAME;
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USHORT AsUSHORT;
|
||||
} PCI_EXPRESS_ROOT_CONTROL_REGISTER, *PPCI_EXPRESS_ROOT_CONTROL_REGISTER;
|
||||
|
||||
typedef union _PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER {
|
||||
struct {
|
||||
USHORT CRSSoftwareVisibility:1;
|
||||
USHORT Rsvd:15;
|
||||
} DUMMYSTRUCTNAME;
|
||||
USHORT AsUSHORT;
|
||||
} PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_ROOT_CAPABILITIES_REGISTER;
|
||||
|
||||
typedef union _PCI_EXPRESS_ROOT_STATUS_REGISTER {
|
||||
struct {
|
||||
ULONG PMERequestorId:16;
|
||||
ULONG PMEStatus:1;
|
||||
ULONG PMEPending:1;
|
||||
ULONG Rsvd:14;
|
||||
} DUMMYSTRUCTNAME;
|
||||
ULONG AsULONG;
|
||||
} PCI_EXPRESS_ROOT_STATUS_REGISTER, *PPCI_EXPRESS_ROOT_STATUS_REGISTER;
|
||||
|
||||
typedef struct _PCI_EXPRESS_CAPABILITY {
|
||||
PCI_CAPABILITIES_HEADER Header;
|
||||
PCI_EXPRESS_CAPABILITIES_REGISTER ExpressCapabilities;
|
||||
PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER DeviceCapabilities;
|
||||
PCI_EXPRESS_DEVICE_CONTROL_REGISTER DeviceControl;
|
||||
PCI_EXPRESS_DEVICE_STATUS_REGISTER DeviceStatus;
|
||||
PCI_EXPRESS_LINK_CAPABILITIES_REGISTER LinkCapabilities;
|
||||
PCI_EXPRESS_LINK_CONTROL_REGISTER LinkControl;
|
||||
PCI_EXPRESS_LINK_STATUS_REGISTER LinkStatus;
|
||||
PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER SlotCapabilities;
|
||||
PCI_EXPRESS_SLOT_CONTROL_REGISTER SlotControl;
|
||||
PCI_EXPRESS_SLOT_STATUS_REGISTER SlotStatus;
|
||||
PCI_EXPRESS_ROOT_CONTROL_REGISTER RootControl;
|
||||
PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER RootCapabilities;
|
||||
PCI_EXPRESS_ROOT_STATUS_REGISTER RootStatus;
|
||||
} PCI_EXPRESS_CAPABILITY, *PPCI_EXPRESS_CAPABILITY;
|
||||
|
||||
typedef enum {
|
||||
MRLClosed = 0,
|
||||
MRLOpen
|
||||
} PCI_EXPRESS_MRL_STATE;
|
||||
|
||||
typedef enum {
|
||||
SlotEmpty = 0,
|
||||
CardPresent
|
||||
} PCI_EXPRESS_CARD_PRESENCE;
|
||||
|
||||
typedef enum {
|
||||
IndicatorOn = 1,
|
||||
IndicatorBlink,
|
||||
IndicatorOff
|
||||
} PCI_EXPRESS_INDICATOR_STATE;
|
||||
|
||||
typedef enum {
|
||||
PowerOn = 0,
|
||||
PowerOff
|
||||
} PCI_EXPRESS_POWER_STATE;
|
||||
|
||||
typedef enum {
|
||||
L0sEntrySupport = 1,
|
||||
L0sAndL1EntrySupport = 3
|
||||
} PCI_EXPRESS_ASPM_SUPPORT;
|
||||
|
||||
typedef enum {
|
||||
L0sAndL1EntryDisabled,
|
||||
L0sEntryEnabled,
|
||||
L1EntryEnabled,
|
||||
L0sAndL1EntryEnabled
|
||||
} PCI_EXPRESS_ASPM_CONTROL;
|
||||
|
||||
typedef enum {
|
||||
L0s_Below64ns = 0,
|
||||
L0s_64ns_128ns,
|
||||
L0s_128ns_256ns,
|
||||
L0s_256ns_512ns,
|
||||
L0s_512ns_1us,
|
||||
L0s_1us_2us,
|
||||
L0s_2us_4us,
|
||||
L0s_Above4us
|
||||
} PCI_EXPRESS_L0s_EXIT_LATENCY;
|
||||
|
||||
typedef enum {
|
||||
L1_Below1us = 0,
|
||||
L1_1us_2us,
|
||||
L1_2us_4us,
|
||||
L1_4us_8us,
|
||||
L1_8us_16us,
|
||||
L1_16us_32us,
|
||||
L1_32us_64us,
|
||||
L1_Above64us
|
||||
} PCI_EXPRESS_L1_EXIT_LATENCY;
|
||||
|
||||
typedef enum {
|
||||
PciExpressEndpoint = 0,
|
||||
PciExpressLegacyEndpoint,
|
||||
PciExpressRootPort = 4,
|
||||
PciExpressUpstreamSwitchPort,
|
||||
PciExpressDownstreamSwitchPort,
|
||||
PciExpressToPciXBridge,
|
||||
PciXToExpressBridge,
|
||||
PciExpressRootComplexIntegratedEndpoint,
|
||||
PciExpressRootComplexEventCollector
|
||||
} PCI_EXPRESS_DEVICE_TYPE;
|
||||
|
||||
typedef enum {
|
||||
MaxPayload128Bytes = 0,
|
||||
MaxPayload256Bytes,
|
||||
MaxPayload512Bytes,
|
||||
MaxPayload1024Bytes,
|
||||
MaxPayload2048Bytes,
|
||||
MaxPayload4096Bytes
|
||||
} PCI_EXPRESS_MAX_PAYLOAD_SIZE;
|
||||
|
||||
typedef union _PCI_EXPRESS_PME_REQUESTOR_ID {
|
||||
struct {
|
||||
USHORT FunctionNumber:3;
|
||||
USHORT DeviceNumber:5;
|
||||
USHORT BusNumber:8;
|
||||
} DUMMYSTRUCTNAME;
|
||||
USHORT AsUSHORT;
|
||||
} PCI_EXPRESS_PME_REQUESTOR_ID, *PPCI_EXPRESS_PME_REQUESTOR_ID;
|
||||
|
||||
#if defined(_WIN64)
|
||||
|
||||
#ifndef USE_DMA_MACROS
|
||||
#define USE_DMA_MACROS
|
||||
#endif
|
||||
|
||||
#ifndef NO_LEGACY_DRIVERS
|
||||
#define NO_LEGACY_DRIVERS
|
||||
#endif
|
||||
|
||||
#endif /* defined(_WIN64) */
|
||||
|
||||
typedef enum _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE {
|
||||
ResourceTypeSingle = 0,
|
||||
ResourceTypeRange,
|
||||
ResourceTypeExtendedCounterConfiguration,
|
||||
ResourceTypeOverflow,
|
||||
ResourceTypeMax
|
||||
} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE;
|
||||
|
||||
typedef struct _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR {
|
||||
PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE Type;
|
||||
ULONG Flags;
|
||||
union {
|
||||
ULONG CounterIndex;
|
||||
ULONG ExtendedRegisterAddress;
|
||||
struct {
|
||||
ULONG Begin;
|
||||
ULONG End;
|
||||
} Range;
|
||||
} u;
|
||||
} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR, *PPHYSICAL_COUNTER_RESOURCE_DESCRIPTOR;
|
||||
|
||||
typedef struct _PHYSICAL_COUNTER_RESOURCE_LIST {
|
||||
ULONG Count;
|
||||
PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR Descriptors[ANYSIZE_ARRAY];
|
||||
} PHYSICAL_COUNTER_RESOURCE_LIST, *PPHYSICAL_COUNTER_RESOURCE_LIST;
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PciPin2Line)(
|
||||
IN struct _BUS_HANDLER *BusHandler,
|
||||
IN struct _BUS_HANDLER *RootHandler,
|
||||
IN PCI_SLOT_NUMBER SlotNumber,
|
||||
IN PPCI_COMMON_CONFIG PciData);
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PciLine2Pin)(
|
||||
IN struct _BUS_HANDLER *BusHandler,
|
||||
IN struct _BUS_HANDLER *RootHandler,
|
||||
IN PCI_SLOT_NUMBER SlotNumber,
|
||||
IN PPCI_COMMON_CONFIG PciNewData,
|
||||
IN PPCI_COMMON_CONFIG PciOldData);
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PciReadWriteConfig)(
|
||||
IN struct _BUS_HANDLER *BusHandler,
|
||||
IN PCI_SLOT_NUMBER Slot,
|
||||
IN PVOID Buffer,
|
||||
IN ULONG Offset,
|
||||
IN ULONG Length);
|
||||
|
||||
#define PCI_DATA_TAG ' ICP'
|
||||
#define PCI_DATA_VERSION 1
|
||||
|
||||
typedef struct _PCIBUSDATA {
|
||||
ULONG Tag;
|
||||
ULONG Version;
|
||||
PciReadWriteConfig ReadConfig;
|
||||
PciReadWriteConfig WriteConfig;
|
||||
PciPin2Line Pin2Line;
|
||||
PciLine2Pin Line2Pin;
|
||||
PCI_SLOT_NUMBER ParentSlot;
|
||||
PVOID Reserved[4];
|
||||
} PCIBUSDATA, *PPCIBUSDATA;
|
||||
|
||||
#ifndef _PCIINTRF_X_
|
||||
#define _PCIINTRF_X_
|
||||
|
||||
typedef ULONG
|
||||
(NTAPI *PCI_READ_WRITE_CONFIG)(
|
||||
IN PVOID Context,
|
||||
IN ULONG BusOffset,
|
||||
IN ULONG Slot,
|
||||
IN PVOID Buffer,
|
||||
IN ULONG Offset,
|
||||
IN ULONG Length);
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PCI_PIN_TO_LINE)(
|
||||
IN PVOID Context,
|
||||
IN PPCI_COMMON_CONFIG PciData);
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PCI_LINE_TO_PIN)(
|
||||
IN PVOID Context,
|
||||
IN PPCI_COMMON_CONFIG PciNewData,
|
||||
IN PPCI_COMMON_CONFIG PciOldData);
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PCI_ROOT_BUS_CAPABILITY)(
|
||||
IN PVOID Context,
|
||||
OUT PPCI_ROOT_BUS_HARDWARE_CAPABILITY HardwareCapability);
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PCI_EXPRESS_WAKE_CONTROL)(
|
||||
IN PVOID Context,
|
||||
IN BOOLEAN EnableWake);
|
||||
|
||||
typedef struct _PCI_BUS_INTERFACE_STANDARD {
|
||||
USHORT Size;
|
||||
USHORT Version;
|
||||
PVOID Context;
|
||||
PINTERFACE_REFERENCE InterfaceReference;
|
||||
PINTERFACE_DEREFERENCE InterfaceDereference;
|
||||
PCI_READ_WRITE_CONFIG ReadConfig;
|
||||
PCI_READ_WRITE_CONFIG WriteConfig;
|
||||
PCI_PIN_TO_LINE PinToLine;
|
||||
PCI_LINE_TO_PIN LineToPin;
|
||||
PCI_ROOT_BUS_CAPABILITY RootBusCapability;
|
||||
PCI_EXPRESS_WAKE_CONTROL ExpressWakeControl;
|
||||
} PCI_BUS_INTERFACE_STANDARD, *PPCI_BUS_INTERFACE_STANDARD;
|
||||
|
||||
#define PCI_BUS_INTERFACE_STANDARD_VERSION 1
|
||||
|
||||
#endif /* _PCIINTRF_X_ */
|
||||
|
||||
#if (NTDDI_VERSION >= NTDDI_WIN7)
|
||||
|
||||
#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX 0x00004000
|
||||
#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX 0x00008000
|
||||
#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX \
|
||||
(FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX | \
|
||||
FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX)
|
||||
|
||||
#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_DEPRECATED 0x00000200
|
||||
#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_DEPRECATED 0x00000300
|
||||
#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_DEPRECATED 0x00000300
|
||||
|
||||
#else
|
||||
|
||||
#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL 0x00000200
|
||||
#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL 0x00000300
|
||||
#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK 0x00000300
|
||||
|
||||
#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL
|
||||
#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL
|
||||
#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK
|
||||
|
||||
#endif /* (NTDDI_VERSION >= NTDDI_WIN7) */
|
||||
|
||||
typedef enum _HAL_QUERY_INFORMATION_CLASS {
|
||||
HalInstalledBusInformation,
|
||||
HalProfileSourceInformation,
|
||||
|
|
@ -422,39 +1134,6 @@ typedef struct _PM_DISPATCH_TABLE {
|
|||
PVOID Function[1];
|
||||
} PM_DISPATCH_TABLE, *PPM_DISPATCH_TABLE;
|
||||
|
||||
typedef enum _RESOURCE_TRANSLATION_DIRECTION {
|
||||
TranslateChildToParent,
|
||||
TranslateParentToChild
|
||||
} RESOURCE_TRANSLATION_DIRECTION;
|
||||
|
||||
typedef NTSTATUS
|
||||
(NTAPI *PTRANSLATE_RESOURCE_HANDLER)(
|
||||
IN OUT PVOID Context,
|
||||
IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source,
|
||||
IN RESOURCE_TRANSLATION_DIRECTION Direction,
|
||||
IN ULONG AlternativesCount OPTIONAL,
|
||||
IN IO_RESOURCE_DESCRIPTOR Alternatives[],
|
||||
IN PDEVICE_OBJECT PhysicalDeviceObject,
|
||||
OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target);
|
||||
|
||||
typedef NTSTATUS
|
||||
(NTAPI *PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER)(
|
||||
IN PVOID Context OPTIONAL,
|
||||
IN PIO_RESOURCE_DESCRIPTOR Source,
|
||||
IN PDEVICE_OBJECT PhysicalDeviceObject,
|
||||
OUT PULONG TargetCount,
|
||||
OUT PIO_RESOURCE_DESCRIPTOR *Target);
|
||||
|
||||
typedef struct _TRANSLATOR_INTERFACE {
|
||||
USHORT Size;
|
||||
USHORT Version;
|
||||
PVOID Context;
|
||||
PINTERFACE_REFERENCE InterfaceReference;
|
||||
PINTERFACE_DEREFERENCE InterfaceDereference;
|
||||
PTRANSLATE_RESOURCE_HANDLER TranslateResources;
|
||||
PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER TranslateResourceRequirements;
|
||||
} TRANSLATOR_INTERFACE, *PTRANSLATOR_INTERFACE;
|
||||
|
||||
typedef VOID
|
||||
(FASTCALL *pHalExamineMBR)(
|
||||
IN PDEVICE_OBJECT DeviceObject,
|
||||
|
|
@ -1867,42 +2546,10 @@ FsRtlIsTotalDeviceFailure(
|
|||
|
||||
/* Hardware Abstraction Layer Types */
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PciPin2Line)(
|
||||
IN struct _BUS_HANDLER *BusHandler,
|
||||
IN struct _BUS_HANDLER *RootHandler,
|
||||
IN PCI_SLOT_NUMBER SlotNumber,
|
||||
IN PPCI_COMMON_CONFIG PciData);
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PciLine2Pin)(
|
||||
IN struct _BUS_HANDLER *BusHandler,
|
||||
IN struct _BUS_HANDLER *RootHandler,
|
||||
IN PCI_SLOT_NUMBER SlotNumber,
|
||||
IN PPCI_COMMON_CONFIG PciNewData,
|
||||
IN PPCI_COMMON_CONFIG PciOldData);
|
||||
|
||||
typedef VOID
|
||||
(NTAPI *PciReadWriteConfig)(
|
||||
IN struct _BUS_HANDLER *BusHandler,
|
||||
IN PCI_SLOT_NUMBER Slot,
|
||||
IN PVOID Buffer,
|
||||
IN ULONG Offset,
|
||||
IN ULONG Length);
|
||||
|
||||
#define PCI_DATA_TAG ' ICP'
|
||||
#define PCI_DATA_VERSION 1
|
||||
|
||||
typedef struct _PCIBUSDATA {
|
||||
ULONG Tag;
|
||||
ULONG Version;
|
||||
PciReadWriteConfig ReadConfig;
|
||||
PciReadWriteConfig WriteConfig;
|
||||
PciPin2Line Pin2Line;
|
||||
PciLine2Pin Line2Pin;
|
||||
PCI_SLOT_NUMBER ParentSlot;
|
||||
PVOID Reserved[4];
|
||||
} PCIBUSDATA, *PPCIBUSDATA;
|
||||
|
||||
/* Hardware Abstraction Layer Functions */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue