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Patch by Anton Yarotsky:
[CPORTLIB]: Implement Windows' Cp (ComPort) library. See Notes in C file. Not yet used. Based on MS Whitepaper: Building Hardware and Firmware to Complement Microsoft Windows Headless Operation. svn path=/trunk/; revision=48727
This commit is contained in:
Sir Richard
parent
228af0c797
commit
c27087c0e6
5 changed files with 420 additions and 0 deletions
108
reactos/include/reactos/drivers/serial/ns16550.h
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108
reactos/include/reactos/drivers/serial/ns16550.h
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@ -0,0 +1,108 @@
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/*
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* PROJECT: ReactOS ComPort Library
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: include/reactos/drivers/serial/ns16550.h
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* PURPOSE: Header for National Semiconductor 16550 UART
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#pragma once
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/* Note: These definitions are the internal definitions used by Microsoft serial
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driver (see src/kernel/serial.h in Windows sources). Linux uses its own, as
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do most other OS.
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*/
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#if !defined(SERIAL_REGISTER_STRIDE)
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#define SERIAL_REGISTER_STRIDE 1
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#endif
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#define RECEIVE_BUFFER_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define TRANSMIT_HOLDING_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define INTERRUPT_ENABLE_REGISTER ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
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#define INTERRUPT_IDENT_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
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#define FIFO_CONTROL_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
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#define LINE_CONTROL_REGISTER ((ULONG)((0x03)*SERIAL_REGISTER_STRIDE))
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#define MODEM_CONTROL_REGISTER ((ULONG)((0x04)*SERIAL_REGISTER_STRIDE))
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#define LINE_STATUS_REGISTER ((ULONG)((0x05)*SERIAL_REGISTER_STRIDE))
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#define MODEM_STATUS_REGISTER ((ULONG)((0x06)*SERIAL_REGISTER_STRIDE))
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#define DIVISOR_LATCH_LSB ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
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#define DIVISOR_LATCH_MSB ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
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#define SERIAL_REGISTER_SPAN ((ULONG)(7*SERIAL_REGISTER_STRIDE))
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#define SERIAL_STATUS_LENGTH ((ULONG)(1*SERIAL_REGISTER_STRIDE))
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#define SERIAL_DATA_LENGTH_5 0x00
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#define SERIAL_DATA_LENGTH_6 0x01
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#define SERIAL_DATA_LENGTH_7 0x02
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#define SERIAL_DATA_LENGTH_8 0x03
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#define SERIAL_IER_RDA 0x01
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#define SERIAL_IER_THR 0x02
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#define SERIAL_IER_RLS 0x04
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#define SERIAL_IER_MS 0x08
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#define SERIAL_IIR_RLS 0x06
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#define SERIAL_IIR_RDA 0x04
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#define SERIAL_IIR_CTI 0x0c
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#define SERIAL_IIR_THR 0x02
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#define SERIAL_IIR_MS 0x00
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#define SERIAL_IIR_FIFOS_ENABLED 0xc0
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#define SERIAL_IIR_NO_INTERRUPT_PENDING 0x01
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#define SERIAL_IIR_MUST_BE_ZERO 0x30
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#define SERIAL_FCR_ENABLE ((UCHAR)0x01)
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#define SERIAL_FCR_RCVR_RESET ((UCHAR)0x02)
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#define SERIAL_FCR_TXMT_RESET ((UCHAR)0x04)
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#define SERIAL_1_BYTE_HIGH_WATER ((UCHAR)0x00)
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#define SERIAL_4_BYTE_HIGH_WATER ((UCHAR)0x40)
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#define SERIAL_8_BYTE_HIGH_WATER ((UCHAR)0x80)
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#define SERIAL_14_BYTE_HIGH_WATER ((UCHAR)0xc0)
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#define SERIAL_LCR_DLAB 0x80
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#define SERIAL_LCR_BREAK 0x40
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#define SERIAL_5_DATA ((UCHAR)0x00)
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#define SERIAL_6_DATA ((UCHAR)0x01)
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#define SERIAL_7_DATA ((UCHAR)0x02)
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#define SERIAL_8_DATA ((UCHAR)0x03)
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#define SERIAL_DATA_MASK ((UCHAR)0x03)
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#define SERIAL_1_STOP ((UCHAR)0x00)
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#define SERIAL_1_5_STOP ((UCHAR)0x04) // Only valid for 5 data bits
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#define SERIAL_2_STOP ((UCHAR)0x04) // Not valid for 5 data bits
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#define SERIAL_STOP_MASK ((UCHAR)0x04)
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#define SERIAL_NONE_PARITY ((UCHAR)0x00)
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#define SERIAL_ODD_PARITY ((UCHAR)0x08)
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#define SERIAL_EVEN_PARITY ((UCHAR)0x18)
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#define SERIAL_MARK_PARITY ((UCHAR)0x28)
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#define SERIAL_SPACE_PARITY ((UCHAR)0x38)
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#define SERIAL_PARITY_MASK ((UCHAR)0x38)
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#define SERIAL_MCR_DTR 0x01
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#define SERIAL_MCR_RTS 0x02
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#define SERIAL_MCR_OUT1 0x04
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#define SERIAL_MCR_OUT2 0x08
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#define SERIAL_MCR_LOOP 0x10
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#define SERIAL_MCR_TL16C550CAFE 0x20
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#define SERIAL_LSR_DR 0x01
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#define SERIAL_LSR_OE 0x02
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#define SERIAL_LSR_PE 0x04
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#define SERIAL_LSR_FE 0x08
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#define SERIAL_LSR_BI 0x10
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#define SERIAL_LSR_THRE 0x20
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#define SERIAL_LSR_TEMT 0x40
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#define SERIAL_LSR_FIFOERR 0x80
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#define SERIAL_MSR_DCTS 0x01
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#define SERIAL_MSR_DDSR 0x02
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#define SERIAL_MSR_TERI 0x04
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#define SERIAL_MSR_DDCD 0x08
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#define SERIAL_MSR_CTS 0x10
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#define SERIAL_MSR_DSR 0x20
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#define SERIAL_MSR_RI 0x40
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#define SERIAL_MSR_DCD 0x80
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74
reactos/include/reactos/libs/cportlib/cportlib.h
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74
reactos/include/reactos/libs/cportlib/cportlib.h
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@ -0,0 +1,74 @@
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/*
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* PROJECT: ReactOS ComPort Library
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: include/reactos/lib/cportlib/cportlib.h
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* PURPOSE: Header for the ComPort Library
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <ntdef.h>
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#define CP_GET_SUCCESS 0
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#define CP_GET_NODATA 1
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#define CP_GET_ERROR 2
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#define CPPORT_FLAG_MODEM_CONTROL 0x02
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typedef struct _CPPORT
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{
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PUCHAR Address;
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ULONG Baud;
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USHORT Flags;
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} CPPORT, *PCPPORT;
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VOID
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NTAPI
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CpInitialize(
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IN PCPPORT Port,
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IN PUCHAR Address,
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IN ULONG Rate
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);
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VOID
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NTAPI
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CpEnableFifo(
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IN PUCHAR Address,
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IN BOOLEAN Enable
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);
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BOOLEAN
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NTAPI
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CpDoesPortExist(
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IN PUCHAR Address
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);
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UCHAR
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NTAPI
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CpReadLsr(
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IN PCPPORT Port,
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IN UCHAR ExpectedValue
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);
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VOID
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NTAPI
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CpSetBaud(
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IN PCPPORT Port,
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IN ULONG Rate
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);
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USHORT
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NTAPI
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CpGetByte(
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IN PCPPORT Port,
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IN PUCHAR Byte,
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IN BOOLEAN Wait,
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IN BOOLEAN Poll
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);
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VOID
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NTAPI
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CpPutByte(
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IN PCPPORT Port,
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IN UCHAR Byte
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);
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227
reactos/lib/cportlib/cport.c
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227
reactos/lib/cportlib/cport.c
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/*
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* PROJECT: ReactOS ComPort Library
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: lib/reactos/cportlib/cport.c
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* PURPOSE: Provides a serial port library for KDCOM, INIT, and FREELDR
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* NOTE: This library follows the precise serial port intialization steps documented
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* by Microsoft in some of their Server hardware guidance. Because they've clearly
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* documented their serial algorithms, we use the same ones to stay "compliant".
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* Do not change this code to "improve" it. It's done this way on purpose, at least on x86.
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* -- sir_richard
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*/
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/* NOTE: This code is used by Headless Support (Ntoskrnl.exe and Osloader.exe) and
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Kdcom.dll in Windows. It may be that WinDBG depends on some of these quirks.
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*/
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/* NOTE: The original code supports Modem Control. We currently do not */
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/* FIXMEs:
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- Make this serial-port specific (NS16550 vs other serial port types)
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- Get x64 KDCOM, KDBG, FREELDR, and other current code to use this
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*/
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/* INCLUDES *******************************************************************/
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#include <cportlib/cportlib.h>
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#include <drivers/serial/ns16550.h>
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#include <intrin.h>
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#include <ioaccess.h>
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#include <debug.h>
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/* GLOBALS ********************************************************************/
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UCHAR RingIndicator;
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/* FUNCTIONS ******************************************************************/
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VOID
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NTAPI
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CpInitialize(IN PCPPORT Port,
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IN PUCHAR Address,
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IN ULONG Rate)
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{
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/* Reset port data */
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Port->Address = Address;
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Port->Baud = 0;
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/* Set the baud rate */
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CpSetBaud(Port, Rate);
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/* Enable on DTR and RTS */
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WRITE_PORT_UCHAR(Address + MODEM_CONTROL_REGISTER,
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SERIAL_MCR_DTR | SERIAL_MCR_RTS);
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/* Disable interrupts */
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WRITE_PORT_UCHAR(Address + INTERRUPT_ENABLE_REGISTER, 0);
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}
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VOID
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NTAPI
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CpEnableFifo(IN PUCHAR Address,
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IN BOOLEAN Enable)
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{
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/* Set FIFO */
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WRITE_PORT_UCHAR(Address + FIFO_CONTROL_REGISTER, Enable ? SERIAL_FCR_ENABLE : 0);
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}
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BOOLEAN
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NTAPI
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CpDoesPortExist(IN PUCHAR Address)
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{
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UCHAR Old;
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/*
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* See "Building Hardware and Firmware to Complement Microsoft Windows Headless Operation"
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* Out-of-Band Management Port Device Requirements:
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* The device must act as a 16550 or 16450 UART.
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* Windows Server 2003 will test this device using the following process.
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* 1. Save off the current modem status register.
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* 2. Place the UART into diagnostic mode (The UART is placed into loopback mode
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* by writing SERIAL_MCR_LOOP to the modem control register).
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* 3. The modem status register is read and the high bits are checked. This means
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* SERIAL_MSR_CTS, SERIAL_MSR_DSR, SERIAL_MSR_RI and SERIAL_MSR_DCD should
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* all be clear.
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* 4. Place the UART in diagnostic mode and turn on OUTPUT (Loopback Mode and
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* OUTPUT are both turned on by writing (SERIAL_MCR_LOOP | SERIAL_MCR_OUT1)
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* to the modem control register).
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* 5. The modem status register is read and the ring indicator is checked.
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* This means SERIAL_MSR_RI should be set.
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* 6. Restore original modem status register.
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*/
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Old = READ_PORT_UCHAR(Address + MODEM_CONTROL_REGISTER);
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WRITE_PORT_UCHAR(Address + MODEM_CONTROL_REGISTER, SERIAL_MCR_LOOP);
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WRITE_PORT_UCHAR(Address + MODEM_CONTROL_REGISTER, SERIAL_MCR_LOOP);
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if (!(READ_PORT_UCHAR(Address + MODEM_STATUS_REGISTER) &
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(SERIAL_MSR_CTS | SERIAL_MSR_DSR | SERIAL_MSR_RI | SERIAL_MSR_DCD)))
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{
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WRITE_PORT_UCHAR(Address + MODEM_CONTROL_REGISTER,
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(SERIAL_MCR_OUT1 | SERIAL_MCR_LOOP));
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if (READ_PORT_UCHAR(Address + MODEM_STATUS_REGISTER) & SERIAL_MSR_RI)
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{
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WRITE_PORT_UCHAR(Address + MODEM_CONTROL_REGISTER, Old);
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return TRUE;
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}
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}
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WRITE_PORT_UCHAR(Address + MODEM_CONTROL_REGISTER, Old);
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return FALSE;
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}
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UCHAR
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NTAPI
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CpReadLsr(IN PCPPORT Port,
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IN UCHAR ExpectedValue)
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{
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UCHAR Lsr, Msr;
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/* Read the LSR and check if the expected value is present */
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Lsr = READ_PORT_UCHAR(Port->Address + LINE_STATUS_REGISTER);
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if (!(Lsr & ExpectedValue))
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{
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/* Check the MSR for ring indicator toggle */
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Msr = READ_PORT_UCHAR(Port->Address + MODEM_STATUS_REGISTER);
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/* If the indicator reaches 3, we've seen this on/off twice */
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RingIndicator |= (Msr & SERIAL_MSR_RI) ? 1 : 2;
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if (RingIndicator == 3) Port->Flags |= CPPORT_FLAG_MODEM_CONTROL;
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}
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return Lsr;
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}
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VOID
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NTAPI
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CpSetBaud(IN PCPPORT Port,
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IN ULONG Rate)
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{
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UCHAR Lcr;
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USHORT Mode;
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/* Add DLAB */
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Lcr = READ_PORT_UCHAR(Port->Address + LINE_CONTROL_REGISTER);
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WRITE_PORT_UCHAR(Port->Address + LINE_CONTROL_REGISTER, Lcr | SERIAL_LCR_DLAB);
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/* Set baud rate */
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Mode = 115200 / Rate;
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WRITE_PORT_UCHAR(Port->Address + DIVISOR_LATCH_MSB, (UCHAR)((Mode >> 8) & 0xff));
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WRITE_PORT_UCHAR(Port->Address + DIVISOR_LATCH_LSB, (UCHAR)(Mode & 0xff));
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/* Reset DLAB and set 8 data bits, 1 stop bit, no parity, no break */
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WRITE_PORT_UCHAR(Port->Address + LINE_CONTROL_REGISTER,
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SERIAL_8_DATA | SERIAL_1_STOP | SERIAL_NONE_PARITY);
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/* Save baud rate in port */
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Port->Baud = Rate;
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}
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USHORT
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NTAPI
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CpGetByte(IN PCPPORT Port,
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IN PUCHAR Byte,
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IN BOOLEAN Wait,
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IN BOOLEAN Poll)
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{
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UCHAR Lsr;
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ULONG i;
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/* Handle early read-before-init */
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if (!Port->Address) return CP_GET_NODATA;
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/* If "wait" mode enabled, spin many times, otherwise attempt just once */
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i = Wait ? 204800 : 1;
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while (i--)
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{
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/* Read LSR for data ready */
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Lsr = CpReadLsr(Port, SERIAL_LSR_DR);
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if ((Lsr & SERIAL_LSR_DR) == SERIAL_LSR_DR)
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{
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/* If an error happened, clear the byte and fail */
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if (Lsr & (SERIAL_LSR_FE | SERIAL_LSR_PE))
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{
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*Byte = 0;
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return CP_GET_ERROR;
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}
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/* If only polling was requested by caller, return now */
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if (Poll) return CP_GET_SUCCESS;
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/* Otherwise read the byte and return it */
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*Byte = READ_PORT_UCHAR(Port->Address + RECEIVE_BUFFER_REGISTER);
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/* Handle CD if port is in modem control mode */
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if (Port->Flags & CPPORT_FLAG_MODEM_CONTROL)
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{
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/* Not implemented yet */
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DPRINT1("CP: CPPORT_FLAG_MODEM_CONTROL unexpected\n");
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}
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/* Byte was read */
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return CP_GET_SUCCESS;
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}
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}
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/* Reset LSR, no data was found */
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CpReadLsr(Port, 0);
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return CP_GET_NODATA;
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}
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VOID
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NTAPI
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CpPutByte(IN PCPPORT Port,
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IN UCHAR Byte)
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{
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/* Check if port is in modem control to handle CD */
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while (Port->Flags & CPPORT_FLAG_MODEM_CONTROL)
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{
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/* Not implemented yet */
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DPRINT1("CP: CPPORT_FLAG_MODEM_CONTROL unexpected\n");
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}
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/* Wait for LSR to say we can go ahead */
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while (!(CpReadLsr(Port, SERIAL_LSR_THRE) & SERIAL_LSR_THRE));
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/* Send the byte */
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WRITE_PORT_UCHAR(Port->Address + RECEIVE_BUFFER_REGISTER, Byte);
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}
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8
reactos/lib/cportlib/cportlib.rbuild
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8
reactos/lib/cportlib/cportlib.rbuild
Normal file
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<?xml version="1.0"?>
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<!DOCTYPE module SYSTEM "../../tools/rbuild/project.dtd">
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<group>
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<module name="cportlib" type="staticlibrary">
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<include base="cportlib">.</include>
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<file>cport.c</file>
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</module>
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</group>
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@ -13,6 +13,9 @@
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<directory name="cmlib">
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<xi:include href="cmlib/cmlib.rbuild" />
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</directory>
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<directory name="cportlib">
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<xi:include href="cportlib/cportlib.rbuild" />
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</directory>
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<directory name="debugsup">
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<xi:include href="debugsup/debugsup.rbuild" />
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</directory>
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