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[FREELDR] Add ARC-emulation support for NEC PC-98 series
- Add ARC-emulation support for NEC PC-98 series - Add global definition for PC-98 port into CMakeLists.txt - Add floppy verison of freeldr.ini for PC-98 CD boot
This commit is contained in:
Dmitry Borisov
Hermès BÉLUSCA - MAÏTO
parent
9ccd179e4a
commit
c14cc22bfd
22 changed files with 3853 additions and 29 deletions
26
sdk/include/reactos/drivers/pc98/fdc.h
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26
sdk/include/reactos/drivers/pc98/fdc.h
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/*
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* PROJECT: NEC PC-98 series onboard hardware
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: NEC uPD765A FDC header file
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* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
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*/
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#pragma once
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#define FDC1_IO_BASE 0x90
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#define FDC2_IO_BASE 0xC8
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#define FDC_IO_o_MODE_SWITCH 0xBE
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#define FDC_IO_o_EMODE_SWITCH 0x4BE
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#define FDC_IO_i_MODE 0xBE
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#define FDC_IO_i_EMODE 0x4BE
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/*
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* FDC registers offsets
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*/
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#define FDC_o_DATA 0x02
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#define FDC_o_CONTROL 0x04
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#define FDC_i_STATUS 0x00
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#define FDC_i_DATA 0x02
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#define FDC_i_READ_SWITCH 0x04
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279
sdk/include/reactos/drivers/pc98/video.h
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279
sdk/include/reactos/drivers/pc98/video.h
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/*
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* PROJECT: NEC PC-98 series onboard hardware
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: Graphics system header file
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* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
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*/
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#pragma once
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/* Video memory ***************************************************************/
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#define VRAM_NORMAL_PLANE_B 0xA8000
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#define VRAM_NORMAL_PLANE_G 0xB0000
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#define VRAM_NORMAL_PLANE_R 0xB8000
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#define VRAM_NORMAL_PLANE_I 0xE0000
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#define VRAM_PLANE_SIZE 0x08000
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#define VRAM_NORMAL_TEXT 0xA0000
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#define VRAM_TEXT_ATTR_OFFSET 0x02000
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#define VRAM_TEXT_SIZE 0x02000
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#define VRAM_ATTR_SIZE 0x02000
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/* High-resolution machine */
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#define VRAM_HI_RESO_PLANE_B 0xC0000
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#define VRAM_HI_RESO_PLANE_G 0xC8000
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#define VRAM_HI_RESO_PLANE_R 0xD0000
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#define VRAM_HI_RESO_PLANE_I 0xD8000
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#define VRAM_HI_RESO_TEXT 0xE0000
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/* GDC definitions ************************************************************/
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#define GDC_STATUS_DRDY 0x01
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#define GDC_STATUS_FIFO_FULL 0x02
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#define GDC_STATUS_FIFO_EMPTY 0x04
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#define GDC_STATUS_DRAWING 0x08
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#define GDC_STATUS_DMA_EXECUTE 0x10
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#define GDC_STATUS_VSYNC 0x20
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#define GDC_STATUS_HBLANK 0x40
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#define GDC_STATUS_LPEN 0x80
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#define GDC_ATTR_VISIBLE 0x01
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#define GDC_ATTR_BLINK 0x02
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#define GDC_ATTR_REVERSE 0x04
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#define GDC_ATTR_UNDERLINE 0x08
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#define GDC_ATTR_VERTICAL_LINE 0x10
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#define GDC_ATTR_BLACK 0x00
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#define GDC_ATTR_BLUE 0x20
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#define GDC_ATTR_RED 0x40
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#define GDC_ATTR_PURPLE 0x60
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#define GDC_ATTR_GREEN 0x80
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#define GDC_ATTR_LIGHTBLUE 0xA0
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#define GDC_ATTR_YELLOW 0xC0
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#define GDC_ATTR_WHITE 0xE0
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#define GDC_COMMAND_RESET 0x00
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#define GDC_COMMAND_BCTRL_STOP 0x0C
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#define GDC_COMMAND_BCTRL_START 0x0D
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#define GDC_COMMAND_SYNC_ON 0x0E
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#define GDC_COMMAND_SYNC_OFF 0x0F
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#define GDC_COMMAND_WRITE 0x20
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#define GDC_COMMAND_SLAVE 0x6E
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#define GDC_COMMAND_MASTER 0x6F
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#define GDC_COMMAND_CSRFORM 0x4B
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typedef struct _CSRFORMPARAM
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{
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BOOLEAN Show;
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BOOLEAN Blink;
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UCHAR BlinkRate;
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UCHAR LinesPerRow;
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UCHAR StartScanLine;
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UCHAR EndScanLine;
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} CSRFORMPARAM, *PCSRFORMPARAM;
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FORCEINLINE
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VOID
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WRITE_GDC_CSRFORM(PUCHAR Port, PCSRFORMPARAM CursorParameters)
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{
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WRITE_PORT_UCHAR(Port, ((CursorParameters->Show & 0x01) << 7) |
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(CursorParameters->LinesPerRow - 1));
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WRITE_PORT_UCHAR(Port, ((CursorParameters->BlinkRate & 0x03) << 6) |
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((!CursorParameters->Blink & 0x01) << 5) | CursorParameters->StartScanLine);
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WRITE_PORT_UCHAR(Port, (CursorParameters->EndScanLine << 3) | ((CursorParameters->BlinkRate & 0x1C) >> 2));
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}
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#define GDC_COMMAND_START 0x6B
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#define GDC_COMMAND_ZOOM 0x46
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#define GDC_COMMAND_CSRW 0x49
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typedef struct _CSRWPARAM
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{
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ULONG CursorAdress;
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UCHAR DotAddress;
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} CSRWPARAM, *PCSRWPARAM;
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FORCEINLINE
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VOID
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WRITE_GDC_CSRW(PUCHAR Port, PCSRWPARAM CursorParameters)
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{
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ASSERT(CursorParameters->CursorAdress < 0xF00000);
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ASSERT(CursorParameters->DotAddress < 0x10);
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WRITE_PORT_UCHAR(Port, CursorParameters->CursorAdress & 0xFF);
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WRITE_PORT_UCHAR(Port, (CursorParameters->CursorAdress >> 8) & 0xFF);
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WRITE_PORT_UCHAR(Port, (CursorParameters->DotAddress << 4) |
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((CursorParameters->CursorAdress >> 16) & 0x03));
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}
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#define GDC_COMMAND_PRAM 0x70
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#define GDC_COMMAND_PITCH 0x47
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#define GDC_COMMAND_MASK 0x4A
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#define GDC_COMMAND_FIGS 0x4C
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#define GDC_COMMAND_FIGD 0x6C
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#define GDC_COMMAND_GCHRD 0x68
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#define GDC_COMMAND_READ 0xA0
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#define GDC_COMMAND_CURD 0xE0
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#define GDC_COMMAND_LPRD 0xC0
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#define GDC_COMMAND_DMAR 0xA4
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#define GDC_COMMAND_DMAW 0x24
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/* Master GDC *****************************************************************/
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#define GDC1_IO_i_STATUS 0x60
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#define GDC1_IO_i_DATA 0x62
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#define GDC1_IO_i_MODE_FLIPFLOP1 0x68
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#define GDC1_IO_o_PARAM 0x60
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#define GDC1_IO_o_COMMAND 0x62
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#define GDC1_IO_o_VSYNC 0x64 /* CRT interrupt reset */
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#define GDC1_IO_o_MODE_FLIPFLOP1 0x68
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#define GDC1_MODE_VERTICAL_LINE 0x00 /* Character attribute */
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#define GDC1_MODE_SIMPLE_GRAPHICS 0x01
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#define GDC1_MODE_COLORED 0x02
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#define GDC1_MODE_MONOCHROME 0x03
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#define GDC1_MODE_COLS_80 0x04
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#define GDC1_MODE_COLS_40 0x05
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#define GDC1_MODE_ANK_6_8 0x06
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#define GDC1_MODE_ANK_7_13 0x07
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#define GDC1_MODE_LINES_400 0x08
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#define GDC1_MODE_LINES_200 0x09 /* Hide odd raster line */
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#define GDC1_MODE_KCG_CODE 0x0A /* CG access during V-SYNC */
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#define GDC1_MODE_KCG_BITMAP 0x0B
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#define GDC1_NVMW_PROTECT 0x0C
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#define GDC1_NVMW_UNPROTECT 0x0D /* Memory at TextVramSegment:(3FE2-3FFEh) */
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#define GDC1_MODE_DISPLAY_DISABLE 0x0E
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#define GDC1_MODE_DISPLAY_ENABLE 0x0F
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#define GDC1_IO_o_BORDER_COLOR 0x6C /* PC-H98 */
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/* Slave GDC ******************************************************************/
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#define GDC2_IO_i_STATUS 0xA0
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#define GDC2_IO_i_DATA 0xA2
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#define GDC2_IO_i_VIDEO_PAGE 0xA4
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#define GDC2_IO_i_VIDEO_PAGE_ACCESS 0xA6
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#define GDC2_IO_i_PALETTE_INDEX 0xA8
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#define GDC2_IO_i_GREEN 0xAA
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#define GDC2_IO_i_RED 0xAC
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#define GDC2_IO_i_BLUE 0xAE
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#define GDC2_IO_i_MODE_FLIPFLOP2 0x6A
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#define GDC2_IO_i_MODE_FLIPFLOP3 0x6E
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#define GDC2_IO_o_PARAM 0xA0
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#define GDC2_IO_o_COMMAND 0xA2
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#define GDC2_IO_o_VIDEO_PAGE 0xA4 /* Video page to display (invalid in 480 height mode) */
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#define GDC2_IO_o_VIDEO_PAGE_ACCESS 0xA6 /* Video page to CPU access */
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#define GDC2_IO_o_PALETTE_INDEX 0xA8
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#define GDC2_IO_o_GREEN 0xAA
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#define GDC2_IO_o_RED 0xAC
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#define GDC2_IO_o_BLUE 0xAE
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#define GDC2_IO_o_MODE_FLIPFLOP2 0x6A
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#define GDC2_MODE_COLORS_8 0x00
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#define GDC2_MODE_COLORS_16 0x01
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#define GDC2_MODE_GRCG 0x04
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#define GDC2_MODE_EGC 0x05
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#define GDC2_EGC_FF_PROTECT 0x06
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#define GDC2_EGC_FF_UNPROTECT 0x07 /* Unprotect the EGC F/F registers */
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#define GDC2_MODE_PEGS_DISABLE 0x20
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#define GDC2_MODE_PEGC_ENABLE 0x21
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// #define GDC2_MODE_ 0x26
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// #define GDC2_MODE_ 0x27
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// #define GDC2_MODE_ 0x28
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// #define GDC2_MODE_ 0x29
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// #define GDC2_MODE_ 0x2A
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// #define GDC2_MODE_ 0x2B
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// #define GDC2_MODE_ 0x2C
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// #define GDC2_MODE_ 0x2D
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#define GDC2_MODE_CRT 0x40
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#define GDC2_MODE_LCD 0x41
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// #define GDC2_MODE_VRAM_PLAIN 0x62 /* PC-H98 */
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// #define GDC2_MODE_VRAM_PACKED 0x63
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#define GDC2_MODE_LINES_400 0x68 /* 128 kB VRAM boundary */
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#define GDC2_MODE_LINES_800 0x69 /* 256 kB VRAM boundary */
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// #define GDC2_MODE_ 0x6C
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// #define GDC2_MODE_ 0x6D
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#define GDC2_CLOCK1_2_5MHZ 0x82
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#define GDC2_CLOCK1_5MHZ 0x83
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#define GDC2_CLOCK2_2_5MHZ 0x84
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#define GDC2_CLOCK2_5MHZ 0x85
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#define GDC2_IO_o_MODE_FLIPFLOP3 0x6E
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// #define GDC2_MODE_ 0x02
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// #define GDC2_MODE_ 0x03
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// #define GDC2_MODE_ 0x08
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// #define GDC2_MODE_ 0x09
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// #define GDC2_MODE_ 0x0A
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// #define GDC2_MODE_ 0x0B
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// #define GDC2_MODE_ 0x0C
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// #define GDC2_MODE_ 0x0D
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// #define GDC2_MODE_ 0x0E
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// #define GDC2_MODE_ 0x0F
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// #define GDC2_MODE_ 0x14
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// #define GDC2_MODE_ 0x15
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FORCEINLINE
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VOID
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WRITE_GDC1_COMMAND(UCHAR Command)
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{
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while (!(READ_PORT_UCHAR((PUCHAR)GDC1_IO_i_STATUS) & GDC_STATUS_FIFO_EMPTY))
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NOTHING;
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WRITE_PORT_UCHAR((PUCHAR)GDC1_IO_o_COMMAND, Command);
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}
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FORCEINLINE
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VOID
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WRITE_GDC2_COMMAND(UCHAR Command)
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{
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while (!(READ_PORT_UCHAR((PUCHAR)GDC2_IO_i_STATUS) & GDC_STATUS_FIFO_EMPTY))
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NOTHING;
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WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_COMMAND, Command);
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}
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/* CRT Controller *************************************************************/
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#define CRTC_IO_o_SCANLINE_START 0x70
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#define CRTC_IO_o_SCANLINE_END 0x72
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#define CRTC_IO_o_SCANLINE_BLANK_AT 0x74
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#define CRTC_IO_o_SCANLINES 0x76
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#define CRTC_IO_o_SUR 0x78
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#define CRTC_IO_o_SDR 0x7A
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/* GRCG (Graphic Charger) *****************************************************/
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#define GRCG_IO_i_MODE 0x7C
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#define GRCG_IO_o_MODE 0x7C
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typedef union _GRCG_MODE_REGISTER
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{
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struct
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{
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UCHAR DisablePlaneB:1;
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UCHAR DisablePlaneR:1;
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UCHAR DisablePlaneG:1;
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UCHAR DisablePlaneI:1;
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UCHAR Unused:2;
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UCHAR Mode:1;
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#define GRCG_MODE_TILE_DIRECT_WRITE 0
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#define GRCG_MODE_TILE_COMPARE_READ 0
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#define GRCG_MODE_READ_MODIFY_WRITE 1
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UCHAR Enable:1;
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};
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UCHAR Bits;
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} GRCG_MODE_REGISTER, *PGRCG_MODE_REGISTER;
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#define GRCG_IO_o_TILE_PATTERN 0x7E
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/* CG Window ******************************************************************/
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#define KCG_IO_o_CHARCODE_HIGH 0xA1
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#define KCG_IO_o_CHARCODE_LOW 0xA3
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#define KCG_IO_o_LINE 0xA5
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#define KCG_IO_o_PATTERN 0xA9
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#define KCG_IO_i_PATTERN 0xA9
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