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- Add inital support for PCI and ISA interrupts.
- Use different register allocation to be more efficient on certain systems. - Add tables and initial code for Lazy IRQL support. svn path=/trunk/; revision=44115
This commit is contained in:
Stefan Ginsberg
parent
8e510a0ea2
commit
c02b96254e
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@ -69,25 +69,73 @@ KiI8259MaskTable:
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.long 0xFFFFFFFB /* IRQL 30 */
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.long 0xFFFFFFFB /* IRQL 31 */
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HalpSysIntHandler:
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.rept 7
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FindHigherIrqlMask:
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.long 0xFFFFFFFE /* IRQL 0 */
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.long 0xFFFFFFFC /* IRQL 1 */
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.long 0xFFFFFFF8 /* IRQL 2 */
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.long 0xFFFFFFF0 /* IRQL 3 */
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.long 0x7FFFFF0 /* IRQL 4 */
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.long 0x3FFFFF0 /* IRQL 5 */
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.long 0x1FFFFF0 /* IRQL 6 */
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.long 0x0FFFFF0 /* IRQL 7 */
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.long 0x7FFFF0 /* IRQL 8 */
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.long 0x3FFFF0 /* IRQL 9 */
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.long 0x1FFFF0 /* IRQL 10 */
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.long 0x0FFFF0 /* IRQL 11 */
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.long 0x7FFF0 /* IRQL 12 */
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.long 0x3FFF0 /* IRQL 13 */
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.long 0x1FFF0 /* IRQL 14 */
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.long 0x0FFF0 /* IRQL 15 */
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.long 0x7FF0 /* IRQL 16 */
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.long 0x3FF0 /* IRQL 17 */
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.long 0x1FF0 /* IRQL 18 */
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.long 0x1FF0 /* IRQL 19 */
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.long 0x17F0 /* IRQL 20 */
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.long 0x13F0 /* IRQL 21 */
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.long 0x11F0 /* IRQL 22 */
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.long 0x10F0 /* IRQL 23 */
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.long 0x1070 /* IRQL 24 */
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.long 0x1030 /* IRQL 25 */
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.long 0x1010 /* IRQL 26 */
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.long 0x10 /* IRQL 27 */
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.long 0 /* IRQL 28 */
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.long 0 /* IRQL 29 */
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.long 0 /* IRQL 30 */
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.long 0 /* IRQL 31 */
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HalpSpecialDismissTable:
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.rept 7
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.long GenericIRQ /* IRQ 0-7 */
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.endr
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.endr
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.long IRQ7 /* IRQ 7 */
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.rept 7
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.long GenericIRQ /* IRQ 8-15 */
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.endr
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.rept 5
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.long GenericIRQ /* IRQ 8-12 */
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.endr
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.long IRQ13 /* IRQ 13 */
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.long GenericIRQ /* IRQ 14 */
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.long IRQ15 /* IRQ 15 */
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.rept 20
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.rept 20
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.long GenericIRQ /* IRQ 16-35 */
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.endr
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.endr
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#if DBG
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.rept 172
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.long InvalidIRQ /* IRQ 36-207 */
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.endr
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#endif
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SoftIntByteTable:
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HalpSpecialDismissLevelTable:
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.rept 7
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.long GenericIRQLevel /* IRQ 0-7 */
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.endr
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.long IRQ7Level /* IRQ 7 */
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.rept 5
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.long GenericIRQLevel /* IRQ 8-12 */
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.endr
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.long IRQ13Level /* IRQ 13 */
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.long GenericIRQLevel /* IRQ 14 */
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.long IRQ15Level /* IRQ 15 */
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SWInterruptLookUpTable:
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.byte PASSIVE_LEVEL /* IRR 0 */
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.byte PASSIVE_LEVEL /* IRR 1 */
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.byte APC_LEVEL /* IRR 2 */
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@ -97,12 +145,12 @@ SoftIntByteTable:
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.byte DISPATCH_LEVEL /* IRR 6 */
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.byte DISPATCH_LEVEL /* IRR 7 */
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SoftIntHandlerTable:
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SWInterruptHandlerTable:
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.long _KiUnexpectedInterrupt /* PASSIVE_LEVEL */
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.long _HalpApcInterrupt /* APC_LEVEL */
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.long _HalpDispatchInterrupt /* DISPATCH_LEVEL */
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SoftIntHandlerTable2:
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SWInterruptHandlerTable2:
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.long _KiUnexpectedInterrupt /* PASSIVE_LEVEL */
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.long _HalpApcInterrupt2ndEntry /* APC_LEVEL */
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.long _HalpDispatchInterrupt2ndEntry /* DISPATCH_LEVEL */
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@ -112,6 +160,39 @@ _UnhandledMsg:
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/* FUNCTIONS *****************************************************************/
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/* HAL interrupt handlers */
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GENERATE_HAL_INT_HANDLERS
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.globl _HalpHardwareInterruptLevel
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.func HalpHardwareInterruptLevel
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_HalpHardwareInterruptLevel:
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/* Get IRQL and check for pending interrupts */
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mov eax, PCR[KPCR_IRQL]
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mov ecx, PCR[KPCR_IRR]
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and ecx, FindHigherIrqlMask[eax*4]
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jz NothingHardware
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/* Check the active IRR */
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test dword ptr PCR[KPCR_IRR_ACTIVE], 0xFFFFFFF0
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jnz NothingHardware
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/* Check for pending software interrupts */
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mov eax, ecx
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bsr ecx, eax
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mov eax, 1
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shl eax, cl
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/* Clear IRR */
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xor PCR[KPCR_IRR], eax
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/* Now dispatch the interrupt */
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call SWInterruptHandlerTable[ecx*4]
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NothingHardware:
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ret
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.endfunc
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.globl _HalpInitPICs@0
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.func HalpInitPICs@0
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_HalpInitPICs@0:
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@ -150,7 +231,23 @@ InitLoop:
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cmp ax, 0
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jnz InitLoop
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/* Restore interrupts and return */
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/* Read EISA Edge/Level Register */
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mov edx, 0x4D1
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in al, dx
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mov ah, al
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dec edx
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in al, dx
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/* Clear reserved bits and see if there's anything there */
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and eax, 0xDEF8
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cmp eax, 0xDEF8
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jz NoEisa
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/* FIXME */
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//UNHANDLED_PATH
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/* Restore interrupts and return */
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NoEisa:
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popf
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pop esi
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ret
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@ -192,12 +289,12 @@ InitLoop:
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/* Get highest pending software interrupt and check if it's higher */
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xor edx, edx
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mov dl, SoftIntByteTable[eax]
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mov dl, SWInterruptLookUpTable[eax]
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cmp dl, cl
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jbe AfterCall
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/* Call the pending interrupt */
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call SoftIntHandlerTable[edx*4]
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call SWInterruptHandlerTable[edx*4]
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AfterCall:
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@ -249,38 +346,53 @@ _HalEnableSystemInterrupt@12:
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cmp ecx, CLOCK2_LEVEL
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jnb Invalid
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/* Get the current PCI Edge/Level control registers */
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mov edx, 0x4D1
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in al, dx
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shl ax, 8
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mov edx, 0x4D0
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in al, dx
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mov dx, 1
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shl dx, cl
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and dx, 0xDEF8
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#if 0
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/* Is PCI IRQ Routing enabled? */
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cmp byte ptr _HalpIrqMiniportInitialized, 0
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jz NoMiniport
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/* Check if this is a latched interrupt */
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cmp dword ptr [esp+12], 0
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/* UNHANDLED */
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UNHANDLED_PATH
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NoMiniport:
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/* Check if this is an EISA IRQ */
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bt _HalpEisaIrqIgnore, ecx
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jb IgnoredIrq
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/* Clear the EISA Edge/Level Control Register */
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btr _HalpEisaELCR, ecx
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/* Get the interrupt type */
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mov al, [esp+12]
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cmp al, 0
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jnz Latched
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/* Use OR for edge interrupt */
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or ax, dx
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jmp AfterMask
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/* Check the register again */
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bt _HalpEisaELCR, ecx
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jb Dismiss
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/* Check if the miniport is active */
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cmp byte ptr _HalpIrqMiniportInitialized, 0
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jz Dismiss
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/* Update the EISA Edge/Level Control Register */
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bts _HalpEisaELCR, ecx
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Dismiss:
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/* Use the level hardware interrupt handler */
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mov dword ptr SWInterruptHandlerTableHardware[ecx*4], offset _HalpHardwareInterruptLevel
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mov edx, HalpSpecialDismissLevelTable[ecx*4]
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mov HalpSpecialDismissTable[ecx*4], edx
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Latched:
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/* Is PCI IRQ Routing enabled? */
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cmp byte ptr _HalpIrqMiniportInitialized, 0
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jz IgnoredIrq
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/* Mask it out for level interrupt */
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not dx
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and ax, dx
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AfterMask:
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/* Set the PCI Edge/Level control registers */
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mov edx, 0x4D0
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out dx, al
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shr ax, 8
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mov edx, 0x4D1
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out dx, al
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/* UNHANDLED */
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UNHANDLED_PATH
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#endif
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IgnoredIrq:
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/* Calculate the new IDR */
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mov eax, 1
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shl eax, cl
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@ -316,9 +428,10 @@ Invalid:
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_HalBeginSystemInterrupt@12:
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/* Convert to IRQ and call the handler */
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movzx ebx, byte ptr [esp+8]
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sub ebx, PRIMARY_VECTOR_BASE
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jmp HalpSysIntHandler[ebx*4]
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xor ecx, ecx
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mov cl, byte ptr [esp+8]
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sub ecx, PRIMARY_VECTOR_BASE
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jmp HalpSpecialDismissTable[ecx*4]
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IRQ15:
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/* This is IRQ 15, check if it's spurious */
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@ -330,6 +443,7 @@ IRQ15:
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jnz GenericIRQ
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/* Cascaded interrupt... dismiss it and return FALSE */
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CascadedInterrupt:
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mov al, 0x62
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out 0x20, al
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mov eax, 0
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@ -348,15 +462,21 @@ IRQ7:
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mov eax, 0
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ret 12
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GenericIRQ:
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/* Return the current IRQL */
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mov eax, [esp+12]
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mov ecx, PCR[KPCR_IRQL]
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mov [eax], cl
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IRQ13:
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/* AT 80287 latch clear */
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xor al, al
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out 0xF0, al
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/* Set the new IRQL */
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movzx eax, byte ptr [esp+4]
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GenericIRQ:
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/* Get current and new IRQL */
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xor eax, eax
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mov al, byte ptr [esp+4]
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mov ebx, PCR[KPCR_IRQL]
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/* Set and save old */
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mov PCR[KPCR_IRQL], eax
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mov edx, [esp+12]
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mov [edx], bl
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/* Set IRQ mask in the PIC */
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mov eax, KiI8259MaskTable[eax*4]
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@ -366,14 +486,18 @@ GenericIRQ:
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out 0xA1, al
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/* Check to which PIC the EOI was sent */
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mov eax, ebx
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mov eax, ecx
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cmp eax, 8
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jnb Pic1
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/* Write mask to master PIC */
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or al, 0x60
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out 0x20, al
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jmp DoneBegin
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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Pic1:
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/* Write mask to slave PIC */
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@ -382,9 +506,7 @@ Pic1:
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mov al, 0x62
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out 0x20, al
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DoneBegin:
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/* Enable interrupts and return TRUE */
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in al, 0x21
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sti
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mov eax, 1
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ret 12
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@ -397,12 +519,111 @@ InvalidIRQ:
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#endif
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.endfunc
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IRQ15Level:
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/* This is IRQ 15, check if it's spurious */
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mov al, 0xB
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out 0xA0, al
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jmp $+2
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in al, 0xA0
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test al, 0x80
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jnz GenericIRQLevel
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jmp CascadedInterrupt
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IRQ7Level:
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/* This is IRQ 7, check if it's spurious */
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mov al, 0xB
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out 0x20, al
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jmp $+2
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in al, 0x20
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test al, 0x80
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jnz GenericIRQLevel
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/* It is, return FALSE */
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SpuriousInterrupt:
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mov eax, 0
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ret 12
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IRQ13Level:
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/* AT 80287 latch clear */
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xor al, al
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out 0xF0, al
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GenericIRQLevel:
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/* Save IRQL */
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xor eax, eax
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mov al, [esp+4]
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/* Set IRQ mask in the PIC */
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mov eax, KiI8259MaskTable[eax*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Compute new IRR */
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mov eax, ecx
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mov ebx, 1
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add ecx, 4
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shl ebx, cl
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or PCR[KPCR_IRR], ebx
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/* Get IRQLs */
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mov cl, [esp+4]
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mov bl, PCR[KPCR_IRQL]
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mov edx, [esp+12]
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/* Check to which PIC the EOI was sent */
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cmp eax, 8
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jnb Pic1Level
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/* Write mask to master PIC */
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or al, 0x60
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out 0x20, al
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/* Check for spurious */
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cmp cl, bl
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jbe SpuriousInterrupt
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/* Write IRQL values */
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movzx ecx, cl
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mov PCR[KPCR_IRQL], ecx
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mov [edx], bl
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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Pic1Level:
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/* Write mask to slave and master PIC */
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add al, 0x58
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out 0xA0, al
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mov al, 0x62
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out 0x20, al
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/* Was this a lower interrupt? */
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cmp cl, bl
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jbe SpuriousInterrupt
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/* Write IRQL values */
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movzx ecx, cl
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mov PCR[KPCR_IRQL], ecx
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mov [edx], bl
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/* Enable interrupts and return TRUE */
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sti
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mov eax, 1
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ret 12
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.globl _HalEndSystemInterrupt@8
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.func HalEndSystemInterrupt@8
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_HalEndSystemInterrupt@8:
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/* Get the IRQL and check if it's a software interrupt */
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movzx ecx, byte ptr [esp+4]
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/* Read IRQL */
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xor ecx, ecx
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mov cl, [esp+4]
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/* Check if it's a software interrupt */
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cmp dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
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jbe SkipMask2
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@ -418,7 +639,7 @@ SkipMask2:
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/* Set IRQL and check if there are pending software interrupts */
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mov PCR[KPCR_IRQL], ecx
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mov eax, PCR[KPCR_IRR]
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mov al, SoftIntByteTable[eax]
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mov al, SWInterruptLookUpTable[eax]
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cmp al, cl
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ja DoCall
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ret 8
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@ -427,7 +648,7 @@ DoCall:
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/* There are pending software interrupts, call their handlers */
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add esp, 12
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jmp SoftIntHandlerTable2[eax*4]
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jmp SWInterruptHandlerTable2[eax*4]
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.endfunc
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.globl @KfLowerIrql@4
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@ -435,19 +656,21 @@ DoCall:
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_@KfLowerIrql@4:
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@KfLowerIrql@4:
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/* Save flags since we'll disable interrupts */
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pushf
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/* Cleanup IRQL */
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and ecx, 0xFF
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/* Validate IRQL */
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movzx ecx, cl
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#if DBG
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#if DBG
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cmp cl, PCR[KPCR_IRQL]
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ja InvalidIrql
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#endif
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#endif
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/* Save flags since we'll disable interrupts */
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pushf
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cli
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/* Disable interrupts and check if IRQL is below DISPATCH_LEVEL */
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cmp dword ptr PCR[KPCR_IRQL], DISPATCH_LEVEL
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cli
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jbe SkipMask
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/* Clear interrupt masks since there's a pending hardware interrupt */
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@ -462,7 +685,7 @@ SkipMask:
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/* Set the new IRQL and check if there's a pending software interrupt */
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mov PCR[KPCR_IRQL], ecx
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mov eax, PCR[KPCR_IRR]
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mov al, SoftIntByteTable[eax]
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mov al, SWInterruptLookUpTable[eax]
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cmp al, cl
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ja DoCall3
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@ -487,7 +710,7 @@ InvalidIrql:
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DoCall3:
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/* There is, call it */
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call SoftIntHandlerTable[eax*4]
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call SWInterruptHandlerTable[eax*4]
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/* Restore interrupts and return */
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popf
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|
@ -499,9 +722,9 @@ DoCall3:
|
|||
_@KfRaiseIrql@4:
|
||||
@KfRaiseIrql@4:
|
||||
|
||||
/* Get the IRQL */
|
||||
mov eax, PCR[KPCR_IRQL]
|
||||
/* Get the IRQL */
|
||||
movzx ecx, cl
|
||||
mov eax, PCR[KPCR_IRQL]
|
||||
|
||||
#if DBG
|
||||
/* Validate it */
|
||||
|
|
@ -521,7 +744,7 @@ _@KfRaiseIrql@4:
|
|||
cli
|
||||
|
||||
/* Set the new IRQL */
|
||||
mov PCR[KPCR_IRQL], cl
|
||||
mov PCR[KPCR_IRQL], ecx
|
||||
|
||||
/* Mask the interrupts in the PIC */
|
||||
mov eax, KiI8259MaskTable[ecx*4]
|
||||
|
|
@ -536,7 +759,6 @@ _@KfRaiseIrql@4:
|
|||
ret
|
||||
|
||||
SetIrql:
|
||||
|
||||
/* Set the IRQL and return */
|
||||
mov PCR[KPCR_IRQL], ecx
|
||||
ret
|
||||
|
|
@ -598,29 +820,17 @@ InvalidRaise:
|
|||
.func KeRaiseIrqlToSynchLevel@0
|
||||
_KeRaiseIrqlToSynchLevel@0:
|
||||
|
||||
/* Disable interrupts */
|
||||
pushf
|
||||
cli
|
||||
|
||||
/* Mask out interrupts */
|
||||
mov eax, KiI8259MaskTable[SYNCH_LEVEL*4]
|
||||
or eax, PCR[KPCR_IDR]
|
||||
out 0x21, al
|
||||
shr eax, 8
|
||||
out 0xA1, al
|
||||
|
||||
/* Return the old IRQL, enable interrupts and set to SYNCH */
|
||||
/* Get the current IRQL */
|
||||
mov eax, PCR[KPCR_IRQL]
|
||||
|
||||
/* Set SYNCH_LEVEL */
|
||||
mov dword ptr PCR[KPCR_IRQL], SYNCH_LEVEL
|
||||
popf
|
||||
|
||||
#if DBG
|
||||
/* Validate raise */
|
||||
/* Make sure we were not higher then dispatch */
|
||||
cmp eax, SYNCH_LEVEL
|
||||
ja InvalidSyRaise
|
||||
#endif
|
||||
|
||||
/* Return */
|
||||
ret
|
||||
|
||||
#if DBG
|
||||
|
|
@ -737,7 +947,7 @@ SoftwareInt:
|
|||
/* Check if there are pending software interrupts */
|
||||
mov PCR[KPCR_IRQL], ecx
|
||||
mov eax, PCR[KPCR_IRR]
|
||||
mov al, SoftIntByteTable[eax]
|
||||
mov al, SWInterruptLookUpTable[eax]
|
||||
cmp al, cl
|
||||
ja DoCall2
|
||||
ret 4
|
||||
|
|
@ -745,5 +955,5 @@ SoftwareInt:
|
|||
DoCall2:
|
||||
/* There are pending softwate interrupts, call their handlers */
|
||||
add esp, 8
|
||||
jmp SoftIntHandlerTable2[eax*4]
|
||||
jmp SWInterruptHandlerTable2[eax*4]
|
||||
.endfunc
|
||||
|
|
|
|||
|
|
@ -191,6 +191,40 @@ _KiUnexpectedInterrupt&Number:
|
|||
.endr
|
||||
.endm
|
||||
|
||||
//
|
||||
// @name GENERATE_HAL_INT_HANDLER
|
||||
//
|
||||
// This macro creates a HAL hardware interrupt handler.
|
||||
//
|
||||
// @param None.
|
||||
//
|
||||
// @remark None.
|
||||
//
|
||||
.macro GENERATE_HAL_INT_HANDLER Number
|
||||
.func HalpHardwareInterrupt&Number
|
||||
_HalpHardwareInterrupt&Number:
|
||||
int PRIMARY_VECTOR_BASE + Number
|
||||
ret
|
||||
.endfunc
|
||||
.endm
|
||||
|
||||
//
|
||||
// @name GENERATE_HAL_INT_HANDLERS
|
||||
//
|
||||
// This macro creates the unexpected interrupt handlers.
|
||||
//
|
||||
// @param None.
|
||||
//
|
||||
// @remark None.
|
||||
//
|
||||
.macro GENERATE_HAL_INT_HANDLERS
|
||||
.set i, 0
|
||||
.rept 16
|
||||
GENERATE_HAL_INT_HANDLER %i
|
||||
.set i, i + 1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
//
|
||||
// @name INVALID_V86_OPCODE
|
||||
//
|
||||
|
|
|
|||
Loading…
Reference in a new issue