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Add all pci bridge control function (PciBridgeIoBase, PciBridgeIoLimit, PciBridgeMemoryBase, PciBridgeMemoryLimit, PciBridgePrefetchMemoryBase, PciBridgePrefetchMemoryLimit, PciBridgeMemoryWorstCasealignment, PciBridgeIsPositiveDecode, PciBridgeIsSubtractiveDecode)
More support ICH0/1/2/3/4 hub Add all PCI2PCI bridge limit/current resource codes (PPBridge_*), now is BAR setup okay, and Device_* must be implement Support ISA+VGA legacy decode, 20+64-bit decode, ROM BAR, prefetch BAR svn path=/trunk/; revision=48298
This commit is contained in:
evb
parent
8458508701
commit
bf7de6528b
3 changed files with 735 additions and 10 deletions
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@ -1070,6 +1070,14 @@ PciExecuteCriticalSystemRoutine(
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IN ULONG_PTR IpiContext
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);
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BOOLEAN
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NTAPI
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PciCreateIoDescriptorFromBarLimit(
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PIO_RESOURCE_DESCRIPTOR ResourceDescriptor,
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IN PULONG BarArray,
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IN BOOLEAN Rom
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);
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BOOLEAN
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NTAPI
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PciIsSlotPresentInParentMethod(
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@ -16,36 +16,612 @@
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/* FUNCTIONS ******************************************************************/
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ULONG
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NTAPI
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PciBridgeIoBase(IN PPCI_COMMON_HEADER PciData)
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{
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BOOLEAN Is32Bit;
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ULONG Base, IoBase;
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ASSERT(PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE);
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/* Get the base */
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Base = PciData->u.type1.IOLimit;
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/* Low bit specifies 32-bit address, top bits specify the base */
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Is32Bit = (Base & 0xF) == 1;
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IoBase = (Base & 0xF0) << 8;
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/* Is it 32-bit? */
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if (Is32Bit)
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{
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/* Read the upper 16-bits from the other register */
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IoBase |= PciData->u.type1.IOBaseUpper16 << 16;
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ASSERT(PciData->u.type1.IOLimit & 0x1);
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}
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/* Return the base address */
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return IoBase;
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}
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ULONG
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NTAPI
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PciBridgeIoLimit(IN PPCI_COMMON_HEADER PciData)
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{
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BOOLEAN Is32Bit;
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ULONG Limit, IoLimit;
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ASSERT(PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE);
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/* Get the limit */
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Limit = PciData->u.type1.IOLimit;
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/* Low bit specifies 32-bit address, top bits specify the limit */
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Is32Bit = (Limit & 0xF) == 1;
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IoLimit = (Limit & 0xF0) << 8;
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/* Is it 32-bit? */
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if (Is32Bit)
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{
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/* Read the upper 16-bits from the other register */
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IoLimit |= PciData->u.type1.IOLimitUpper16 << 16;
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ASSERT(PciData->u.type1.IOBase & 0x1);
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}
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/* Return the I/O limit */
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return IoLimit | 0xFFF;
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}
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ULONG
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NTAPI
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PciBridgeMemoryBase(IN PPCI_COMMON_HEADER PciData)
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{
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ASSERT(PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE);
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/* Return the memory base */
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return (PciData->u.type1.MemoryBase << 16);
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}
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ULONG
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NTAPI
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PciBridgeMemoryLimit(IN PPCI_COMMON_HEADER PciData)
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{
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ASSERT(PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE);
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/* Return the memory limit */
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return (PciData->u.type1.MemoryLimit << 16) | 0xFFFFF;
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}
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PHYSICAL_ADDRESS
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NTAPI
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PciBridgePrefetchMemoryBase(IN PPCI_COMMON_HEADER PciData)
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{
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BOOLEAN Is64Bit;
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LARGE_INTEGER Base;
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USHORT PrefetchBase;
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ASSERT(PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE);
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/* Get the base */
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PrefetchBase = PciData->u.type1.PrefetchBase;
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/* Low bit specifies 64-bit address, top bits specify the base */
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Is64Bit = (PrefetchBase & 0xF) == 1;
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Base.LowPart = ((PrefetchBase & 0xFFF0) << 16);
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/* Is it 64-bit? */
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if (Is64Bit)
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{
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/* Read the upper 32-bits from the other register */
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Base.HighPart = PciData->u.type1.PrefetchBaseUpper32;
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}
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/* Return the base */
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return Base;
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}
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PHYSICAL_ADDRESS
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NTAPI
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PciBridgePrefetchMemoryLimit(IN PPCI_COMMON_HEADER PciData)
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{
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BOOLEAN Is64Bit;
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LARGE_INTEGER Limit;
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USHORT PrefetchLimit;
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ASSERT(PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE);
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/* Get the base */
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PrefetchLimit = PciData->u.type1.PrefetchLimit;
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/* Low bit specifies 64-bit address, top bits specify the limit */
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Is64Bit = (PrefetchLimit & 0xF) == 1;
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Limit.LowPart = (PrefetchLimit << 16) | 0xFFFFF;
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/* Is it 64-bit? */
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if (Is64Bit)
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{
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/* Read the upper 32-bits from the other register */
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Limit.HighPart = PciData->u.type1.PrefetchLimitUpper32;
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}
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/* Return the limit */
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return Limit;
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}
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ULONG
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NTAPI
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PciBridgeMemoryWorstCaseAlignment(IN ULONG Length)
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{
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ULONG Alignment;
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ASSERT(Length != 0);
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/* Start with highest alignment (2^31) */
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Alignment = 0x80000000;
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/* Keep dividing until we reach the correct power of two */
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while (!(Length & Alignment)) Alignment >>= 1;
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/* Return the alignment */
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return Alignment;
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}
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BOOLEAN
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NTAPI
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PciBridgeIsPositiveDecode(IN PPCI_PDO_EXTENSION PdoExtension)
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{
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/* Undocumented ACPI Method PDEC to get positive decode settings */
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return PciIsSlotPresentInParentMethod(PdoExtension, 'CEDP');
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}
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BOOLEAN
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NTAPI
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PciBridgeIsSubtractiveDecode(IN PPCI_CONFIGURATOR_CONTEXT Context)
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{
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PPCI_COMMON_HEADER Current, PciData;
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PPCI_PDO_EXTENSION PdoExtension;
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/* Get pointers from context */
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Current = Context->Current;
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PciData = Context->PciData;
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PdoExtension = Context->PdoExtension;
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/* Only valid for PCI-to-PCI bridges */
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ASSERT((Current->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
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(Current->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI));
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/* Check for hacks first, then check the ProgIf of the bridge */
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if (!(PdoExtension->HackFlags & PCI_HACK_SUBTRACTIVE_DECODE) &&
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(Current->ProgIf != 1) &&
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((PciData->u.type1.IOLimit & 0xF0) == 0xF0))
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{
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/* A subtractive decode bridge would have a ProgIf 1, and no I/O limit */
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DPRINT("Subtractive decode does not seem to be enabled\n");
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return FALSE;
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}
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/*
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* Check for Intel ICH PCI-to-PCI (i82801) bridges (used on the i810,
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* i820, i840, i845 Chipsets) that have subtractive decode broken.
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*/
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if (((PdoExtension->VendorId == 0x8086) &&
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((PdoExtension->DeviceId == 0x2418) ||
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(PdoExtension->DeviceId == 0x2428) ||
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(PdoExtension->DeviceId == 0x244E) ||
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(PdoExtension->DeviceId == 0x2448))) ||
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(PdoExtension->HackFlags & PCI_HACK_BROKEN_SUBTRACTIVE_DECODE))
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{
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/* Check if the ACPI BIOS says positive decode should be enabled */
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if (PciBridgeIsPositiveDecode(PdoExtension))
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{
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/* Obey ACPI */
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DPRINT1("Putting bridge in positive decode because of PDEC\n");
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return FALSE;
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}
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}
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/* If we found subtractive decode, we'll need a resource update later */
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DPRINT1("PCI : Subtractive decode on 0x%x\n", Current->u.type1.SecondaryBus);
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PdoExtension->UpdateHardware = TRUE;
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return TRUE;
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}
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VOID
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NTAPI
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PPBridge_SaveCurrentSettings(IN PPCI_CONFIGURATOR_CONTEXT Context)
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{
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UNIMPLEMENTED;
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while (TRUE);
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NTSTATUS Status;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
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PIO_RESOURCE_DESCRIPTOR IoDescriptor;
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PPCI_FUNCTION_RESOURCES Resources;
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PCI_COMMON_HEADER BiosData;
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PPCI_COMMON_HEADER Current;
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PPCI_COMMON_CONFIG SavedConfig;
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ULONG i, Bar, BarMask;
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PULONG BarArray;
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PHYSICAL_ADDRESS Limit, Base, Length;
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BOOLEAN HaveIoLimit, CheckAlignment;
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PPCI_PDO_EXTENSION PdoExtension;
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/* Get the pointers from the extension */
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PdoExtension = Context->PdoExtension;
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Resources = PdoExtension->Resources;
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Current = Context->Current;
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/* Check if decodes are disabled */
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if (!(Context->Command & (PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE)))
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{
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/* Well, we're going to need them from somewhere, use the registry data */
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Status = PciGetBiosConfig(PdoExtension, &BiosData);
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if (NT_SUCCESS(Status)) Current = &BiosData;
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}
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/* Scan all current and limit descriptors for each BAR needed */
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BarArray = Current->u.type1.BaseAddresses;
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for (i = 0; i < 6; i++)
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{
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/* Get the current resource descriptor, and the limit requirement */
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CmDescriptor = &Resources->Current[i];
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IoDescriptor = &Resources->Limit[i];
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/* Copy descriptor data, skipping null descriptors */
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CmDescriptor->Type = IoDescriptor->Type;
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if (CmDescriptor->Type == CmResourceTypeNull) continue;
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CmDescriptor->Flags = IoDescriptor->Flags;
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CmDescriptor->ShareDisposition = IoDescriptor->ShareDisposition;
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/* Initialize the high-parts to zero, since most stuff is 32-bit only */
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Base.QuadPart = Limit.QuadPart = Length.QuadPart = 0;
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/* Check if we're handling PCI BARs, or the ROM BAR */
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if ((i < PCI_TYPE1_ADDRESSES) || (i == 5))
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{
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/* Is this the ROM BAR? */
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if (i == 5)
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{
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/* Read the correct bar, with the appropriate mask */
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Bar = Current->u.type1.ROMBaseAddress;
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BarMask = PCI_ADDRESS_ROM_ADDRESS_MASK;
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/* Decode the base address, and write down the length */
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Base.LowPart = Bar & BarMask;
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DPRINT1("ROM BAR Base: %lx\n", Base.LowPart);
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CmDescriptor->u.Memory.Length = IoDescriptor->u.Memory.Length;
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}
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else
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{
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/* Otherwise, get the BAR from the array */
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Bar = BarArray[i];
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/* Is this an I/O BAR? */
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if (Bar & PCI_ADDRESS_IO_SPACE)
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{
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/* Set the correct mask */
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ASSERT(CmDescriptor->Type == CmResourceTypePort);
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BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
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}
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else
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{
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/* This is a memory BAR, set the correct base */
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ASSERT(CmDescriptor->Type == CmResourceTypeMemory);
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BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
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/* IS this a 64-bit BAR? */
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if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
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{
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/* Read the next 32-bits as well, ie, the next BAR */
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Base.HighPart = BarArray[i + 1];
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}
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}
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/* Decode the base address, and write down the length */
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Base.LowPart = Bar & BarMask;
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DPRINT1("BAR Base: %lx\n", Base.LowPart);
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CmDescriptor->u.Generic.Length = IoDescriptor->u.Generic.Length;
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}
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}
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else
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{
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/* Reset loop conditions */
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HaveIoLimit = FALSE;
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CheckAlignment = FALSE;
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/* Check which descriptor is being parsed */
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if (i == 2)
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{
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/* I/O Port Requirements */
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Base.LowPart = PciBridgeIoBase(Current);
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Limit.LowPart = PciBridgeIoLimit(Current);
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DPRINT1("Bridge I/O Base and Limit: %lx %lx\n",
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Base.LowPart, Limit.LowPart);
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/* Do we have any I/O Port data? */
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if (!(Base.LowPart) && (Current->u.type1.IOLimit))
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{
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/* There's a limit */
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HaveIoLimit = TRUE;
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}
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}
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else if (i == 3)
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{
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/* Memory requirements */
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Base.LowPart = PciBridgeMemoryBase(Current);
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Limit.LowPart = PciBridgeMemoryLimit(Current);
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/* These should always be there, so check their alignment */
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DPRINT1("Bridge MEM Base and Limit: %lx %lx\n",
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Base.LowPart, Limit.LowPart);
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CheckAlignment = TRUE;
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}
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else if (i == 4)
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{
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/* This should only be present for prefetch memory */
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ASSERT(CmDescriptor->Flags & CM_RESOURCE_MEMORY_PREFETCHABLE);
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Base = PciBridgePrefetchMemoryBase(Current);
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Limit = PciBridgePrefetchMemoryLimit(Current);
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/* If it's there, check the alignment */
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DPRINT1("Bridge Prefetch MEM Base and Limit: %I64x %I64x\n", Base, Limit);
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CheckAlignment = TRUE;
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}
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/* Check for invalid base address */
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if (Base.QuadPart >= Limit.QuadPart)
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{
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/* Assume the descriptor is bogus */
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CmDescriptor->Type = CmResourceTypeNull;
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IoDescriptor->Type = CmResourceTypeNull;
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continue;
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}
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/* Check if there's no memory, and no I/O port either */
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if (!(Base.LowPart) && !(HaveIoLimit))
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{
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/* This seems like a bogus requirement, ignore it */
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CmDescriptor->Type = CmResourceTypeNull;
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continue;
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}
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/* Set the length to be the limit - the base; should always be 32-bit */
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Length.QuadPart = Limit.LowPart - Base.LowPart + 1;
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ASSERT(Length.HighPart == 0);
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CmDescriptor->u.Generic.Length = Length.LowPart;
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/* Check if alignment should be set */
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if (CheckAlignment)
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{
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/* Compute the required alignment for this length */
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ASSERT(CmDescriptor->u.Memory.Length > 0);
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IoDescriptor->u.Memory.Alignment =
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PciBridgeMemoryWorstCaseAlignment(CmDescriptor->u.Memory.Length);
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}
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}
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/* Now set the base address */
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CmDescriptor->u.Generic.Start.LowPart = Base.LowPart;
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}
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/* Save PCI settings into the PDO extension for easy access later */
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PdoExtension->Dependent.type1.PrimaryBus = Current->u.type1.PrimaryBus;
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PdoExtension->Dependent.type1.SecondaryBus = Current->u.type1.SecondaryBus;
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PdoExtension->Dependent.type1.SubordinateBus = Current->u.type1.SubordinateBus;
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/* Check for subtractive decode bridges */
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if (PdoExtension->Dependent.type1.SubtractiveDecode)
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{
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/* Check if legacy VGA decodes are enabled */
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DPRINT1("Subtractive decode bridge\n");
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if (Current->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA)
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{
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/* Save this setting for later */
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DPRINT1("VGA Bridge\n");
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PdoExtension->Dependent.type1.VgaBitSet = TRUE;
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}
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/* Legacy ISA decoding is not compatible with subtractive decode */
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ASSERT(PdoExtension->Dependent.type1.IsaBitSet == FALSE);
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}
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else
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{
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/* Check if legacy VGA decodes are enabled */
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if (Current->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA)
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{
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/* Save this setting for later */
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DPRINT1("VGA Bridge\n");
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PdoExtension->Dependent.type1.VgaBitSet = TRUE;
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/* And on positive decode, we'll also need extra resources locked */
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PdoExtension->AdditionalResourceCount = 4;
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}
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/* Check if legacy ISA decoding is enabled */
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if (Current->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_ISA)
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{
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/* Save this setting for later */
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DPRINT1("ISA Bridge\n");
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PdoExtension->Dependent.type1.IsaBitSet = TRUE;
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}
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}
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/*
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* Check for Intel ICH PCI-to-PCI (i82801) bridges (used on the i810,
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* i820, i840, i845 Chipsets) that have subtractive decode broken.
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*/
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if (((PdoExtension->VendorId == 0x8086) &&
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((PdoExtension->DeviceId == 0x2418) ||
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(PdoExtension->DeviceId == 0x2428) ||
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(PdoExtension->DeviceId == 0x244E) ||
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(PdoExtension->DeviceId == 0x2448))) ||
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(PdoExtension->HackFlags & PCI_HACK_BROKEN_SUBTRACTIVE_DECODE))
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{
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/* Check if subtractive decode is actually enabled */
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if (PdoExtension->Dependent.type1.SubtractiveDecode)
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{
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/* We're going to need a copy of the configuration for later use */
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DPRINT1("apply config save hack to ICH subtractive decode\n");
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SavedConfig = ExAllocatePoolWithTag(0, PCI_COMMON_HDR_LENGTH, 'PciP');
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PdoExtension->ParentFdoExtension->PreservedConfig = SavedConfig;
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if (SavedConfig) RtlCopyMemory(SavedConfig, Current, PCI_COMMON_HDR_LENGTH);
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}
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}
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}
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VOID
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NTAPI
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PPBridge_SaveLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
|
||||
{
|
||||
UNIMPLEMENTED;
|
||||
while (TRUE);
|
||||
PIO_RESOURCE_DESCRIPTOR Limit;
|
||||
PULONG BarArray;
|
||||
PHYSICAL_ADDRESS MemoryLimit;
|
||||
ULONG i;
|
||||
PPCI_COMMON_HEADER Working;
|
||||
PPCI_PDO_EXTENSION PdoExtension;
|
||||
|
||||
/* Get the pointers from the context */
|
||||
Working = Context->PciData;
|
||||
PdoExtension = Context->PdoExtension;
|
||||
|
||||
/* Scan the BARs into the limit descriptors */
|
||||
BarArray = Working->u.type1.BaseAddresses;
|
||||
Limit = PdoExtension->Resources->Limit;
|
||||
|
||||
/* First of all, loop all the BARs */
|
||||
for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
|
||||
{
|
||||
/* Create a descriptor for their limits */
|
||||
if (PciCreateIoDescriptorFromBarLimit(&Limit[i], &BarArray[i], FALSE))
|
||||
{
|
||||
/* This was a 64-bit descriptor, make sure there's space */
|
||||
ASSERT((i + 1) < PCI_TYPE1_ADDRESSES);
|
||||
|
||||
/* Skip the next descriptor since this one is double sized */
|
||||
i++;
|
||||
(&Limit[i])->Type == CmResourceTypeNull;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if this is a subtractive decode bridge */
|
||||
if (PciBridgeIsSubtractiveDecode(Context))
|
||||
{
|
||||
/* This bridge is subtractive */
|
||||
PdoExtension->Dependent.type1.SubtractiveDecode = TRUE;
|
||||
|
||||
/* Subtractive bridges cannot use legacy ISA or VGA functionality */
|
||||
PdoExtension->Dependent.type1.IsaBitSet = FALSE;
|
||||
PdoExtension->Dependent.type1.VgaBitSet = FALSE;
|
||||
}
|
||||
|
||||
/* For normal decode bridges, we'll need to find the bridge limits too */
|
||||
if (!PdoExtension->Dependent.type1.SubtractiveDecode)
|
||||
{
|
||||
/* Loop the descriptors that are left, to store the bridge limits */
|
||||
for (i = PCI_TYPE1_ADDRESSES; i < 5; i++)
|
||||
{
|
||||
/* No 64-bit memory addresses, and set the address to 0 to begin */
|
||||
MemoryLimit.HighPart = 0;
|
||||
(&Limit[i])->u.Port.MinimumAddress.QuadPart = 0;
|
||||
|
||||
/* Are we getting the I/O limit? */
|
||||
if (i == 2)
|
||||
{
|
||||
/* There should be one, get it */
|
||||
ASSERT(Working->u.type1.IOLimit != 0);
|
||||
ASSERT((Working->u.type1.IOLimit & 0x0E) == 0);
|
||||
MemoryLimit.LowPart = PciBridgeIoLimit(Working);
|
||||
|
||||
/* Build a descriptor for this limit */
|
||||
(&Limit[i])->Type = CmResourceTypePort;
|
||||
(&Limit[i])->Flags = CM_RESOURCE_PORT_WINDOW_DECODE |
|
||||
CM_RESOURCE_PORT_POSITIVE_DECODE;
|
||||
(&Limit[i])->u.Port.Alignment = 0x1000;
|
||||
(&Limit[i])->u.Port.MinimumAddress.QuadPart = 0;
|
||||
(&Limit[i])->u.Port.MaximumAddress = MemoryLimit;
|
||||
(&Limit[i])->u.Port.Length = 0;
|
||||
}
|
||||
else if (i == 3)
|
||||
{
|
||||
/* There should be a valid memory limit, get it */
|
||||
ASSERT((Working->u.type1.MemoryLimit & 0xF) == 0);
|
||||
MemoryLimit.LowPart = PciBridgeMemoryLimit(Working);
|
||||
|
||||
/* Build the descriptor for it */
|
||||
(&Limit[i])->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
|
||||
(&Limit[i])->Type = CmResourceTypeMemory;
|
||||
(&Limit[i])->u.Memory.Alignment = 0x100000;
|
||||
(&Limit[i])->u.Memory.MinimumAddress.QuadPart = 0;
|
||||
(&Limit[i])->u.Memory.MaximumAddress = MemoryLimit;
|
||||
(&Limit[i])->u.Memory.Length = 0;
|
||||
}
|
||||
else if (Working->u.type1.PrefetchLimit)
|
||||
{
|
||||
/* Get the prefetch memory limit, if there is one */
|
||||
MemoryLimit = PciBridgePrefetchMemoryLimit(Working);
|
||||
|
||||
/* Write out the descriptor for it */
|
||||
(&Limit[i])->Flags = CM_RESOURCE_MEMORY_PREFETCHABLE;
|
||||
(&Limit[i])->Type = CmResourceTypeMemory;
|
||||
(&Limit[i])->u.Memory.Alignment = 0x100000;
|
||||
(&Limit[i])->u.Memory.MinimumAddress.QuadPart = 0;
|
||||
(&Limit[i])->u.Memory.MaximumAddress = MemoryLimit;
|
||||
(&Limit[i])->u.Memory.Length = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Blank descriptor */
|
||||
(&Limit[i])->Type = CmResourceTypeNull;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Does the ROM have its own BAR? */
|
||||
if (Working->u.type1.ROMBaseAddress & PCI_ROMADDRESS_ENABLED)
|
||||
{
|
||||
/* Build a limit for it as well */
|
||||
PciCreateIoDescriptorFromBarLimit(&Limit[i],
|
||||
&Working->u.type1.ROMBaseAddress,
|
||||
TRUE);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
PPBridge_MassageHeaderForLimitsDetermination(IN PPCI_CONFIGURATOR_CONTEXT Context)
|
||||
{
|
||||
UNIMPLEMENTED;
|
||||
while (TRUE);
|
||||
PPCI_COMMON_HEADER PciData, Current;
|
||||
|
||||
/* Get pointers from context */
|
||||
PciData = Context->PciData;
|
||||
Current = Context->Current;
|
||||
|
||||
/*
|
||||
* Write FFh everywhere so that the PCI bridge ignores what it can't handle.
|
||||
* Based on the bits that were ignored (still 0), this is how we can tell
|
||||
* what the limit is.
|
||||
*/
|
||||
RtlFillMemory(PciData->u.type1.BaseAddresses,
|
||||
FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.CapabilitiesPtr) -
|
||||
FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.BaseAddresses),
|
||||
0xFF);
|
||||
|
||||
/* Copy the saved settings from the current context into the PCI header */
|
||||
PciData->u.type1.PrimaryBus = Current->u.type1.PrimaryBus;
|
||||
PciData->u.type1.SecondaryBus = Current->u.type1.SecondaryBus;
|
||||
PciData->u.type1.SubordinateBus = Current->u.type1.SubordinateBus;
|
||||
PciData->u.type1.SecondaryLatency = Current->u.type1.SecondaryLatency;
|
||||
|
||||
/* No I/O limit or base. The bottom base bit specifies that FIXME */
|
||||
PciData->u.type1.IOBaseUpper16 = 0xFFFE;
|
||||
PciData->u.type1.IOLimitUpper16 = 0xFFFF;
|
||||
|
||||
/* Save secondary status before it gets cleared */
|
||||
Context->SecondaryStatus = Current->u.type1.SecondaryStatus;
|
||||
|
||||
/* Clear secondary status */
|
||||
Current->u.type1.SecondaryStatus = 0;
|
||||
PciData->u.type1.SecondaryStatus = 0;
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
PPBridge_RestoreCurrent(IN PPCI_CONFIGURATOR_CONTEXT Context)
|
||||
{
|
||||
UNIMPLEMENTED;
|
||||
while (TRUE);
|
||||
/* Copy back the secondary status register */
|
||||
Context->Current->u.type1.SecondaryStatus = Context->SecondaryStatus;
|
||||
}
|
||||
|
||||
VOID
|
||||
|
|
@ -54,8 +630,40 @@ PPBridge_GetAdditionalResourceDescriptors(IN PPCI_CONFIGURATOR_CONTEXT Context,
|
|||
IN PPCI_COMMON_HEADER PciData,
|
||||
IN PIO_RESOURCE_DESCRIPTOR IoDescriptor)
|
||||
{
|
||||
UNIMPLEMENTED;
|
||||
while (TRUE);
|
||||
/* Does this bridge have VGA decodes on it? */
|
||||
if (PciData->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA)
|
||||
{
|
||||
/* Build a private descriptor with 3 entries */
|
||||
IoDescriptor->Type = CmResourceTypeDevicePrivate;
|
||||
IoDescriptor->u.DevicePrivate.Data[0] = 3;
|
||||
IoDescriptor->u.DevicePrivate.Data[1] = 3;
|
||||
|
||||
/* First, the VGA range at 0xA0000 */
|
||||
IoDescriptor[1].Type = CmResourceTypeMemory;
|
||||
IoDescriptor[1].Flags = CM_RESOURCE_MEMORY_READ_WRITE;
|
||||
IoDescriptor[1].u.Port.Length = 0x20000;
|
||||
IoDescriptor[1].u.Port.Alignment = 1;
|
||||
IoDescriptor[1].u.Port.MinimumAddress.QuadPart = 0xA0000;
|
||||
IoDescriptor[1].u.Port.MaximumAddress.QuadPart = 0xBFFFF;
|
||||
|
||||
/* Then, the VGA registers at 0x3B0 */
|
||||
IoDescriptor[2].Type = CmResourceTypePort;
|
||||
IoDescriptor[2].Flags = CM_RESOURCE_PORT_POSITIVE_DECODE |
|
||||
CM_RESOURCE_PORT_10_BIT_DECODE;
|
||||
IoDescriptor[2].u.Port.Length = 12;
|
||||
IoDescriptor[2].u.Port.Alignment = 1;
|
||||
IoDescriptor[2].u.Port.MinimumAddress.QuadPart = 0x3B0;
|
||||
IoDescriptor[2].u.Port.MaximumAddress.QuadPart = 0x3BB;
|
||||
|
||||
/* And finally the VGA registers at 0x3C0 */
|
||||
IoDescriptor[3].Type = CmResourceTypePort;
|
||||
IoDescriptor[3].Flags = CM_RESOURCE_PORT_POSITIVE_DECODE |
|
||||
CM_RESOURCE_PORT_10_BIT_DECODE;
|
||||
IoDescriptor[3].u.Port.Length = 32;
|
||||
IoDescriptor[3].u.Port.Alignment = 1;
|
||||
IoDescriptor[3].u.Port.MinimumAddress.QuadPart = 0x3C0;
|
||||
IoDescriptor[3].u.Port.MaximumAddress.QuadPart = 0x3DF;
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
|
|
|
|||
|
|
@ -1130,6 +1130,115 @@ PciIsSlotPresentInParentMethod(IN PPCI_PDO_EXTENSION PdoExtension,
|
|||
return FoundSlot;
|
||||
}
|
||||
|
||||
ULONG
|
||||
NTAPI
|
||||
PciGetLengthFromBar(IN ULONG Bar)
|
||||
{
|
||||
ULONG Length;
|
||||
|
||||
/* I/O addresses vs. memory addresses start differently due to alignment */
|
||||
Length = 1 << ((Bar & PCI_ADDRESS_IO_SPACE) ? 2 : 4);
|
||||
|
||||
/* Keep going until a set bit */
|
||||
while (!(Length & Bar) && (Length)) Length <<= 1;
|
||||
|
||||
/* Return the length (might be 0 on 64-bit because it's the low-word) */
|
||||
if ((Bar & PCI_ADDRESS_MEMORY_TYPE_MASK) != PCI_TYPE_64BIT) ASSERT(Length);
|
||||
return Length;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
NTAPI
|
||||
PciCreateIoDescriptorFromBarLimit(PIO_RESOURCE_DESCRIPTOR ResourceDescriptor,
|
||||
IN PULONG BarArray,
|
||||
IN BOOLEAN Rom)
|
||||
{
|
||||
ULONG CurrentBar, BarLength, BarMask;
|
||||
BOOLEAN Is64BitBar = FALSE;
|
||||
|
||||
/* Check if the BAR is nor I/O nor memory */
|
||||
CurrentBar = BarArray[0];
|
||||
if (!(CurrentBar & ~PCI_ADDRESS_IO_SPACE))
|
||||
{
|
||||
/* Fail this descriptor */
|
||||
ResourceDescriptor->Type = CmResourceTypeNull;
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Set default flag and clear high words */
|
||||
ResourceDescriptor->Flags = 0;
|
||||
ResourceDescriptor->u.Generic.MaximumAddress.HighPart = 0;
|
||||
ResourceDescriptor->u.Generic.MinimumAddress.LowPart = 0;
|
||||
ResourceDescriptor->u.Generic.MinimumAddress.HighPart = 0;
|
||||
|
||||
/* Check for ROM Address */
|
||||
if (Rom)
|
||||
{
|
||||
/* Clean up the BAR to get just the address */
|
||||
CurrentBar &= PCI_ADDRESS_ROM_ADDRESS_MASK;
|
||||
if (!CurrentBar)
|
||||
{
|
||||
/* Invalid ar, fail this descriptor */
|
||||
ResourceDescriptor->Type = CmResourceTypeNull;
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* ROM Addresses are always read only */
|
||||
ResourceDescriptor->Flags = CM_RESOURCE_MEMORY_READ_ONLY;
|
||||
}
|
||||
|
||||
/* Compute the length, assume it's the alignment for now */
|
||||
BarLength = PciGetLengthFromBar(CurrentBar);
|
||||
ResourceDescriptor->u.Generic.Length = BarLength;
|
||||
ResourceDescriptor->u.Generic.Alignment = BarLength;
|
||||
|
||||
/* Check what kind of BAR this is */
|
||||
if (CurrentBar & PCI_ADDRESS_IO_SPACE)
|
||||
{
|
||||
/* Use correct mask to decode the address */
|
||||
BarMask = PCI_ADDRESS_IO_ADDRESS_MASK;
|
||||
|
||||
/* Set this as an I/O Port descriptor */
|
||||
ResourceDescriptor->Type = CmResourceTypePort;
|
||||
ResourceDescriptor->Flags = CM_RESOURCE_PORT_IO;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use correct mask to decode the address */
|
||||
BarMask = PCI_ADDRESS_MEMORY_ADDRESS_MASK;
|
||||
|
||||
/* Set this as a memory descriptor */
|
||||
ResourceDescriptor->Type = CmResourceTypeMemory;
|
||||
|
||||
/* Check if it's 64-bit or 20-bit decode */
|
||||
if ((CurrentBar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
|
||||
{
|
||||
/* The next BAR has the high word, read it */
|
||||
ResourceDescriptor->u.Port.MaximumAddress.HighPart = BarArray[1];
|
||||
Is64BitBar = TRUE;
|
||||
}
|
||||
else if ((CurrentBar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_20BIT)
|
||||
{
|
||||
/* Use the correct mask to decode the address */
|
||||
BarMask = ~0xFFF0000F;
|
||||
}
|
||||
|
||||
/* Check if the BAR is listed as prefetchable memory */
|
||||
if (CurrentBar & PCI_ADDRESS_MEMORY_PREFETCHABLE)
|
||||
{
|
||||
/* Mark the descriptor in the same way */
|
||||
ResourceDescriptor->Flags |= CM_RESOURCE_MEMORY_PREFETCHABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Now write down the maximum address based on the base + length */
|
||||
ResourceDescriptor->u.Port.MaximumAddress.QuadPart = (CurrentBar & BarMask) +
|
||||
BarLength - 1;
|
||||
|
||||
/* Return if this is a 64-bit BAR, so the loop code knows to skip the next one */
|
||||
return Is64BitBar;
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
PciDecodeEnable(IN PPCI_PDO_EXTENSION PdoExtension,
|
||||
|
|
|
|||
Loading…
Reference in a new issue