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[HALPC98] Add Hardware Abstraction Layer for NEC PC-98 series (#3002)
This commit is contained in:
Dmitry Borisov
GitHub
parent
0c222cfe96
commit
b36018ff26
37 changed files with 1880 additions and 372 deletions
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@ -7,13 +7,15 @@
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#pragma once
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#define CPU_IO_o_RESET 0x0F
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#define CPU_IO_o_RESET 0xF0
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#define CPU_IO_o_A20_UNMASK 0xF2
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#define CPU_IO_o_A20_CONTROL 0xF6
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#define CPU_A20_ENABLE 0x02
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#define CPU_A20_DISABLE 0x03
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#define CPU_IO_o_FPU_BUSY_LATCH 0xF8
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/*
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* ARTIC (A Relative Time Indication Counter) - 24-bit binary up counter
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*/
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231
sdk/include/reactos/drivers/pc98/pic.h
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231
sdk/include/reactos/drivers/pc98/pic.h
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@ -0,0 +1,231 @@
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/*
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* PROJECT: NEC PC-98 series onboard hardware
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: Intel 8259A PIC header file
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* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
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*/
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#pragma once
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#define PIC1_CONTROL_PORT 0x00
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#define PIC1_DATA_PORT 0x02
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#define PIC2_CONTROL_PORT 0x08
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#define PIC2_DATA_PORT 0x0A
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#define PIC_TIMER_IRQ 0
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#define PIC_CASCADE_IRQ 7
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#define PIC_RTC_IRQ 15
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/*
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* Definitions for ICW/OCW Bits
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*/
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typedef enum _I8259_ICW1_OPERATING_MODE
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{
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Cascade,
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Single
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} I8259_ICW1_OPERATING_MODE;
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typedef enum _I8259_ICW1_INTERRUPT_MODE
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{
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EdgeTriggered,
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LevelTriggered
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} I8259_ICW1_INTERRUPT_MODE;
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typedef enum _I8259_ICW1_INTERVAL
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{
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Interval8,
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Interval4
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} I8259_ICW1_INTERVAL;
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typedef enum _I8259_ICW4_SYSTEM_MODE
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{
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Mcs8085Mode,
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New8086Mode
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} I8259_ICW4_SYSTEM_MODE;
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typedef enum _I8259_ICW4_EOI_MODE
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{
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NormalEoi,
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AutomaticEoi
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} I8259_ICW4_EOI_MODE;
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typedef enum _I8259_ICW4_BUFFERED_MODE
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{
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NonBuffered,
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NonBuffered2,
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BufferedSlave,
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BufferedMaster
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} I8259_ICW4_BUFFERED_MODE;
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typedef enum _I8259_READ_REQUEST
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{
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InvalidRequest,
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InvalidRequest2,
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ReadIdr,
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ReadIsr
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} I8259_READ_REQUEST;
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typedef enum _I8259_EOI_MODE
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{
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RotateAutoEoiClear,
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NonSpecificEoi,
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InvalidEoiMode,
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SpecificEoi,
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RotateAutoEoiSet,
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RotateNonSpecific,
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SetPriority,
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RotateSpecific
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} I8259_EOI_MODE;
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/*
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* Definitions for ICW Registers
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*/
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typedef union _I8259_ICW1
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{
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struct
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{
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UCHAR NeedIcw4:1;
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UCHAR OperatingMode:1;
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UCHAR Interval:1;
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UCHAR InterruptMode:1;
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UCHAR Init:1;
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UCHAR InterruptVectorAddress:3;
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};
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UCHAR Bits;
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} I8259_ICW1, *PI8259_ICW1;
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typedef union _I8259_ICW2
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{
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struct
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{
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UCHAR Sbz:3;
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UCHAR InterruptVector:5;
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};
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UCHAR Bits;
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} I8259_ICW2, *PI8259_ICW2;
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typedef union _I8259_ICW3
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{
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union
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{
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struct
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{
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UCHAR SlaveIrq0:1;
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UCHAR SlaveIrq1:1;
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UCHAR SlaveIrq2:1;
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UCHAR SlaveIrq3:1;
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UCHAR SlaveIrq4:1;
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UCHAR SlaveIrq5:1;
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UCHAR SlaveIrq6:1;
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UCHAR SlaveIrq7:1;
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};
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struct
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{
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UCHAR SlaveId:3;
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UCHAR Reserved:5;
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};
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};
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UCHAR Bits;
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} I8259_ICW3, *PI8259_ICW3;
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typedef union _I8259_ICW4
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{
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struct
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{
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UCHAR SystemMode:1;
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UCHAR EoiMode:1;
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UCHAR BufferedMode:2;
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UCHAR SpecialFullyNestedMode:1;
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UCHAR Reserved:3;
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};
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UCHAR Bits;
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} I8259_ICW4, *PI8259_ICW4;
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typedef union _I8259_OCW2
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{
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struct
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{
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UCHAR IrqNumber:3;
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UCHAR Sbz:2;
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UCHAR EoiMode:3;
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};
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UCHAR Bits;
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} I8259_OCW2, *PI8259_OCW2;
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typedef union _I8259_OCW3
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{
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struct
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{
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UCHAR ReadRequest:2;
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UCHAR PollCommand:1;
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UCHAR Sbo:1;
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UCHAR Sbz:1;
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UCHAR SpecialMaskMode:2;
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UCHAR Reserved:1;
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};
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UCHAR Bits;
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} I8259_OCW3, *PI8259_OCW3;
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typedef union _I8259_ISR
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{
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struct
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{
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UCHAR Irq0:1;
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UCHAR Irq1:1;
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UCHAR Irq2:1;
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UCHAR Irq3:1;
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UCHAR Irq4:1;
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UCHAR Irq5:1;
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UCHAR Irq6:1;
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UCHAR Irq7:1;
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};
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UCHAR Bits;
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} I8259_ISR, *PI8259_ISR;
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typedef I8259_ISR I8259_IDR, *PI8259_IDR;
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/*
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* NESA Edge/Level Triggered Register
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*/
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#define EISA_ELCR_MASTER 0x98D2
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#define EISA_ELCR_SLAVE 0x98D4
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typedef union _EISA_ELCR
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{
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struct
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{
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struct
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{
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UCHAR Irq0Level:1;
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UCHAR Irq1Level:1;
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UCHAR Irq2Level:1;
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UCHAR Irq3Level:1;
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UCHAR Irq4Level:1;
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UCHAR Irq5Level:1;
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UCHAR Irq6Level:1;
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UCHAR Irq7Level:1;
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} Master;
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struct
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{
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UCHAR Irq8Level:1;
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UCHAR Irq9Level:1;
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UCHAR Irq10Level:1;
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UCHAR Irq11Level:1;
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UCHAR Irq12Level:1;
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UCHAR Irq13Level:1;
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UCHAR Irq14Level:1;
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UCHAR Irq15Level:1;
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} Slave;
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};
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USHORT Bits;
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} EISA_ELCR, *PEISA_ELCR;
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typedef union _PIC_MASK
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{
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struct
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{
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UCHAR Master;
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UCHAR Slave;
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};
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USHORT Both;
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} PIC_MASK, *PPIC_MASK;
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44
sdk/include/reactos/drivers/pc98/rtc.h
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44
sdk/include/reactos/drivers/pc98/rtc.h
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@ -0,0 +1,44 @@
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/*
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* PROJECT: NEC PC-98 series onboard hardware
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: NEC uPD1990A/uPD4990A RTC header file
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* COPYRIGHT: Copyright 2020 Dmitry Borisov (di.sean@protonmail.com)
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*/
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#pragma once
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#define RTC_IO_o_DATA 0x20
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/* Input terminals */
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#define RTC_DATA_INPUT 0x20
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#define RTC_CLOCK 0x10
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#define RTC_STROBE 0x08
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/* Commands, shift register 40 bit */
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#define RTC_CMD_REGISTER_HOLD 0x00
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#define RTC_CMD_REGISTER_SHIFT 0x01
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#define RTC_CMD_TIME_SET_COUNTER_HOLD 0x02
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#define RTC_CMD_TIME_READ 0x03
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#define RTC_CMD_TIMING_PULSE_64_HZ 0x04
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#define RTC_CMD_TIMING_PULSE_256_HZ 0x05
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#define RTC_CMD_TIMING_PULSE_2048_HZ 0x06
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#define RTC_CMD_SERIAL_TRANSFER_MODE 0x07
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/* Serial data commands, shift register 52 bit (uPD4990A only) */
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#define RTC_CMD_TIMING_PULSE_4096_HZ 0x07
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#define RTC_CMD_TIMING_PULSE_1_S_INT 0x08
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#define RTC_CMD_TIMING_PULSE_10_S_INT 0x09
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#define RTC_CMD_TIMING_PULSE_30_S_INT 0x0A
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#define RTC_CMD_TIMING_PULSE_60_S_INT 0x0B
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#define RTC_CMD_INTERRUPT_RESET 0x0C
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#define RTC_CMD_INTERRUPT_START 0x0D
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#define RTC_CMD_INTERRUPT_STOP 0x0E
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#define RTC_CMD_TEST_MODE 0x0F
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#define RTC_IO_o_MODE 0x22
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#define RTC_IO_o_INT_CLOCK_DIVISOR 0x128
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#define RTC_INT_CLOCK_DIVISOR_64 0x00
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#define RTC_INT_CLOCK_DIVISOR_32 0x01
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#define RTC_INT_CLOCK_DIVISOR_0 0x02
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#define RTC_INT_CLOCK_DIVISOR_16 0x03
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#define RTC_IO_i_MODE 0x22
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#define RTC_IO_i_INTERRUPT_RESET 0x128
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@ -8,7 +8,12 @@
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#pragma once
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#define PPI_IO_o_PORT_C 0x35
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#define PPI_IO_o_CONTROL 0x37
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#define PPI_TIMER_1_GATE_TO_SPEAKER 0x06
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#define PPI_TIMER_1_UNGATE_TO_SPEAKER 0x07
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#define PPI_SHUTDOWN_1_ENABLE 0x0B
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#define PPI_SHUTDOWN_0_ENABLE 0x0F
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#define PPI_IO_i_PORT_A 0x31
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#define PPI_IO_i_PORT_B 0x33
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@ -64,19 +69,3 @@ typedef union _SYSTEM_CONTROL_PORT_C_REGISTER
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};
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UCHAR Bits;
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} SYSTEM_CONTROL_PORT_C_REGISTER, *PSYSTEM_CONTROL_PORT_C_REGISTER;
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typedef union _SYSTEM_CONTROL_PORT_REGISTER
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{
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struct
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{
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UCHAR InterruptEnableRxReady:1;
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UCHAR InterruptEnableTxEmpty:1;
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UCHAR InterruptEnableTxReady:1;
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UCHAR Timer1GateToSpeaker:1;
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UCHAR Mcke:1;
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UCHAR Shut1:1;
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UCHAR PrinterStrobeSignal:1;
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UCHAR Shut0:1;
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};
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UCHAR Bits;
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} SYSTEM_CONTROL_PORT_REGISTER, *PSYSTEM_CONTROL_PORT_REGISTER;
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