mirror of
https://github.com/reactos/reactos.git
synced 2025-07-31 18:22:35 +00:00
Fix IRP_MN_QUERY_RESOURCES and implement IRP_MN_QUERY_RESOURCE_REQUIREMENTS.
svn path=/trunk/; revision=10588
This commit is contained in:
Eric Kohl
parent
543091ce46
commit
b299113f7b
1 changed files with 327 additions and 28 deletions
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@ -1,4 +1,4 @@
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/* $Id: pdo.c,v 1.6 2004/08/16 09:13:00 ekohl Exp $
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/* $Id: pdo.c,v 1.7 2004/08/18 08:25:58 ekohl Exp $
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*
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* PROJECT: ReactOS PCI bus driver
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* FILE: pdo.c
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@ -262,47 +262,35 @@ PdoGetRangeLength(PPDO_DEVICE_EXTENSION DeviceExtension,
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#if 0
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DbgPrint("BaseAddress 0x%08lx Length 0x%08lx",
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BaseValue, XLength);
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#endif
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if (NewValue & 0x00000001)
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{
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#if 0
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DbgPrint(" IO range");
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#endif
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}
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else
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{
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#if 0
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DbgPrint(" Memory range");
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#endif
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if ((NewValue & 0x00000006) == 0)
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{
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#if 0
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DbgPrint(" in 32-Bit address space");
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#endif
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}
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else if ((NewValue & 0x00000006) == 2)
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{
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#if 0
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DbgPrint("below 1BM ");
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#endif
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DbgPrint(" below 1BM ");
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}
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else if ((NewValue & 0x00000006) == 4)
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{
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#if 0
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DbgPrint(" in 64-Bit address space");
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#endif
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}
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if (NewValue & 0x00000008)
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{
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#if 0
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DbgPrint(" prefetchable");
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#endif
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}
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}
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DbgPrint("\n");
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#endif
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*Length = XLength;
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*Flags = (NewValue & 0x00000001) ? (NewValue & 0x3) : (NewValue & 0xF);
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@ -317,9 +305,271 @@ PdoQueryResourceRequirements(
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IN PIRP Irp,
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PIO_STACK_LOCATION IrpSp)
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{
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PPDO_DEVICE_EXTENSION DeviceExtension;
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PCI_COMMON_CONFIG PciConfig;
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PIO_RESOURCE_REQUIREMENTS_LIST ResourceList;
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PIO_RESOURCE_DESCRIPTOR Descriptor;
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ULONG Size;
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ULONG ResCount = 0;
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ULONG ListSize;
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ULONG i;
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ULONG Base;
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ULONG Length;
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ULONG Flags;
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DPRINT("PdoQueryResourceRequirements() called\n");
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return STATUS_NOT_IMPLEMENTED;
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DeviceExtension = (PPDO_DEVICE_EXTENSION)DeviceObject->DeviceExtension;
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/* Get PCI configuration space */
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Size= HalGetBusData(PCIConfiguration,
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DeviceExtension->BusNumber,
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DeviceExtension->SlotNumber.u.AsULONG,
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&PciConfig,
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sizeof(PCI_COMMON_CONFIG));
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DPRINT("Size %lu\n", Size);
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if (Size < sizeof(PCI_COMMON_CONFIG))
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{
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Irp->IoStatus.Information = 0;
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return STATUS_UNSUCCESSFUL;
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}
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DPRINT("Command register: 0x%04hx\n", PciConfig.Command);
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/* Count required resource descriptors */
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ResCount = 0;
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if ((PciConfig.HeaderType & 0x7F) == 0)
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{
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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if (!PdoGetRangeLength(DeviceExtension,
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0x10 + i * 4,
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&Base,
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&Length,
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&Flags))
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break;
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ResCount += 2;
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}
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/* FIXME: Check ROM address */
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if (PciConfig.u.type0.InterruptPin != 0)
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ResCount++;
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}
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else if ((PciConfig.HeaderType & 0x7F) == 1)
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{
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for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
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{
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if (!PdoGetRangeLength(DeviceExtension,
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0x10 + i * 4,
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&Base,
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&Length,
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&Flags))
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break;
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ResCount += 2;
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}
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}
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else
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{
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DPRINT1("Unsupported header type %u\n", PciConfig.HeaderType);
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}
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if (ResCount == 0)
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{
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Irp->IoStatus.Information = 0;
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return STATUS_SUCCESS;
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}
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/* Calculate the resource list size */
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ListSize = sizeof(IO_RESOURCE_REQUIREMENTS_LIST);
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if (ResCount > 1)
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{
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ListSize += ((ResCount - 1) * sizeof(IO_RESOURCE_DESCRIPTOR));
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}
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DPRINT1("ListSize %lu (0x%lx)\n", ListSize, ListSize);
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/* Allocate the resource requirements list */
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ResourceList = ExAllocatePool(PagedPool,
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ListSize);
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if (ResourceList == NULL)
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{
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Irp->IoStatus.Information = 0;
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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ResourceList->ListSize = ListSize;
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ResourceList->InterfaceType = PCIBus;
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ResourceList->AlternativeLists = 1;
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ResourceList->List[0].Version = 1;
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ResourceList->List[0].Revision = 1;
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ResourceList->List[0].Count = ResCount;
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Descriptor = &ResourceList->List[0].Descriptors[0];
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if ((PciConfig.HeaderType & 0x7F) == 0)
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{
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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if (!PdoGetRangeLength(DeviceExtension,
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0x10 + i * 4,
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&Base,
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&Length,
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&Flags))
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{
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DPRINT1("PdoGetRangeLength() failed\n");
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break;
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}
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if (Length == 0)
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{
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DPRINT("Unused address register\n");
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break;
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}
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/* Set preferred descriptor */
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Descriptor->Option = IO_RESOURCE_PREFERRED;
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if (Flags & PCI_ADDRESS_IO_SPACE)
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{
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO;
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Descriptor->u.Port.Length = Length;
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Descriptor->u.Port.Alignment = 1;
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Descriptor->u.Port.MinimumAddress.QuadPart = (ULONGLONG)Base;
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Descriptor->u.Port.MaximumAddress.QuadPart = (ULONGLONG)(Base + Length - 1);
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}
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else
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{
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Descriptor->Type = CmResourceTypeMemory;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
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Descriptor->u.Memory.Length = Length;
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Descriptor->u.Memory.Alignment = 1;
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Descriptor->u.Memory.MinimumAddress.QuadPart = (ULONGLONG)Base;
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Descriptor->u.Memory.MaximumAddress.QuadPart = (ULONGLONG)(Base + Length - 1);
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}
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Descriptor++;
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/* Set alternative descriptor */
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Descriptor->Option = IO_RESOURCE_ALTERNATIVE;
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if (Flags & PCI_ADDRESS_IO_SPACE)
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{
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO;
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Descriptor->u.Port.Length = Length;
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Descriptor->u.Port.Alignment = Length;
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Descriptor->u.Port.MinimumAddress.QuadPart = (ULONGLONG)0;
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Descriptor->u.Port.MaximumAddress.QuadPart = (ULONGLONG)(ULONG)-1;
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}
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else
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{
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Descriptor->Type = CmResourceTypeMemory;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
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Descriptor->u.Memory.Length = Length;
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Descriptor->u.Memory.Alignment = Length;
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Descriptor->u.Port.MinimumAddress.QuadPart = (ULONGLONG)0;
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Descriptor->u.Port.MaximumAddress.QuadPart = (ULONGLONG)(ULONG)-1;
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}
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Descriptor++;
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}
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/* FIXME: Check ROM address */
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if (PciConfig.u.type0.InterruptPin != 0)
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{
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Descriptor->Type = CmResourceTypeInterrupt;
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Descriptor->ShareDisposition = CmResourceShareShared;
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Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
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Descriptor->u.Interrupt.MinimumVector = 0;
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Descriptor->u.Interrupt.MaximumVector = 0xFF;
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}
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}
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else if ((PciConfig.HeaderType & 0x7F) == 1)
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{
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for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
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{
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if (!PdoGetRangeLength(DeviceExtension,
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0x10 + i * 4,
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&Base,
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&Length,
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&Flags))
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{
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DPRINT1("PdoGetRangeLength() failed\n");
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break;
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}
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if (Length == 0)
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{
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DPRINT("Unused address register\n");
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break;
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}
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/* Set preferred descriptor */
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Descriptor->Option = IO_RESOURCE_PREFERRED;
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if (Flags & PCI_ADDRESS_IO_SPACE)
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{
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO;
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Descriptor->u.Port.Length = Length;
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Descriptor->u.Port.Alignment = 1;
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Descriptor->u.Port.MinimumAddress.QuadPart = (ULONGLONG)Base;
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Descriptor->u.Port.MaximumAddress.QuadPart = (ULONGLONG)(Base + Length - 1);
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}
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else
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{
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Descriptor->Type = CmResourceTypeMemory;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
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Descriptor->u.Memory.Length = Length;
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Descriptor->u.Memory.Alignment = 1;
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Descriptor->u.Memory.MinimumAddress.QuadPart = (ULONGLONG)Base;
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Descriptor->u.Memory.MaximumAddress.QuadPart = (ULONGLONG)(Base + Length - 1);
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}
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Descriptor++;
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/* Set alternative descriptor */
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Descriptor->Option = IO_RESOURCE_ALTERNATIVE;
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if (Flags & PCI_ADDRESS_IO_SPACE)
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{
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO;
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Descriptor->u.Port.Length = Length;
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Descriptor->u.Port.Alignment = Length;
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Descriptor->u.Port.MinimumAddress.QuadPart = (ULONGLONG)0;
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Descriptor->u.Port.MaximumAddress.QuadPart = (ULONGLONG)(ULONG)-1;
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}
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else
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{
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Descriptor->Type = CmResourceTypeMemory;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
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Descriptor->u.Memory.Length = Length;
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Descriptor->u.Memory.Alignment = Length;
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Descriptor->u.Port.MinimumAddress.QuadPart = (ULONGLONG)0;
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Descriptor->u.Port.MaximumAddress.QuadPart = (ULONGLONG)0x00000000FFFFFFFF;
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}
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Descriptor++;
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}
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}
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Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
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return STATUS_SUCCESS;
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}
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@ -335,7 +585,7 @@ PdoQueryResources(
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PCM_PARTIAL_RESOURCE_LIST PartialList;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor;
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ULONG Size;
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ULONG ResCount;
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ULONG ResCount = 0;
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ULONG ListSize;
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ULONG i;
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ULONG Base;
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@ -367,20 +617,29 @@ PdoQueryResources(
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{
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for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
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{
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if (PciConfig.u.type0.BaseAddresses[i] == 0)
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if (!PdoGetRangeLength(DeviceExtension,
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0x10 + i * 4,
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&Base,
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&Length,
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&Flags))
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break;
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ResCount++;
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}
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if (PciConfig.u.type0.InterruptLine != 0xFF)
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if ((PciConfig.u.type0.InterruptPin != 0) &&
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(PciConfig.u.type0.InterruptLine != 0xFF))
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ResCount++;
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}
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else if ((PciConfig.HeaderType & 0x7F) == 1)
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{
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for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
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{
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if (PciConfig.u.type0.BaseAddresses[i] != 0)
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if (!PdoGetRangeLength(DeviceExtension,
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0x10 + i * 4,
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&Base,
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&Length,
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&Flags))
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break;
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ResCount++;
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@ -391,6 +650,12 @@ PdoQueryResources(
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DPRINT1("Unsupported header type %u\n", PciConfig.HeaderType);
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}
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if (ResCount == 0)
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{
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Irp->IoStatus.Information = 0;
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return STATUS_SUCCESS;
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}
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/* Calculate the resource list size */
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ListSize = sizeof(CM_RESOURCE_LIST);
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if (ResCount > 1)
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@ -437,7 +702,7 @@ PdoQueryResources(
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if (Flags & PCI_ADDRESS_IO_SPACE)
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{
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Descriptor->Type = CmResourceTypePort;
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// Descriptor->ShareDisposition =
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO;
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Descriptor->u.Port.Start.QuadPart =
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(ULONGLONG)Base;
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@ -446,7 +711,7 @@ PdoQueryResources(
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else
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{
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Descriptor->Type = CmResourceTypeMemory;
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// Descriptor->ShareDisposition =
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
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Descriptor->u.Memory.Start.QuadPart =
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(ULONGLONG)Base;
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@ -456,26 +721,60 @@ PdoQueryResources(
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Descriptor++;
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}
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if (PciConfig.u.type0.InterruptLine != 0xFF)
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/* Add interrupt resource */
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if ((PciConfig.u.type0.InterruptPin != 0) &&
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(PciConfig.u.type0.InterruptLine != 0xFF))
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{
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Descriptor->Type = CmResourceTypeInterrupt;
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// Descriptor->ShareDisposition =
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Descriptor->ShareDisposition = CmResourceShareShared;
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Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
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Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
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Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
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Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
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}
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}
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#if 0
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else if ((PciConfig.HeaderType & 0x7F) == 1)
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{
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for (i = 0; i < PCI_TYPE1_ADDRESSES; i++)
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{
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if (PciConfig.u.type0.BaseAddresses[i] != 0)
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ResCount++;
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if (!PdoGetRangeLength(DeviceExtension,
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0x10 + i * 4,
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&Base,
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&Length,
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&Flags))
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{
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DPRINT1("PdoGetRangeLength() failed\n");
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break;
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}
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if (Length == 0)
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{
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DPRINT("Unused address register\n");
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break;
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}
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if (Flags & PCI_ADDRESS_IO_SPACE)
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{
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Descriptor->Type = CmResourceTypePort;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_PORT_IO;
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Descriptor->u.Port.Start.QuadPart =
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(ULONGLONG)Base;
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Descriptor->u.Port.Length = Length;
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}
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else
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{
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Descriptor->Type = CmResourceTypeMemory;
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Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
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Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
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Descriptor->u.Memory.Start.QuadPart =
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(ULONGLONG)Base;
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Descriptor->u.Memory.Length = Length;
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}
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Descriptor++;
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}
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}
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#endif
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Irp->IoStatus.Information = (ULONG_PTR)ResourceList;
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