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https://github.com/reactos/reactos.git
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[ÇNTOSKRNL]
- modify MiResolveDemandZeroFault to take the page protection as a parameter instead of the PTE. This will be used soon. - Move increment of counters into the region where the pfn lock is held to avoid race conditions and make heavy locked operations unneccessary - Add some ASSERTs svn path=/trunk/; revision=55454
This commit is contained in:
Timo Kreuzer
parent
12f8a6d6a6
commit
b207b33d11
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@ -209,11 +209,12 @@ MiZeroPfn(IN PFN_NUMBER PageFrameNumber)
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NTSTATUS
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NTAPI
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MiResolveDemandZeroFault(IN PVOID Address,
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IN PMMPTE PointerPte,
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IN ULONG Protection,
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IN PEPROCESS Process,
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IN KIRQL OldIrql)
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{
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PFN_NUMBER PageFrameNumber = 0;
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PMMPTE PointerPte = MiAddressToPte(Address);
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MMPTE TempPte;
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BOOLEAN NeedZero = FALSE, HaveLock = FALSE;
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ULONG Color;
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@ -294,14 +295,12 @@ MiResolveDemandZeroFault(IN PVOID Address,
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/* Initialize it */
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MiInitializePfn(PageFrameNumber, PointerPte, TRUE);
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/* Increment demand zero faults */
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KeGetCurrentPrcb()->MmDemandZeroCount++;
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/* Release PFN lock if needed */
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if (HaveLock) KeReleaseQueuedSpinLock(LockQueuePfnLock, OldIrql);
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//
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// Increment demand zero faults
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//
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InterlockedIncrement(&KeGetCurrentPrcb()->MmDemandZeroCount);
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/* Zero the page if need be */
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if (NeedZero) MiZeroPfn(PageFrameNumber);
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@ -311,7 +310,7 @@ MiResolveDemandZeroFault(IN PVOID Address,
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/* For user mode */
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MI_MAKE_HARDWARE_PTE_USER(&TempPte,
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PointerPte,
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PointerPte->u.Soft.Protection,
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Protection,
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PageFrameNumber);
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}
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else
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@ -319,7 +318,7 @@ MiResolveDemandZeroFault(IN PVOID Address,
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/* For kernel mode */
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MI_MAKE_HARDWARE_PTE(&TempPte,
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PointerPte,
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PointerPte->u.Soft.Protection,
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Protection,
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PageFrameNumber);
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}
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@ -462,7 +461,10 @@ MiResolveProtoPteFault(IN BOOLEAN StoreInstruction,
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ASSERT(TempPte.u.Soft.Transition == 0);
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/* Resolve the demand zero fault */
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Status = MiResolveDemandZeroFault(Address, PointerProtoPte, Process, OldIrql);
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Status = MiResolveDemandZeroFault(Address,
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(ULONG)PointerProtoPte->u.Soft.Protection,
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Process,
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OldIrql);
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ASSERT(NT_SUCCESS(Status));
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/* Complete the prototype PTE fault -- this will release the PFN lock */
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@ -494,6 +496,9 @@ MiDispatchFault(IN BOOLEAN StoreInstruction,
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Address,
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Process);
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/* Make sure the addresses are ok */
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ASSERT(PointerPte == MiAddressToPte(Address));
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//
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// Make sure APCs are off and we're not at dispatch
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//
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@ -609,7 +614,7 @@ MiDispatchFault(IN BOOLEAN StoreInstruction,
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// we want. Go handle it!
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//
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Status = MiResolveDemandZeroFault(Address,
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PointerPte,
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(ULONG)PointerPte->u.Soft.Protection,
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Process,
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MM_NOIRQL);
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ASSERT(KeAreAllApcsDisabled() == TRUE);
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@ -658,30 +663,23 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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DPRINT("ARM3 FAULT AT: %p\n", Address);
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//
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// Check for dispatch-level snafu
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//
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/* Check for page fault on high IRQL */
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if (OldIrql > APC_LEVEL)
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{
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//
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// There are some special cases where this is okay, but not in ARM3 yet
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//
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DbgPrint("MM:***PAGE FAULT AT IRQL > 1 Va %p, IRQL %lx\n",
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Address,
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OldIrql);
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ASSERT(OldIrql <= APC_LEVEL);
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}
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//
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// Check for kernel fault address
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//
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/* Check for kernel fault address */
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while (Address >= MmSystemRangeStart)
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{
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//
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// What are you even DOING here?
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//
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/* Bail out, if the fault came from user mode */
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if (Mode == UserMode) return STATUS_ACCESS_VIOLATION;
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/* PXEs and PPEs for kernel mode are mapped for everything we need */
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#if (_MI_PAGING_LEVELS >= 3)
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if (
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#if (_MI_PAGING_LEVELS == 4)
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@ -689,6 +687,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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#endif
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(PointerPpe->u.Hard.Valid == 0))
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{
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/* The address is not from any pageable area! */
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KeBugCheckEx(PAGE_FAULT_IN_NONPAGED_AREA,
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(ULONG_PTR)Address,
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StoreInstruction,
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@ -697,9 +696,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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}
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#endif
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//
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// Is the PDE valid?
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//
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/* Check if the PDE is invalid */
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if (PointerPde->u.Hard.Valid == 0)
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{
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//
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@ -732,9 +729,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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}
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}
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//
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// The PDE is valid, so read the PTE
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//
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/* The PDE is valid, so read the PTE */
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TempPte = *PointerPte;
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if (TempPte.u.Hard.Valid == 1)
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{
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@ -751,9 +746,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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return STATUS_SUCCESS;
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}
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//
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// Check for a fault on the page table or hyperspace itself
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//
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// Check for a fault on the page table or hyperspace
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if (MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address))
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{
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#if (_MI_PAGING_LEVELS == 2)
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@ -776,26 +769,21 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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KeRaiseIrql(APC_LEVEL, &LockIrql);
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MiLockWorkingSet(CurrentThread, WorkingSet);
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//
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// Re-read PTE now that the IRQL has been raised
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//
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/* Re-read PTE now that we own the lock */
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TempPte = *PointerPte;
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if (TempPte.u.Hard.Valid == 1)
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{
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//
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// Only two things can go wrong here:
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// Executing NX page (we couldn't care less)
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// Writing to a read-only page (the stuff ARM3 works with is write,
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// so again, moot point.
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//
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// so again, moot point).
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ASSERT(TempPte.u.Hard.Write == 1);
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/* Release the working set */
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MiUnlockWorkingSet(CurrentThread, WorkingSet);
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KeLowerIrql(LockIrql);
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//
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// Otherwise, the PDE was probably invalid, and all is good now
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//
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return STATUS_SUCCESS;
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}
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@ -823,15 +811,13 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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}
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else
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{
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//
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// We don't implement transition PTEs
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//
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/* We don't implement transition PTEs */
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ASSERT(TempPte.u.Soft.Transition == 0);
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/* Check for no-access PTE */
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if (TempPte.u.Soft.Protection == MM_NOACCESS)
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{
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/* Bad boy, bad boy, whatcha gonna do, whatcha gonna do when ARM3 comes for you! */
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/* Bugcheck the system! */
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KeBugCheckEx(PAGE_FAULT_IN_NONPAGED_AREA,
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(ULONG_PTR)Address,
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StoreInstruction,
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@ -855,9 +841,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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}
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}
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//
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// Now do the real fault handling
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//
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/* Now do the real fault handling */
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Status = MiDispatchFault(StoreInstruction,
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Address,
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PointerPte,
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@ -872,9 +856,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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MiUnlockWorkingSet(CurrentThread, WorkingSet);
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KeLowerIrql(LockIrql);
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//
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// We are done!
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//
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/* We are done! */
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DPRINT("Fault resolved with status: %lx\n", Status);
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return Status;
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}
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@ -939,7 +921,7 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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{
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/* Resolve the fault */
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MiResolveDemandZeroFault(Address,
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PointerPte,
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(ULONG)PointerPte->u.Soft.Protection,
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CurrentProcess,
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MM_NOIRQL);
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@ -1038,11 +1020,12 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
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/* Initialize the PFN entry now */
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MiInitializePfn(PageFrameIndex, PointerPte, 1);
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/* One more demand-zero fault */
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KeGetCurrentPrcb()->MmDemandZeroCount++;
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/* And we're done with the lock */
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KeReleaseQueuedSpinLock(LockQueuePfnLock, OldIrql);
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/* One more demand-zero fault */
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InterlockedIncrement(&KeGetCurrentPrcb()->MmDemandZeroCount);
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/* Was the fault on an actual user page, or a kernel page for the user? */
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if (PointerPte <= MiHighestUserPte)
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