- Detect PCI busses

- Detect IDE controllers and devices
- Improved RegEnumValue()

svn path=/trunk/; revision=4581

freeldr/freeldr/CHANGELOG

@@ -1,3 +1,9 @@
+Changes in v1.8.9 (4/25/2003) (chorns)
+
+- Detect PCI busses
+- Detect IDE controllers and devices
+- Improved RegEnumValue()
+
 Changes in v1.8.8 (4/25/2003) (ekohl)
 
 - Added memmove().

freeldr/freeldr/debug.c

@@ -204,6 +204,18 @@ VOID DebugPrintHeader(U32 Mask)
 		DebugPrintChar(':');
 		DebugPrintChar(' ');
 		break;
+	case DPRINT_HWDETECT:
+		DebugPrintChar('H');
+		DebugPrintChar('W');
+		DebugPrintChar('D');
+		DebugPrintChar('E');
+		DebugPrintChar('T');
+		DebugPrintChar('E');
+		DebugPrintChar('C');
+		DebugPrintChar('T');
+		DebugPrintChar(':');
+		DebugPrintChar(' ');
+		break;
 	default:
 		DebugPrintChar('U');
 		DebugPrintChar('N');

freeldr/freeldr/fs/ext2.c

@@ -845,7 +845,7 @@ BOOL Ext2ReadBlock(U32 BlockNumber, PVOID Buffer)
 	// Make sure its a valid block
 	if (BlockNumber > Ext2SuperBlock->s_blocks_count)
 	{
-		sprintf(ErrorString, "Error reading block %d - block out of range.", BlockNumber);
+		sprintf(ErrorString, "Error reading block %d - block out of range.", (int) BlockNumber);
 		FileSystemError(ErrorString);
 		return FALSE;
 	}

freeldr/freeldr/include/debug.h

@@ -34,6 +34,7 @@
 	#define DPRINT_REGISTRY		0x00000080  // OR this with DebugPrintMask to enable registry messages
 	#define DPRINT_REACTOS		0x00000100  // OR this with DebugPrintMask to enable ReactOS messages
 	#define DPRINT_LINUX		  0x00000200  // OR this with DebugPrintMask to enable Linux messages
+  #define DPRINT_HWDETECT		0x00000400  // OR this with DebugPrintMask to enable hardware detection messages
 
 	VOID	DebugInit(VOID);
 	VOID	DebugPrint(U32 Mask, char *format, ...);

freeldr/freeldr/include/freeldr.h

@@ -26,6 +26,7 @@
 
 #define BOOL	int
 #define BOOLEAN	int
+typedef BOOLEAN *PBOOLEAN;
 
 #define CHAR	char
 #define PCHAR	char *
@@ -61,6 +62,10 @@ typedef S64					__s64;
 
 #endif // __i386__
 
+typedef U8 *PU8;
+typedef U16 *PU16;
+typedef U32 *PU32;
+
 #define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
 
 #define PACKED __attribute__((packed))

freeldr/freeldr/include/version.h

@@ -22,7 +22,7 @@
 
 
 /* just some stuff */
-#define VERSION			"FreeLoader v1.8.8"
+#define VERSION			"FreeLoader v1.8.9"
 #define COPYRIGHT		"Copyright (C) 1998-2003 Brian Palmer <brianp@sginet.com>"
 #define AUTHOR_EMAIL	"<brianp@sginet.com>"
 #define BY_AUTHOR		"by Brian Palmer"
@@ -36,7 +36,7 @@
 //
 #define FREELOADER_MAJOR_VERSION	1
 #define FREELOADER_MINOR_VERSION	8
-#define FREELOADER_PATCH_VERSION	8
+#define FREELOADER_PATCH_VERSION	9
 
 
 PUCHAR	GetFreeLoaderVersionString(VOID);

freeldr/freeldr/reactos/arcname.c

@@ -85,7 +85,7 @@ void ConstructArcPath(PUCHAR ArcPath, PUCHAR SystemFolder, U32 Disk, U32 Partiti
 		 * floppy disk path:
 		 *  multi(0)disk(0)fdisk(x)\path
 		 */
-		sprintf(tmp, "fdisk(%d)", Disk);
+		sprintf(tmp, "fdisk(%d)", (int) Disk);
 		strcat(ArcPath, tmp);
 	}
 	else
@@ -94,7 +94,7 @@ void ConstructArcPath(PUCHAR ArcPath, PUCHAR SystemFolder, U32 Disk, U32 Partiti
 		 * hard disk path:
 		 *  multi(0)disk(0)rdisk(x)partition(y)\path
 		 */
-		sprintf(tmp, "rdisk(%d)partition(%d)", (Disk - 0x80), Partition);
+		sprintf(tmp, "rdisk(%d)partition(%d)", (int) (Disk - 0x80), (int) Partition);
 		strcat(ArcPath, tmp);
 	}
 

freeldr/freeldr/reactos/hwdetect.h

@@ -21,6 +21,397 @@
 #ifndef __HWDETECT_H
 #define __HWDETECT_H
 
+typedef enum _INTERFACE_TYPE
+{
+  InterfaceTypeUndefined = -1,
+  Internal,
+  Isa,
+  Eisa,
+  MicroChannel,
+  TurboChannel,
+  PCIBus,
+  VMEBus,
+  NuBus,
+  PCMCIABus,
+  CBus,
+  MPIBus,
+  MPSABus,
+  ProcessorInternal,
+  InternalPowerBus,
+  PNPISABus,
+  MaximumInterfaceType
+} INTERFACE_TYPE, *PINTERFACE_TYPE;
+
+typedef enum _BUS_DATA_TYPE
+{
+  ConfigurationSpaceUndefined = -1,
+  Cmos,
+  EisaConfiguration,
+  Pos,
+  CbusConfiguration,
+  PCIConfiguration,
+  VMEConfiguration,
+  NuBusConfiguration,
+  PCMCIAConfiguration,
+  MPIConfiguration,
+  MPSAConfiguration,
+  PNPISAConfiguration,
+  MaximumBusDataType,
+} BUS_DATA_TYPE, *PBUS_DATA_TYPE;
+
+typedef struct _CM_INT13_DRIVE_PARAMETER {
+  U16 DriveSelect;
+  U32 MaxCylinders;
+  U16 SectorsPerTrack;
+  U16 MaxHeads;
+  U16 NumberDrives;
+} CM_INT13_DRIVE_PARAMETER, *PCM_INT13_DRIVE_PARAMETER;
+
+/* PCI bus definitions */
+
+#define PCI_TYPE0_ADDRESSES	6
+#define PCI_TYPE1_ADDRESSES	2
+#define PCI_TYPE2_ADDRESSES	5
+
+typedef struct _PCI_COMMON_CONFIG
+{
+  U16 VendorID;		/* read-only */
+  U16 DeviceID;		/* read-only */
+  U16 Command;
+  U16 Status;
+  U8  RevisionID;		/* read-only */
+  U8  ProgIf;		/* read-only */
+  U8  SubClass;		/* read-only */
+  U8  BaseClass;		/* read-only */
+  U8  CacheLineSize;		/* read-only */
+  U8  LatencyTimer;		/* read-only */
+  U8  HeaderType;		/* read-only */
+  U8  BIST;
+  union
+    {
+      struct _PCI_HEADER_TYPE_0
+      	{
+      	  U32  BaseAddresses[PCI_TYPE0_ADDRESSES];
+      	  U32  CIS;
+      	  U16 SubVendorID;
+      	  U16 SubSystemID;
+      	  U32  ROMBaseAddress;
+      	  U32  Reserved2[2];
+      
+      	  U8  InterruptLine;
+      	  U8  InterruptPin;		/* read-only */
+      	  U8  MinimumGrant;		/* read-only */
+      	  U8  MaximumLatency;	/* read-only */
+      	} type0;
+
+      /* PCI to PCI Bridge */
+      struct _PCI_HEADER_TYPE_1
+      	{
+      	  U32  BaseAddresses[PCI_TYPE1_ADDRESSES];
+      	  U8  PrimaryBus;
+      	  U8  SecondaryBus;
+      	  U8  SubordinateBus;
+      	  U8  SecondaryLatency;
+      	  U8  IOBase;
+      	  U8  IOLimit;
+      	  U16 SecondaryStatus;
+      	  U16 MemoryBase;
+      	  U16 MemoryLimit;
+      	  U16 PrefetchBase;
+      	  U16 PrefetchLimit;
+      	  U32  PrefetchBaseUpper32;
+      	  U32  PrefetchLimitUpper32;
+      	  U16 IOBaseUpper16;
+      	  U16 IOLimitUpper16;
+      	  U8  CapabilitiesPtr;
+      	  U8  Reserved1[3];
+      	  U32  ROMBaseAddress;
+      	  U8  InterruptLine;
+      	  U8  InterruptPin;
+      	  U16 BridgeControl;
+      	} type1;
+
+      /* PCI to CARDBUS Bridge */
+      struct _PCI_HEADER_TYPE_2
+      	{
+      	  U32  SocketRegistersBaseAddress;
+      	  U8  CapabilitiesPtr;
+      	  U8  Reserved;
+      	  U16 SecondaryStatus;
+      	  U8  PrimaryBus;
+      	  U8  SecondaryBus;
+      	  U8  SubordinateBus;
+      	  U8  SecondaryLatency;
+      	  struct
+      	    {
+      	      U32 Base;
+      	      U32 Limit;
+      	    } Range[PCI_TYPE2_ADDRESSES-1];
+      	  U8  InterruptLine;
+      	  U8  InterruptPin;
+      	  U16 BridgeControl;
+      	} type2;
+    } u;
+  U8 DeviceSpecific[192];
+} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
+
+#define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
+
+#define PCI_MAX_DEVICES                     32
+#define PCI_MAX_FUNCTION                    8
+
+#define PCI_INVALID_VENDORID                0xFFFF
+
+/* Bit encodings for PCI_COMMON_CONFIG.HeaderType */
+
+#define PCI_MULTIFUNCTION                   0x80
+#define PCI_DEVICE_TYPE                     0x00
+#define PCI_BRIDGE_TYPE                     0x01
+
+
+/* Bit encodings for PCI_COMMON_CONFIG.Command */
+
+#define PCI_ENABLE_IO_SPACE                 0x0001
+#define PCI_ENABLE_MEMORY_SPACE             0x0002
+#define PCI_ENABLE_BUS_MASTER               0x0004
+#define PCI_ENABLE_SPECIAL_CYCLES           0x0008
+#define PCI_ENABLE_WRITE_AND_INVALIDATE     0x0010
+#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE   0x0020
+#define PCI_ENABLE_PARITY                   0x0040
+#define PCI_ENABLE_WAIT_CYCLE               0x0080
+#define PCI_ENABLE_SERR                     0x0100
+#define PCI_ENABLE_FAST_BACK_TO_BACK        0x0200
+
+
+/* Bit encodings for PCI_COMMON_CONFIG.Status */
+
+#define PCI_STATUS_FAST_BACK_TO_BACK        0x0080
+#define PCI_STATUS_DATA_PARITY_DETECTED     0x0100
+#define PCI_STATUS_DEVSEL                   0x0600  /* 2 bits wide */
+#define PCI_STATUS_SIGNALED_TARGET_ABORT    0x0800
+#define PCI_STATUS_RECEIVED_TARGET_ABORT    0x1000
+#define PCI_STATUS_RECEIVED_MASTER_ABORT    0x2000
+#define PCI_STATUS_SIGNALED_SYSTEM_ERROR    0x4000
+#define PCI_STATUS_DETECTED_PARITY_ERROR    0x8000
+
+
+/* PCI device classes */
+
+#define PCI_CLASS_PRE_20                    0x00
+#define PCI_CLASS_MASS_STORAGE_CTLR         0x01
+#define PCI_CLASS_NETWORK_CTLR              0x02
+#define PCI_CLASS_DISPLAY_CTLR              0x03
+#define PCI_CLASS_MULTIMEDIA_DEV            0x04
+#define PCI_CLASS_MEMORY_CTLR               0x05
+#define PCI_CLASS_BRIDGE_DEV                0x06
+#define PCI_CLASS_SIMPLE_COMMS_CTLR         0x07
+#define PCI_CLASS_BASE_SYSTEM_DEV           0x08
+#define PCI_CLASS_INPUT_DEV                 0x09
+#define PCI_CLASS_DOCKING_STATION           0x0a
+#define PCI_CLASS_PROCESSOR                 0x0b
+#define PCI_CLASS_SERIAL_BUS_CTLR           0x0c
+
+
+/* PCI device subclasses for class 1 (mass storage controllers)*/
+
+#define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR      0x00
+#define PCI_SUBCLASS_MSC_IDE_CTLR           0x01
+#define PCI_SUBCLASS_MSC_FLOPPY_CTLR        0x02
+#define PCI_SUBCLASS_MSC_IPI_CTLR           0x03
+#define PCI_SUBCLASS_MSC_RAID_CTLR          0x04
+#define PCI_SUBCLASS_MSC_OTHER              0x80
+
+
+/* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
+
+#define PCI_ADDRESS_IO_SPACE                0x00000001
+#define PCI_ADDRESS_MEMORY_TYPE_MASK        0x00000006
+#define PCI_ADDRESS_MEMORY_PREFETCHABLE     0x00000008
+
+#define PCI_ADDRESS_IO_ADDRESS_MASK         0xfffffffc
+#define PCI_ADDRESS_MEMORY_ADDRESS_MASK     0xfffffff0
+#define PCI_ADDRESS_ROM_ADDRESS_MASK        0xfffff800
+
+#define PCI_TYPE_32BIT      0
+#define PCI_TYPE_20BIT      2
+#define PCI_TYPE_64BIT      4
+
+
+/* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
+
+#define PCI_ROMADDRESS_ENABLED              0x00000001
+
+typedef struct _PCI_SLOT_NUMBER
+{
+  union
+    {
+      struct
+        {
+          U32 DeviceNumber:5;
+          U32 FunctionNumber:3;
+          U32 Reserved:24;
+        } bits;
+      U32 AsULONG;
+    } u;
+} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
+
+
+
+/* ***** BEGIN ATA ***** */
+
+#define  IDE_SECTOR_BUF_SZ      512
+#define  IDE_MAX_POLL_RETRIES   100000
+#define  IDE_MAX_BUSY_RETRIES   50000
+
+// Control Block offsets and masks
+#define  IDE_REG_DEV_CNTRL      0x0000  /* device control register */
+#define    IDE_DC_nIEN            0x02  /* IRQ enable (active low) */
+
+// Command Block offsets and masks
+#define  IDE_REG_DATA_PORT      0x0000
+#define  IDE_REG_ERROR          0x0001  /* error register */
+#define    IDE_ER_AMNF            0x01  /* address mark not found */
+#define    IDE_ER_TK0NF           0x02  /* Track 0 not found */
+#define    IDE_ER_ABRT            0x04  /* Command aborted */
+#define    IDE_ER_MCR             0x08  /* Media change requested */
+#define    IDE_ER_IDNF            0x10  /* ID not found */
+#define    IDE_ER_MC              0x20  /* Media changed */
+#define    IDE_ER_UNC             0x40  /* Uncorrectable data error */
+#define  IDE_REG_PRECOMP        0x0001
+#define  IDE_REG_SECTOR_CNT     0x0002
+#define  IDE_REG_SECTOR_NUM     0x0003
+#define  IDE_REG_CYL_LOW        0x0004
+#define  IDE_REG_CYL_HIGH       0x0005
+#define  IDE_REG_DRV_HEAD       0x0006
+#define    IDE_DH_FIXED           0xA0
+#define    IDE_DH_LBA             0x40
+#define    IDE_DH_HDMASK          0x0F
+#define    IDE_DH_DRV0            0x00
+#define    IDE_DH_DRV1            0x10
+#define  IDE_REG_STATUS         0x0007
+#define    IDE_SR_BUSY            0x80
+#define    IDE_SR_DRQ             0x08
+#define    IDE_SR_ERR             0x01
+#define  IDE_REG_COMMAND        0x0007
+
+/* IDE/ATA commands */
+#define    IDE_CMD_RESET            0x08
+#define    IDE_CMD_IDENT_ATA_DRV    0xEC
+#define    IDE_CMD_IDENT_ATAPI_DRV  0xA1
+
+/* Access macros for command registers
+   Each macro takes an address of the command port block, and data */
+#define IDEWritePrecomp(Address, Data) \
+  (WRITE_PORT_UCHAR((PU8)((Address) + IDE_REG_PRECOMP), (Data)))
+#define IDEWriteSectorCount(Address, Data) \
+  (WRITE_PORT_UCHAR((PU8)((Address) + IDE_REG_SECTOR_CNT), (Data)))
+#define IDEWriteSectorNum(Address, Data) \
+  (WRITE_PORT_UCHAR((PU8)((Address) + IDE_REG_SECTOR_NUM), (Data)))
+#define IDEReadCylinderLow(Address) \
+  (READ_PORT_UCHAR((PU8)((Address) + IDE_REG_CYL_LOW)))
+#define IDEWriteCylinderLow(Address, Data) \
+  (WRITE_PORT_UCHAR((PU8)((Address) + IDE_REG_CYL_LOW), (Data)))
+#define IDEReadCylinderHigh(Address) \
+  (READ_PORT_UCHAR((PU8)((Address) + IDE_REG_CYL_HIGH)))
+#define IDEWriteCylinderHigh(Address, Data) \
+  (WRITE_PORT_UCHAR((PU8)((Address) + IDE_REG_CYL_HIGH), (Data)))
+#define IDEWriteDriveHead(Address, Data) \
+  (WRITE_PORT_UCHAR((PU8)((Address) + IDE_REG_DRV_HEAD), (Data)))
+#define IDEWriteDriveControl(Address, Data) \
+  (WRITE_PORT_UCHAR((PU8)((Address) + IDE_REG_DEV_CNTRL), (Data)))
+#define IDEReadStatus(Address) \
+  (READ_PORT_UCHAR((PU8)((Address) + IDE_REG_STATUS)))
+#define IDEWriteCommand(Address, Data) \
+  (WRITE_PORT_UCHAR((PU8)((Address) + IDE_REG_COMMAND), (Data)))
+
+/* Data block read and write commands */
+#define IDEReadBlock(Address, Buffer, Count) \
+  (READ_PORT_BUFFER_USHORT((PU16)((Address) + IDE_REG_DATA_PORT), \
+  (PU16)(Buffer), (Count) / 2))
+
+typedef struct _IDE_DRIVE_IDENTIFY
+{
+  U16  ConfigBits;             /*00*/
+  U16  LogicalCyls;            /*01*/
+  U16  Reserved02;             /*02*/
+  U16  LogicalHeads;           /*03*/
+  U16  BytesPerTrack;          /*04*/
+  U16  BytesPerSector;         /*05*/
+  U16  SectorsPerTrack;        /*06*/
+  U8   InterSectorGap;         /*07*/
+  U8   InterSectorGapSize;
+  U8   Reserved08H;            /*08*/
+  U8   BytesInPLO;
+  U16  VendorUniqueCnt;        /*09*/
+  CHAR SerialNumber[20];       /*10*/
+  U16  ControllerType;         /*20*/
+  U16  BufferSize;             /*21*/
+  U16  ECCByteCnt;             /*22*/
+  CHAR FirmwareRev[8];         /*23*/
+  CHAR ModelNumber[40];        /*27*/
+  U16  RWMultImplemented;      /*47*/
+  U16  DWordIo;	               /*48*/
+  U16  Capabilities;           /*49*/
+#define IDE_DRID_STBY_SUPPORTED   0x2000
+#define IDE_DRID_IORDY_SUPPORTED  0x0800
+#define IDE_DRID_IORDY_DISABLE    0x0400
+#define IDE_DRID_LBA_SUPPORTED    0x0200
+#define IDE_DRID_DMA_SUPPORTED    0x0100
+  U16  Reserved50;             /*50*/
+  U16  MinPIOTransTime;        /*51*/
+  U16  MinDMATransTime;        /*52*/
+  U16  TMFieldsValid;          /*53*/
+  U16  TMCylinders;            /*54*/
+  U16  TMHeads;                /*55*/
+  U16  TMSectorsPerTrk;        /*56*/
+  U16  TMCapacityLo;           /*57*/
+  U16  TMCapacityHi;           /*58*/
+  U16  RWMultCurrent;          /*59*/
+  U16  TMSectorCountLo;        /*60*/
+  U16  TMSectorCountHi;        /*61*/
+  U16  Reserved62[193];        /*62*/
+  U16  Checksum;               /*255*/
+} IDE_DRIVE_IDENTIFY, *PIDE_DRIVE_IDENTIFY;
+
+/* ***** END ATA ***** */
+
+typedef struct _DETECTED_BUS
+{
+  LIST_ENTRY ListEntry;
+  INTERFACE_TYPE BusType;
+  U32 BusNumber;
+  CHAR Identifier[20];
+} DETECTED_BUS, *PDETECTED_BUS;
+
+typedef struct _DETECTED_BUSSES
+{
+  LIST_ENTRY Busses; /* DETECTED_BUS */
+} DETECTED_BUSSES, *PDETECTED_BUSSES;
+
+
+typedef struct _DETECTED_STORAGE_CONTROLLER
+{
+  LIST_ENTRY ListEntry;
+  INTERFACE_TYPE BusType;
+  U32 BusNumber;
+  U32 DriveCount;
+  IDE_DRIVE_IDENTIFY IdeDriveIdentify[2];
+} DETECTED_STORAGE_CONTROLLER, *PDETECTED_STORAGE_CONTROLLER;
+
+typedef struct _DETECTED_STORAGE
+{
+  LIST_ENTRY StorageControllers; /* DETECTED_STORAGE_CONTROLLER */
+} DETECTED_STORAGE, *PDETECTED_STORAGE;
+
+
+typedef struct _REGISTRY_BUS_INFORMATION
+{
+  LIST_ENTRY ListEntry;
+  HKEY BusKey;
+  INTERFACE_TYPE BusType;
+  U32 BusNumber;
+} REGISTRY_BUS_INFORMATION, *PREGISTRY_BUS_INFORMATION;
+
 VOID DetectHardware(VOID);
 
 #endif /* __HWDETECT_H */

freeldr/freeldr/reactos/registry.c

@@ -753,10 +753,21 @@ RegEnumValue(HKEY Key,
 	    *ValueName = 0;
 	  if (Type != NULL)
 	    *Type = Key->DataType;
+      if (Data != NULL)
+        {
+          if (Key->DataSize <= sizeof(PUCHAR))
+            {
+              memcpy(Data, &Key->Data, min(Key->DataSize, *DataSize));
+            }
+          else
+            {
+              memcpy(Data, Key->Data, min(Key->DataSize, *DataSize));
+            }
+        }
 	  if (DataSize != NULL)
-	    *DataSize = Key->DataSize;
+	    *DataSize = min(Key->DataSize, *DataSize);
 
-	  /* FIXME: return more values */
+      return(ERROR_SUCCESS);
 	}
     }
 
@@ -777,7 +788,26 @@ RegEnumValue(HKEY Key,
 			    VALUE,
 			    ValueList);
 
-  /* FIXME: return values */
+  /* enumerate non-default value */
+  if (ValueName != NULL)
+    memcpy(ValueName, Value->Name, min(Value->NameSize, *NameSize));
+  if (Type != NULL)
+    *Type = Value->DataType;
+
+  if (Data != NULL)
+    {
+      if (Value->DataSize <= sizeof(PUCHAR))
+        {
+          memcpy(Data, &Value->Data, min(Value->DataSize, *DataSize));
+        }
+      else
+        {
+          memcpy(Data, Value->Data, min(Value->DataSize, *DataSize));
+        }
+    }
+
+  if (DataSize != NULL)
+    *DataSize = min(Value->DataSize, *DataSize);
 
   return(ERROR_SUCCESS);
 }

freeldr/freeldr/ui/ui.c

@@ -110,7 +110,7 @@ BOOL UiInitialize(VOID)
 
 			if (!VideoSetMode(VideoMode))
 			{
-				printf("Error: unable to set video display mode 0x%x\n", VideoMode);
+				printf("Error: unable to set video display mode 0x%x\n", (int) VideoMode);
 				printf("Defaulting to 80x25 text mode.\n");
 				printf("Press any key to continue.\n");
 				getch();

freeldr/freeldr/video/pixel.c

@@ -46,7 +46,7 @@
 //
 VOID VideoSetPixel16(U32 X, U32 Y, U8 Color)
 {
-	U8		CurrentColor;
+	//U8		CurrentColor;
 	U8*		MemoryPointer;
 	U32		ByteOffset;
 	U8		BitInByte;