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[NTOSKRNL]

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Fix ARM build

svn path=/trunk/; revision=67735
This commit is contained in:
Timo Kreuzer 2015-05-14 22:31:58 +00:00
parent 014f5582c3
commit adc234ba9c
17 changed files with 400 additions and 309 deletions
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4
reactos/ntoskrnl/ex/sysinfo.c
View file

@ -1597,7 +1597,9 @@ QSI_DEF(SystemExceptionInformation)
{
AlignmentFixupCount += Prcb->KeAlignmentFixupCount;
ExceptionDispatchCount += Prcb->KeExceptionDispatchCount;
#ifndef _M_ARM
FloatingEmulationCount += Prcb->KeFloatingEmulationCount;
#endif // _M_ARM
}
}
@ -2353,7 +2355,7 @@ NtFlushInstructionCache(IN HANDLE ProcessHandle,
DPRINT1("NtFlushInstructionCache() is not implemented\n");
for (;;);
#elif defined(_M_ARM)
__asm__ __volatile__("mov r1, #0; mcr p15, 0, r1, c7, c5, 0");
//__asm__ __volatile__("mov r1, #0; mcr p15, 0, r1, c7, c5, 0");
#else
#error Unknown architecture
#endif

10
reactos/ntoskrnl/include/internal/arm/ke.h
View file

@ -18,7 +18,7 @@
//
#define KD_BREAKPOINT_TYPE ULONG
#define KD_BREAKPOINT_SIZE sizeof(ULONG)
//#define KD_BREAKPOINT_VALUE
#define KD_BREAKPOINT_VALUE 0xDEFE
//
// Maximum IRQs
@ -59,7 +59,7 @@
// All architectures but x86 have it in the PRCB's KeContextSwitches
//
#define KeGetContextSwitches(Prcb) \
CONTAINING_RECORD(Prcb, KIPCR, PrcbData)->ContextSwitches
(Prcb)->KeContextSwitches
//
// Macro to get the second level cache size field name which differs between
@ -71,7 +71,7 @@
// Returns the Interrupt State from a Trap Frame.
// ON = TRUE, OFF = FALSE
//
//#define KeGetTrapFrameInterruptState(TrapFrame)
#define KeGetTrapFrameInterruptState(TrapFrame) 0
FORCEINLINE
BOOLEAN
@ -162,7 +162,7 @@ HalSweepIcache(
#define KiEndInterrupt(x,y)
#define KiGetLinkedTrapFrame(x) \
(PKTRAP_FRAME)((x)->PreviousTrapFrame)
(PKTRAP_FRAME)((x)->TrapFrame)
#define KiGetPreviousMode(tf) \
((tf->Spsr & CPSR_MODES) == CPSR_USER_MODE) ? UserMode: KernelMode
((tf->Cpsr & CPSRM_MASK) == CPSRM_USER) ? UserMode: KernelMode

4
reactos/ntoskrnl/include/internal/ke_x.h
View file

@ -383,7 +383,7 @@ KiRescheduleThread(IN BOOLEAN NewThread,
IN ULONG Cpu)
{
/* Check if a new thread needs to be scheduled on a different CPU */
if ((NewThread) && !(KeGetPcr()->Number == Cpu))
if ((NewThread) && !(KeGetCurrentPrcb()->Number == Cpu))
{
/* Send an IPI to request delivery */
KiIpiSend(AFFINITY_MASK(Cpu), IPI_DPC);
@ -534,7 +534,7 @@ KiRequestApcInterrupt(IN BOOLEAN NeedApc,
if (NeedApc)
{
/* Check if it's on another CPU */
if (KeGetPcr()->Number != Processor)
if (KeGetCurrentPrcb()->Number != Processor)
{
/* Send an IPI to request delivery */
KiIpiSend(AFFINITY_MASK(Processor), IPI_APC);

16
reactos/ntoskrnl/kd/arm/kdbg.c
View file

@ -55,24 +55,24 @@ KdPortInitializeEx(IN PCPPORT PortInformation,
//
// Disable interrupts
//
WRITE_REGISTER_ULONG(UART_PL011_CR, 0);
WRITE_REGISTER_ULONG((PULONG)UART_PL011_CR, 0);
//
// Set the baud rate
//
WRITE_REGISTER_ULONG(UART_PL011_IBRD, Divider);
WRITE_REGISTER_ULONG(UART_PL011_FBRD, Fraction);
WRITE_REGISTER_ULONG((PULONG)UART_PL011_IBRD, Divider);
WRITE_REGISTER_ULONG((PULONG)UART_PL011_FBRD, Fraction);
//
// Set 8 bits for data, 1 stop bit, no parity, FIFO enabled
//
WRITE_REGISTER_ULONG(UART_PL011_LCRH,
WRITE_REGISTER_ULONG((PULONG)UART_PL011_LCRH,
UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN);
//
// Clear and enable FIFO
//
WRITE_REGISTER_ULONG(UART_PL011_CR,
WRITE_REGISTER_ULONG((PULONG)UART_PL011_CR,
UART_PL011_CR_UARTEN |
UART_PL011_CR_TXE |
UART_PL011_CR_RXE);
@ -101,12 +101,12 @@ KdPortPutByteEx(IN PCPPORT PortInformation,
//
// Wait for ready
//
while ((READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_TXFF) != 0);
while ((READ_REGISTER_ULONG((PULONG)UART_PL01x_FR) & UART_PL01x_FR_TXFF) != 0);
//
// Send the character
//
WRITE_REGISTER_ULONG(UART_PL01x_DR, ByteToSend);
WRITE_REGISTER_ULONG((PULONG)UART_PL01x_DR, ByteToSend);
}
/* EOF */

9
reactos/ntoskrnl/kd64/kddata.c
View file

@ -46,7 +46,7 @@ VOID NTAPI RtlpBreakWithStatusInstruction(VOID);
#elif defined(_ARM_)
#define KPCR_SELF_PCR_OFFSET 0
#define KPCR_CURRENT_PRCB_OFFSET FIELD_OFFSET(KPCR, Prcb)
#define KPCR_CURRENT_PRCB_OFFSET FIELD_OFFSET(KIPCR, Prcb)
#define KPCR_CONTAINED_PRCB_OFFSET 0
#define KPCR_INITIAL_STACK_OFFSET FIELD_OFFSET(KPCR, InitialStack)
#define KPCR_STACK_LIMIT_OFFSET FIELD_OFFSET(KPCR, StackLimit)
@ -510,9 +510,16 @@ KDDEBUGGER_DATA64 KdDebuggerDataBlock =
KPCR_CONTAINED_PRCB_OFFSET,
0,
0,
#if defined(_M_ARM)
_WARN("KPCR_INITIAL_STACK_OFFSET, KPCR_STACK_LIMIT_OFFSET and KPRCB_PCR_PAGE_OFFSET not properly defined on ARM")
0,
0,
0,
#else
KPCR_INITIAL_STACK_OFFSET,
KPCR_STACK_LIMIT_OFFSET,
KPRCB_PCR_PAGE_OFFSET,
#endif
FIELD_OFFSET(KPRCB, ProcessorState.SpecialRegisters),
#if defined(_X86_)
//

44
reactos/ntoskrnl/ke/arm/cpu.c
View file

@ -67,10 +67,26 @@ KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState)
//
// Save some critical stuff we use
//
__debugbreak();
#if 0
ProcessorState->SpecialRegisters.ControlRegister = KeArmControlRegisterGet();
ProcessorState->SpecialRegisters.LockdownRegister = KeArmLockdownRegisterGet();
ProcessorState->SpecialRegisters.CacheRegister = KeArmCacheRegisterGet();
ProcessorState->SpecialRegisters.StatusRegister = KeArmStatusRegisterGet();
#endif
}
VOID
NTAPI
KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState)
{
__debugbreak();
#if 0
KeArmControlRegisterSet(ProcessorState->SpecialRegisters.ControlRegister);
KeArmLockdownRegisterSet(ProcessorState->SpecialRegisters.LockdownRegister);
KeArmCacheRegisterSet(ProcessorState->SpecialRegisters.CacheRegister);
KeArmStatusRegisterSet(ProcessorState->SpecialRegisters.StatusRegister);
#endif
}
BOOLEAN
@ -170,30 +186,14 @@ KeSaveStateForHibernate(IN PKPROCESSOR_STATE State)
KiSaveProcessorControlState(State);
}
/*
* @implemented
*/
NTSTATUS
VOID
NTAPI
KeSaveFloatingPointState(OUT PKFLOATING_SAVE Save)
KeFlushIoBuffers(
_In_ PMDL Mdl,
_In_ BOOLEAN ReadOperation,
_In_ BOOLEAN DmaOperation)
{
//
// Nothing to do on ARM
//
return STATUS_SUCCESS;
}
/*
* @implemented
*/
NTSTATUS
NTAPI
KeRestoreFloatingPointState(IN PKFLOATING_SAVE Save)
{
//
// Nothing to do on ARM
//
return STATUS_SUCCESS;
DbgBreakPoint();
}
/* SYSTEM CALLS NOT VALID ON THIS CPU *****************************************/

116
reactos/ntoskrnl/ke/arm/exp.c
View file

@ -9,7 +9,6 @@
/* INCLUDES *******************************************************************/
#include <ntoskrnl.h>
#include <internal/arm/ksarm.h>
#define NDEBUG
#include <debug.h>
@ -24,13 +23,13 @@ KeContextToTrapFrame(IN PCONTEXT Context,
IN KPROCESSOR_MODE PreviousMode)
{
KIRQL OldIrql;
//
// Do this at APC_LEVEL
//
OldIrql = KeGetCurrentIrql();
if (OldIrql < APC_LEVEL) KeRaiseIrql(APC_LEVEL, &OldIrql);
//
// Start with the Control flags
//
@ -39,30 +38,20 @@ KeContextToTrapFrame(IN PCONTEXT Context,
//
// So this basically means all the special stuff
//
if (PreviousMode == UserMode)
{
//
// ARM has register banks
//
TrapFrame->UserSp = Context->Sp;
TrapFrame->UserLr = Context->Lr;
}
else
{
//
// ARM has register banks
//
TrapFrame->SvcSp = Context->Sp;
TrapFrame->SvcLr = Context->Lr;
}
//
// ARM has register banks
//
TrapFrame->Sp = Context->Sp;
TrapFrame->Lr = Context->Lr;
//
// The rest is already in the right mode
//
TrapFrame->Pc = Context->Pc;
TrapFrame->Spsr = Context->Psr;
TrapFrame->Cpsr = Context->Cpsr;
}
//
// Now do the integers
//
@ -75,21 +64,21 @@ KeContextToTrapFrame(IN PCONTEXT Context,
TrapFrame->R1 = Context->R1;
TrapFrame->R2 = Context->R2;
TrapFrame->R3 = Context->R3;
TrapFrame->R4 = Context->R4;
TrapFrame->R5 = Context->R5;
TrapFrame->R6 = Context->R6;
TrapFrame->R7 = Context->R7;
TrapFrame->R8 = Context->R8;
TrapFrame->R0 = Context->R9;
TrapFrame->R10 = Context->R10;
TrapFrame->R11 = Context->R11;
ExceptionFrame->R4 = Context->R4;
ExceptionFrame->R5 = Context->R5;
ExceptionFrame->R6 = Context->R6;
ExceptionFrame->R7 = Context->R7;
ExceptionFrame->R8 = Context->R8;
ExceptionFrame->R9 = Context->R9;
ExceptionFrame->R10 = Context->R10;
ExceptionFrame->R11 = Context->R11;
TrapFrame->R12 = Context->R12;
}
//
// Restore IRQL
//
if (OldIrql < APC_LEVEL) KeLowerIrql(OldIrql);
if (OldIrql < APC_LEVEL) KeLowerIrql(OldIrql);
}
VOID
@ -99,13 +88,13 @@ KeTrapFrameToContext(IN PKTRAP_FRAME TrapFrame,
IN OUT PCONTEXT Context)
{
KIRQL OldIrql;
//
// Do this at APC_LEVEL
//
OldIrql = KeGetCurrentIrql();
if (OldIrql < APC_LEVEL) KeRaiseIrql(APC_LEVEL, &OldIrql);
//
// Start with the Control flags
//
@ -114,30 +103,20 @@ KeTrapFrameToContext(IN PKTRAP_FRAME TrapFrame,
//
// So this basically means all the special stuff
//
if (KiGetPreviousMode(TrapFrame) == UserMode)
{
//
// ARM has register banks
//
Context->Sp = TrapFrame->UserSp;
Context->Lr = TrapFrame->UserLr;
}
else
{
//
// ARM has register banks
//
Context->Sp = TrapFrame->SvcSp;
Context->Lr = TrapFrame->SvcLr;
}
//
// ARM has register banks
//
Context->Sp = TrapFrame->Sp;
Context->Lr = TrapFrame->Lr;
//
// The rest is already in the right mode
//
Context->Pc = TrapFrame->Pc;
Context->Psr = TrapFrame->Spsr;
Context->Cpsr = TrapFrame->Cpsr;
}
//
// Now do the integers
//
@ -150,21 +129,21 @@ KeTrapFrameToContext(IN PKTRAP_FRAME TrapFrame,
Context->R1 = TrapFrame->R1;
Context->R2 = TrapFrame->R2;
Context->R3 = TrapFrame->R3;
Context->R4 = TrapFrame->R4;
Context->R5 = TrapFrame->R5;
Context->R6 = TrapFrame->R6;
Context->R7 = TrapFrame->R7;
Context->R8 = TrapFrame->R8;
Context->R0 = TrapFrame->R9;
Context->R10 = TrapFrame->R10;
Context->R11 = TrapFrame->R11;
Context->R4 = ExceptionFrame->R4;
Context->R5 = ExceptionFrame->R5;
Context->R6 = ExceptionFrame->R6;
Context->R7 = ExceptionFrame->R7;
Context->R8 = ExceptionFrame->R8;
Context->R0 = ExceptionFrame->R9;
Context->R10 = ExceptionFrame->R10;
Context->R11 = ExceptionFrame->R11;
Context->R12 = TrapFrame->R12;
}
//
// Restore IRQL
//
if (OldIrql < APC_LEVEL) KeLowerIrql(OldIrql);
if (OldIrql < APC_LEVEL) KeLowerIrql(OldIrql);
}
VOID
@ -182,7 +161,7 @@ KiDispatchException(IN PEXCEPTION_RECORD ExceptionRecord,
/* Set the context flags */
Context.ContextFlags = CONTEXT_FULL;
/* Check if User Mode or if the kernel debugger is enabled */
if ((PreviousMode == UserMode) || (KeGetPcr()->KdVersionBlock))
{
@ -281,3 +260,12 @@ Handled:
PreviousMode);
return;
}
NTSTATUS
NTAPI
KeRaiseUserException(
_In_ NTSTATUS ExceptionCode)
{
ASSERT(FALSE);
return STATUS_NOT_IMPLEMENTED;
}

173
reactos/ntoskrnl/ke/arm/kiinit.c
View file

@ -12,6 +12,13 @@
#define NDEBUG
#include <debug.h>
VOID
NTAPI
KdPortPutByteEx(
PCPPORT PortInformation,
UCHAR ByteToSend
);
/* GLOBALS ********************************************************************/
KINTERRUPT KxUnexpectedInterrupt;
@ -44,15 +51,16 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
PKIPCR Pcr = (PKIPCR)KeGetPcr();
ULONG PageDirectory[2];
ULONG i;
/* Set the default NX policy (opt-in) */
SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN;
/* Initialize spinlocks and DPC data */
KiInitSpinLocks(Prcb, Number);
/* Set stack pointers */
Pcr->InitialStack = IdleStack;
//Pcr->InitialStack = IdleStack;
Pcr->Prcb.SpBase = IdleStack; // ???
/* Check if this is the Boot CPU */
if (!Number)
@ -64,22 +72,23 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
/* Copy the template code */
KxUnexpectedInterrupt.DispatchCode[i] = ((PULONG)KiInterruptTemplate)[i];
}
/* Set DMA coherency */
KiDmaIoCoherency = 0;
/* Sweep D-Cache */
HalSweepDcache();
/* Set boot-level flags */
KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_ARM;
KeFeatureBits = 0;
KeProcessorLevel = (USHORT)(Pcr->ProcessorId >> 8);
KeProcessorRevision = (USHORT)(Pcr->ProcessorId & 0xFF);
/// FIXME: just a wild guess
KeProcessorLevel = (USHORT)(Pcr->Prcb.ProcessorState.ArchState.Cp15_Cr0_CpuId >> 8);
KeProcessorRevision = (USHORT)(Pcr->Prcb.ProcessorState.ArchState.Cp15_Cr0_CpuId & 0xFF);
#if 0
/* Set the current MP Master KPRCB to the Boot PRCB */
Prcb->MultiThreadSetMaster = Prcb;
#endif
/* Lower to APC_LEVEL */
KeLowerIrql(APC_LEVEL);
@ -160,9 +169,9 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
LoaderBlock->Prcb = 0;
}
C_ASSERT((PKIPCR)KeGetPcr() == (PKIPCR)0xFFDFF000);
C_ASSERT((FIELD_OFFSET(KIPCR, FirstLevelDcacheSize) & 4) == 0);
C_ASSERT(sizeof(KIPCR) <= PAGE_SIZE);
//C_ASSERT((PKIPCR)KeGetPcr() == (PKIPCR)0xFFDFF000);
//C_ASSERT((FIELD_OFFSET(KIPCR, FirstLevelDcacheSize) & 4) == 0);
//C_ASSERT(sizeof(KIPCR) <= PAGE_SIZE);
VOID
NTAPI
@ -173,109 +182,127 @@ KiInitializePcr(IN ULONG ProcessorNumber,
IN PVOID InterruptStack)
{
ULONG i;
/* Set the Current Thread */
Pcr->PrcbData.CurrentThread = IdleThread;
Pcr->Prcb.CurrentThread = IdleThread;
/* Set pointers to ourselves */
Pcr->Self = (PKPCR)Pcr;
Pcr->Prcb = &Pcr->PrcbData;
Pcr->CurrentPrcb = &Pcr->Prcb;
/* Set the PCR Version */
Pcr->MajorVersion = PCR_MAJOR_VERSION;
Pcr->MinorVersion = PCR_MINOR_VERSION;
/* Set the PCRB Version */
Pcr->PrcbData.MajorVersion = 1;
Pcr->PrcbData.MinorVersion = 1;
Pcr->Prcb.MajorVersion = 1;
Pcr->Prcb.MinorVersion = 1;
/* Set the Build Type */
Pcr->PrcbData.BuildType = 0;
Pcr->Prcb.BuildType = 0;
#ifndef CONFIG_SMP
Pcr->PrcbData.BuildType |= PRCB_BUILD_UNIPROCESSOR;
Pcr->Prcb.BuildType |= PRCB_BUILD_UNIPROCESSOR;
#endif
#if DBG
Pcr->PrcbData.BuildType |= PRCB_BUILD_DEBUG;
Pcr->Prcb.BuildType |= PRCB_BUILD_DEBUG;
#endif
/* Set the Processor Number and current Processor Mask */
Pcr->PrcbData.Number = (UCHAR)ProcessorNumber;
Pcr->PrcbData.SetMember = 1 << ProcessorNumber;
Pcr->Prcb.Number = (UCHAR)ProcessorNumber;
Pcr->Prcb.SetMember = 1 << ProcessorNumber;
/* Set the PRCB for this Processor */
KiProcessorBlock[ProcessorNumber] = Pcr->Prcb;
KiProcessorBlock[ProcessorNumber] = Pcr->CurrentPrcb;
/* Start us out at PASSIVE_LEVEL */
Pcr->Irql = PASSIVE_LEVEL;
Pcr->CurrentIrql = PASSIVE_LEVEL;
/* Set the stacks */
Pcr->PanicStack = PanicStack;
Pcr->InterruptStack = InterruptStack;
Pcr->Prcb.PanicStackBase = (ULONG)PanicStack;
Pcr->Prcb.IsrStack = InterruptStack;
#if 0
/* Setup the processor set */
Pcr->PrcbData.MultiThreadProcessorSet = Pcr->PrcbData.SetMember;
Pcr->Prcb.MultiThreadProcessorSet = Pcr->Prcb.SetMember;
#endif
/* Copy cache information from the loader block */
Pcr->FirstLevelDcacheSize = KeLoaderBlock->u.Arm.FirstLevelDcacheSize;
Pcr->SecondLevelDcacheSize = KeLoaderBlock->u.Arm.SecondLevelDcacheSize;
Pcr->FirstLevelIcacheSize = KeLoaderBlock->u.Arm.FirstLevelIcacheSize;
Pcr->SecondLevelIcacheSize = KeLoaderBlock->u.Arm.SecondLevelIcacheSize;
Pcr->FirstLevelDcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelDcacheFillSize;
Pcr->SecondLevelDcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelDcacheFillSize;
Pcr->FirstLevelIcacheFillSize = KeLoaderBlock->u.Arm.FirstLevelIcacheFillSize;
Pcr->SecondLevelIcacheFillSize = KeLoaderBlock->u.Arm.SecondLevelIcacheFillSize;
Pcr->Prcb.Cache[FirstLevelDcache].Type = CacheData;
Pcr->Prcb.Cache[FirstLevelDcache].Level = 1;
Pcr->Prcb.Cache[FirstLevelDcache].Associativity = 0; // FIXME
Pcr->Prcb.Cache[FirstLevelDcache].LineSize = KeLoaderBlock->u.Arm.FirstLevelDcacheFillSize;
Pcr->Prcb.Cache[FirstLevelDcache].Size = KeLoaderBlock->u.Arm.FirstLevelDcacheSize;
Pcr->Prcb.Cache[SecondLevelDcache].Type = CacheData;
Pcr->Prcb.Cache[SecondLevelDcache].Level = 2;
Pcr->Prcb.Cache[SecondLevelDcache].Associativity = 0; // FIXME
Pcr->Prcb.Cache[SecondLevelDcache].LineSize = KeLoaderBlock->u.Arm.SecondLevelDcacheFillSize;
Pcr->Prcb.Cache[SecondLevelDcache].Size = KeLoaderBlock->u.Arm.SecondLevelDcacheSize;
Pcr->Prcb.Cache[FirstLevelIcache].Type = CacheInstruction;
Pcr->Prcb.Cache[FirstLevelIcache].Level = 1;
Pcr->Prcb.Cache[FirstLevelIcache].Associativity = 0; // FIXME
Pcr->Prcb.Cache[FirstLevelIcache].LineSize = KeLoaderBlock->u.Arm.FirstLevelIcacheFillSize;
Pcr->Prcb.Cache[FirstLevelIcache].Size = KeLoaderBlock->u.Arm.FirstLevelIcacheSize;
Pcr->Prcb.Cache[SecondLevelIcache].Type = CacheInstruction;
Pcr->Prcb.Cache[SecondLevelIcache].Level = 2;
Pcr->Prcb.Cache[SecondLevelIcache].Associativity = 0; // FIXME
Pcr->Prcb.Cache[SecondLevelIcache].LineSize = KeLoaderBlock->u.Arm.SecondLevelIcacheFillSize;
Pcr->Prcb.Cache[SecondLevelIcache].Size = KeLoaderBlock->u.Arm.SecondLevelIcacheSize;
/* Set global d-cache fill and alignment values */
if (!Pcr->SecondLevelDcacheSize)
if (Pcr->Prcb.Cache[SecondLevelDcache].Size == 0)
{
/* Use the first level */
Pcr->DcacheFillSize = Pcr->FirstLevelDcacheSize;
Pcr->Prcb.Cache[GlobalDcache] = Pcr->Prcb.Cache[FirstLevelDcache];
}
else
{
/* Use the second level */
Pcr->DcacheFillSize = Pcr->SecondLevelDcacheSize;
Pcr->Prcb.Cache[GlobalDcache] = Pcr->Prcb.Cache[SecondLevelDcache];
}
/* Set the alignment */
Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1;
//Pcr->DcacheAlignment = Pcr->DcacheFillSize - 1;
/* Set global i-cache fill and alignment values */
if (!Pcr->SecondLevelIcacheSize)
if (Pcr->Prcb.Cache[SecondLevelIcache].Size == 0)
{
/* Use the first level */
Pcr->IcacheFillSize = Pcr->FirstLevelIcacheSize;
Pcr->Prcb.Cache[GlobalIcache] = Pcr->Prcb.Cache[FirstLevelIcache];
}
else
{
/* Use the second level */
Pcr->IcacheFillSize = Pcr->SecondLevelIcacheSize;
Pcr->Prcb.Cache[GlobalIcache] = Pcr->Prcb.Cache[SecondLevelIcache];
}
/* Set the alignment */
Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1;
//Pcr->IcacheAlignment = Pcr->IcacheFillSize - 1;
/* Set processor information */
Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong;
//Pcr->ProcessorId = KeArmIdCodeRegisterGet().AsUlong;
/* Set all interrupt routines to unexpected interrupts as well */
for (i = 0; i < MAXIMUM_VECTOR; i++)
{
/* Point to the same template */
Pcr->InterruptRoutine[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode;
Pcr->Idt[i] = (PVOID)&KxUnexpectedInterrupt.DispatchCode;
}
/* Set default stall factor */
Pcr->StallScaleFactor = 50;
/* Setup software interrupts */
Pcr->InterruptRoutine[PASSIVE_LEVEL] = KiPassiveRelease;
Pcr->InterruptRoutine[APC_LEVEL] = KiApcInterrupt;
Pcr->InterruptRoutine[DISPATCH_LEVEL] = KiDispatchInterrupt;
Pcr->Idt[PASSIVE_LEVEL] = KiPassiveRelease;
Pcr->Idt[APC_LEVEL] = KiApcInterrupt;
Pcr->Idt[DISPATCH_LEVEL] = KiDispatchInterrupt;
#if 0
Pcr->ReservedVectors = (1 << PASSIVE_LEVEL) |
(1 << APC_LEVEL) |
(1 << DISPATCH_LEVEL) |
(1 << IPI_LEVEL);
#endif
}
VOID
@ -283,7 +310,7 @@ KiInitializeMachineType(VOID)
{
/* Detect ARM version */
KeIsArmV6 = KeArmIdCodeRegisterGet().Architecture >= 7;
/* Set the number of TLB entries and ASIDs */
KeNumberTbEntries = 64;
if (__ARMV6__)
@ -310,7 +337,7 @@ KiInitializeSystem(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
/* Flush the TLB */
KeFlushTb();
/* Save the loader block and get the current CPU */
KeLoaderBlock = LoaderBlock;
Cpu = KeNumberProcessors;
@ -327,7 +354,7 @@ KiInitializeSystem(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
/* Skip initial setup if this isn't the Boot CPU */
if (Cpu) goto AppCpuInit;
/* Initialize the PCR */
RtlZeroMemory(Pcr, PAGE_SIZE);
KiInitializePcr(Cpu,
@ -339,22 +366,20 @@ KiInitializeSystem(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
/* Now sweep caches */
HalSweepIcache();
HalSweepDcache();
/* Set us as the current process */
InitialThread->ApcState.Process = InitialProcess;
AppCpuInit:
/* Setup CPU-related fields */
Pcr->Number = Cpu;
Pcr->SetMember = 1 << Cpu;
Pcr->SetMemberCopy = 1 << Cpu;
Pcr->PrcbData.SetMember = 1 << Cpu;
Pcr->Prcb.Number = Cpu;
Pcr->Prcb.SetMember = 1 << Cpu;
/* Initialize the Processor with HAL */
HalInitializeProcessor(Cpu, KeLoaderBlock);
/* Set active processors */
KeActiveProcessors |= Pcr->SetMember;
KeActiveProcessors |= Pcr->Prcb.SetMember;
KeNumberProcessors++;
/* Check if this is the boot CPU */
@ -369,12 +394,12 @@ AppCpuInit:
/* Raise to HIGH_LEVEL */
KfRaiseIrql(HIGH_LEVEL);
/* Set the exception address to high */
ControlRegister = KeArmControlRegisterGet();
ControlRegister.HighVectors = TRUE;
KeArmControlRegisterSet(ControlRegister);
/* Setup the exception vector table */
RtlCopyMemory((PVOID)0xFFFF0000, &KiArmVectorTable, 14 * sizeof(PVOID));
@ -382,8 +407,8 @@ AppCpuInit:
KiInitializeKernel((PKPROCESS)LoaderBlock->Process,
(PKTHREAD)LoaderBlock->Thread,
(PVOID)LoaderBlock->KernelStack,
Pcr->Prcb,
Pcr->Prcb->Number,
&Pcr->Prcb,
Pcr->Prcb.Number,
KeLoaderBlock);
/* Set the priority of this thread to 0 */
@ -412,7 +437,7 @@ DbgPrintEarly(const char *fmt, ...)
va_start(args, fmt);
i = vsprintf(Buffer, fmt, args);
va_end(args);
/* Output the message */
while (*String != 0)
{
@ -423,6 +448,6 @@ DbgPrintEarly(const char *fmt, ...)
KdPortPutByteEx(NULL, *String);
String++;
}
return STATUS_SUCCESS;
}

48
reactos/ntoskrnl/ke/arm/thrdini.c
View file

@ -70,19 +70,19 @@ KiInitializeContextThread(IN PKTHREAD Thread,
PKUINIT_FRAME InitFrame;
InitFrame = (PKUINIT_FRAME)((ULONG_PTR)Thread->InitialStack -
sizeof(KUINIT_FRAME));
//
// Setup the Trap Frame and Exception frame
//
TrapFrame = &InitFrame->TrapFrame;
ExceptionFrame = &InitFrame->ExceptionFrame;
///
// Zero out the trap frame and exception frame
//
RtlZeroMemory(TrapFrame, sizeof(KTRAP_FRAME));
RtlZeroMemory(ExceptionFrame, sizeof(KEXCEPTION_FRAME));
//
// Set up a trap frame from the context
//
@ -97,12 +97,12 @@ KiInitializeContextThread(IN PKTHREAD Thread,
//
//TrapFrame->PreviousMode = UserMode;
Thread->PreviousMode = UserMode;
//
// Clear the return address
//
ExceptionFrame->Lr = 0;
ExceptionFrame->Return = 0;
//
// Context switch frame to setup below
//
@ -116,22 +116,22 @@ KiInitializeContextThread(IN PKTHREAD Thread,
PKKINIT_FRAME InitFrame;
InitFrame = (PKKINIT_FRAME)((ULONG_PTR)Thread->InitialStack -
sizeof(KKINIT_FRAME));
//
// Set the previous mode as kernel
//
Thread->PreviousMode = KernelMode;
//
// Context switch frame to setup below
//
CtxSwitchFrame = &InitFrame->CtxSwitchFrame;
}
//
// Now setup the context switch frame
//
CtxSwitchFrame->Lr = (ULONG)KiThreadStartup;
CtxSwitchFrame->Return = (ULONG)KiThreadStartup;
CtxSwitchFrame->R11 = (ULONG)(ExceptionFrame ? ExceptionFrame : CtxSwitchFrame);
//
@ -141,7 +141,7 @@ KiInitializeContextThread(IN PKTHREAD Thread,
CtxSwitchFrame->R5 = (ULONG)StartContext;
CtxSwitchFrame->R6 = (ULONG)StartRoutine;
CtxSwitchFrame->R7 = (ULONG)SystemRoutine;
//
// Save back the new value of the kernel stack
//
@ -221,7 +221,7 @@ KiSwapContextExit(IN PKTHREAD OldThread,
ARM_TTB_REGISTER TtbRegister;
/* We are on the new thread stack now */
NewThread = Pcr->PrcbData.CurrentThread;
NewThread = Pcr->Prcb.CurrentThread;
/* Now we are the new thread. Check if it's in a new process */
OldProcess = OldThread->ApcState.Process;
@ -236,11 +236,8 @@ KiSwapContextExit(IN PKTHREAD OldThread,
/* Increase thread context switches */
NewThread->ContextSwitches++;
/* Load data from switch frame */
Pcr->NtTib.ExceptionList = SwitchFrame->ExceptionList;
/* DPCs shouldn't be active */
if (Pcr->PrcbData.DpcRoutineActive)
if (Pcr->Prcb.DpcRoutineActive)
{
/* Crash the machine */
KeBugCheckEx(ATTEMPTED_SWITCH_FROM_DPC,
@ -276,20 +273,21 @@ KiSwapContextEntry(IN PKSWITCHFRAME SwitchFrame,
/* Save APC bypass disable */
SwitchFrame->ApcBypassDisable = OldThreadAndApcFlag & 3;
SwitchFrame->ExceptionList = Pcr->NtTib.ExceptionList;
/* Increase context switch count and check if tracing is enabled */
Pcr->ContextSwitches++;
Pcr->Prcb.KeContextSwitches++;
#if 0
if (Pcr->PerfGlobalGroupMask)
{
/* We don't support this yet on x86 either */
DPRINT1("WMI Tracing not supported\n");
ASSERT(FALSE);
}
#endif // 0
/* Get thread pointers */
OldThread = (PKTHREAD)(OldThreadAndApcFlag & ~3);
NewThread = Pcr->PrcbData.CurrentThread;
NewThread = Pcr->Prcb.CurrentThread;
/* Get the old thread and set its kernel stack */
OldThread->KernelStack = SwitchFrame;
@ -303,8 +301,7 @@ NTAPI
KiDispatchInterrupt(VOID)
{
PKIPCR Pcr = (PKIPCR)KeGetPcr();
PKPRCB Prcb = &Pcr->PrcbData;
PVOID OldHandler;
PKPRCB Prcb = &Pcr->Prcb;
PKTHREAD NewThread, OldThread;
/* Disable interrupts */
@ -315,17 +312,10 @@ KiDispatchInterrupt(VOID)
(Prcb->TimerRequest) ||
(Prcb->DeferredReadyListHead.Next))
{
/* Switch to safe execution context */
OldHandler = Pcr->NtTib.ExceptionList;
Pcr->NtTib.ExceptionList = EXCEPTION_CHAIN_END;
/* Retire DPCs while under the DPC stack */
//KiRetireDpcListInDpcStack(Prcb, Prcb->DpcStack);
// FIXME!!! //
KiRetireDpcList(Prcb);
/* Restore context */
Pcr->NtTib.ExceptionList = OldHandler;
}
/* Re-enable interrupts */
@ -339,7 +329,7 @@ KiDispatchInterrupt(VOID)
KiQuantumEnd();
}
else if (Prcb->NextThread)
{
{
/* Capture current thread data */
OldThread = Prcb->CurrentThread;
NewThread = Prcb->NextThread;

150
reactos/ntoskrnl/ke/arm/trapc.c
View file

@ -9,7 +9,6 @@
/* INCLUDES *******************************************************************/
#include <ntoskrnl.h>
#include <internal/arm/ksarm.h>
#define NDEBUG
#include <debug.h>
@ -22,13 +21,13 @@ KiIdleLoop(VOID)
PKPCR Pcr = (PKPCR)KeGetPcr();
PKPRCB Prcb = Pcr->Prcb;
PKTHREAD OldThread, NewThread;
//
// Loop forever... that's why this is an idle loop
//
DPRINT1("[IDLE LOOP]\n");
while (TRUE);
while (TRUE)
{
//
@ -36,7 +35,7 @@ KiIdleLoop(VOID)
//
_disable();
_enable();
//
// Check if there's DPC work to do
//
@ -48,13 +47,13 @@ KiIdleLoop(VOID)
// Clear the pending interrupt
//
HalClearSoftwareInterrupt(DISPATCH_LEVEL);
//
// Retire DPCs
//
KiRetireDpcList(Prcb);
}
//
// Check if there's a thread to schedule
//
@ -64,15 +63,15 @@ KiIdleLoop(VOID)
// Out with the old, in with the new...
//
OldThread = Prcb->CurrentThread;
NewThread = Prcb->NextThread;
NewThread = Prcb->NextThread;
Prcb->CurrentThread = NewThread;
Prcb->NextThread = NULL;
//
// Update thread state
//
NewThread->State = Running;
//
// Swap to the new thread
// On ARM we call KiSwapContext instead of KiSwapContextInternal,
@ -101,19 +100,19 @@ KiSwapProcess(IN PKPROCESS NewProcess,
DPRINT1("Swapping from: %p (%16s) to %p (%16s)\n",
OldProcess, ((PEPROCESS)OldProcess)->ImageFileName,
NewProcess, ((PEPROCESS)NewProcess)->ImageFileName);
//
// Update the page directory base
//
TtbRegister.AsUlong = NewProcess->DirectoryTableBase[0];
ASSERT(TtbRegister.Reserved == 0);
KeArmTranslationTableRegisterSet(TtbRegister);
//
// FIXME: Flush the TLB
//
DPRINT1("Survived!\n");
while (TRUE);
}
@ -126,15 +125,15 @@ KiSwapContextInternal(IN PKTHREAD OldThread,
PKIPCR Pcr = (PKIPCR)KeGetPcr();
PKPRCB Prcb = Pcr->Prcb;
PKPROCESS OldProcess, NewProcess;
DPRINT1("SWAP\n");
while (TRUE);
//
// Increase context switch count
//
Pcr->ContextSwitches++;
//
// Check if WMI tracing is enabled
//
@ -146,7 +145,7 @@ KiSwapContextInternal(IN PKTHREAD OldThread,
DPRINT1("WMI Tracing not supported\n");
ASSERT(FALSE);
}
//
// Check if the processes are also different
//
@ -167,7 +166,7 @@ KiSwapContextInternal(IN PKTHREAD OldThread,
ASSERT(FALSE);
}
}
//
// Increase thread context switches
//
@ -199,7 +198,7 @@ KiSwapContextInternal(IN PKTHREAD OldThread,
(ULONG_PTR)OldThread->InitialStack,
0);
}
//
// Kernel APCs may be pending
//
@ -217,7 +216,7 @@ KiSwapContextInternal(IN PKTHREAD OldThread,
return TRUE;
}
}
//
// Return
//
@ -231,20 +230,20 @@ KiApcInterrupt(VOID)
KPROCESSOR_MODE PreviousMode;
KEXCEPTION_FRAME ExceptionFrame;
PKTRAP_FRAME TrapFrame = KeGetCurrentThread()->TrapFrame;
DPRINT1("[APC TRAP]\n");
while (TRUE);
//
// Isolate previous mode
//
PreviousMode = KiGetPreviousMode(TrapFrame);
//
// FIXME-USER: Handle APC interrupt while in user-mode
//
if (PreviousMode == UserMode) ASSERT(FALSE);
//
// Disable interrupts
//
@ -254,12 +253,12 @@ KiApcInterrupt(VOID)
// Clear APC interrupt
//
HalClearSoftwareInterrupt(APC_LEVEL);
//
// Re-enable interrupts
//
_enable();
//
// Deliver APCs
//
@ -273,17 +272,17 @@ KiDispatchInterrupt(VOID)
PKIPCR Pcr;
PKPRCB Prcb;
PKTHREAD NewThread, OldThread;
DPRINT1("[DPC TRAP]\n");
while (TRUE);
//
// Get the PCR and disable interrupts
//
Pcr = (PKIPCR)KeGetPcr();
Prcb = Pcr->Prcb;
_disable();
//
//Check if we have to deliver DPCs, timers, or deferred threads
//
@ -296,12 +295,12 @@ KiDispatchInterrupt(VOID)
//
KiRetireDpcList(Prcb);
}
//
// Re-enable interrupts
//
_enable();
//
// Check for quantum end
//
@ -314,12 +313,12 @@ KiDispatchInterrupt(VOID)
KiQuantumEnd();
return;
}
//
// Check if we have a thread to swap to
//
if (Prcb->NextThread)
{
{
//
// Next is now current
//
@ -327,18 +326,18 @@ KiDispatchInterrupt(VOID)
NewThread = Prcb->NextThread;
Prcb->CurrentThread = NewThread;
Prcb->NextThread = NULL;
//
// Update thread states
//
NewThread->State = Running;
OldThread->WaitReason = WrDispatchInt;
//
// Make the old thread ready
//
KxQueueReadyThread(OldThread, Prcb);
//
// Swap to the new thread
// On ARM we call KiSwapContext instead of KiSwapContextInternal,
@ -355,23 +354,23 @@ KiInterruptHandler(IN PKTRAP_FRAME TrapFrame,
IN ULONG Reserved)
{
KIRQL OldIrql, Irql;
ULONG InterruptCause, InterruptMask;
ULONG InterruptCause;//, InterruptMask;
PKIPCR Pcr;
PKTRAP_FRAME OldTrapFrame;
ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00);
ASSERT(TrapFrame->Reserved == 0xBADB0D00);
//
// Increment interrupt count
//
Pcr = (PKIPCR)KeGetPcr();
Pcr->Prcb->InterruptCount++;
Pcr->Prcb.InterruptCount++;
//
// Get the old IRQL
//
OldIrql = KeGetCurrentIrql();
TrapFrame->OldIrql = OldIrql;
TrapFrame->PreviousIrql = OldIrql;
//
// Get the interrupt source
//
@ -381,14 +380,17 @@ KiInterruptHandler(IN PKTRAP_FRAME TrapFrame,
//
// Get the new IRQL and Interrupt Mask
//
Irql = Pcr->IrqlMask[InterruptCause];
InterruptMask = Pcr->IrqlTable[Irql];
/// FIXME: use a global table in ntoskrnl instead of HAL?
//Irql = Pcr->IrqlMask[InterruptCause];
//InterruptMask = Pcr->IrqlTable[Irql];
Irql = 0;
__debugbreak();
//
// Raise to the new IRQL
//
KfRaiseIrql(Irql);
//
// The clock ISR wants the trap frame as a parameter
//
@ -399,7 +401,7 @@ KiInterruptHandler(IN PKTRAP_FRAME TrapFrame,
// Check if this interrupt is at DISPATCH or higher
//
if (Irql > DISPATCH_LEVEL)
{
{
//
// FIXME-TODO: Switch to interrupt stack
//
@ -417,11 +419,13 @@ KiInterruptHandler(IN PKTRAP_FRAME TrapFrame,
//
// Call the registered interrupt routine
//
Pcr->InterruptRoutine[Irql]();
/// FIXME: this should probably go into a table in ntoskrnl
//Pcr->InterruptRoutine[Irql]();
__debugbreak();
ASSERT(KeGetCurrentThread()->TrapFrame == TrapFrame);
KeGetCurrentThread()->TrapFrame = OldTrapFrame;
// DPRINT1("[ISR RETURN]\n");
//
// Restore IRQL and interrupts
//
@ -433,15 +437,15 @@ NTSTATUS
KiPrefetchAbortHandler(IN PKTRAP_FRAME TrapFrame)
{
PVOID Address = (PVOID)KeArmFaultAddressRegisterGet();
ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00);
ASSERT(TrapFrame->Reserved == 0xBADB0D00);
ULONG Instruction = *(PULONG)TrapFrame->Pc;
ULONG DebugType, Parameter0;
EXCEPTION_RECORD ExceptionRecord;
DPRINT1("[PREFETCH ABORT] (%x) @ %p/%p/%p\n",
KeArmInstructionFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc);
KeArmInstructionFaultStatusRegisterGet(), Address, TrapFrame->Lr, TrapFrame->Pc);
while (TRUE);
//
// What we *SHOULD* do is look at the instruction fault status register
// and see if it's equal to 2 (debug trap). Unfortunately QEMU doesn't seem
@ -469,7 +473,7 @@ KiPrefetchAbortHandler(IN PKTRAP_FRAME TrapFrame)
//
Parameter0 = STATUS_SUCCESS;
}
//
// Build the exception record
//
@ -478,14 +482,14 @@ KiPrefetchAbortHandler(IN PKTRAP_FRAME TrapFrame)
ExceptionRecord.ExceptionRecord = NULL;
ExceptionRecord.ExceptionAddress = (PVOID)TrapFrame->Pc;
ExceptionRecord.NumberParameters = 3;
//
// Build the parameters
//
ExceptionRecord.ExceptionInformation[0] = Parameter0;
ExceptionRecord.ExceptionInformation[1] = TrapFrame->R1;
ExceptionRecord.ExceptionInformation[2] = TrapFrame->R2;
//
// Dispatch the exception
//
@ -500,7 +504,7 @@ KiPrefetchAbortHandler(IN PKTRAP_FRAME TrapFrame)
//
return STATUS_SUCCESS;
}
//
// Unhandled
//
@ -514,12 +518,12 @@ KiDataAbortHandler(IN PKTRAP_FRAME TrapFrame)
{
NTSTATUS Status;
PVOID Address = (PVOID)KeArmFaultAddressRegisterGet();
ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00);
ASSERT(TrapFrame->Reserved == 0xBADB0D00);
DPRINT1("[ABORT] (%x) @ %p/%p/%p\n",
KeArmFaultStatusRegisterGet(), Address, TrapFrame->SvcLr, TrapFrame->Pc);
KeArmFaultStatusRegisterGet(), Address, TrapFrame->Lr, TrapFrame->Pc);
while (TRUE);
//
// Check if this is a page fault
//
@ -546,33 +550,33 @@ KiSoftwareInterruptHandler(IN PKTRAP_FRAME TrapFrame)
PKTHREAD Thread;
KPROCESSOR_MODE PreviousMode;
ULONG Instruction;
ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00);
DPRINT1("[SWI] @ %p/%p\n", TrapFrame->SvcLr, TrapFrame->Pc);
ASSERT(TrapFrame->Reserved == 0xBADB0D00);
DPRINT1("[SWI] @ %p/%p\n", TrapFrame->Lr, TrapFrame->Pc);
while (TRUE);
//
// Get the current thread
//
Thread = KeGetCurrentThread();
//
// Isolate previous mode
//
PreviousMode = KiGetPreviousMode(TrapFrame);
//
// Save old previous mode
//
TrapFrame->PreviousMode = PreviousMode;
TrapFrame->PreviousTrapFrame = (ULONG_PTR)Thread->TrapFrame;
TrapFrame->TrapFrame = (ULONG_PTR)Thread->TrapFrame;
//
// Save previous mode and trap frame
//
Thread->TrapFrame = TrapFrame;
Thread->PreviousMode = PreviousMode;
//
// Read the opcode
//
@ -587,12 +591,12 @@ KiSoftwareInterruptHandler(IN PKTRAP_FRAME TrapFrame)
NTSTATUS
KiUndefinedExceptionHandler(IN PKTRAP_FRAME TrapFrame)
{
ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00);
ASSERT(TrapFrame->Reserved == 0xBADB0D00);
//
// This should never happen
//
DPRINT1("[UNDEF] @ %p/%p\n", TrapFrame->SvcLr, TrapFrame->Pc);
DPRINT1("[UNDEF] @ %p/%p\n", TrapFrame->Lr, TrapFrame->Pc);
UNIMPLEMENTED;
ASSERT(FALSE);
return STATUS_SUCCESS;

88
reactos/ntoskrnl/ke/arm/usercall.c
View file

@ -9,7 +9,6 @@
/* INCLUDES *******************************************************************/
#include <ntoskrnl.h>
#include <internal/arm/ksarm.h>
#define NDEBUG
#include <debug.h>
@ -92,20 +91,20 @@ KiSystemService(IN PKTHREAD Thread,
PVOID* Argument;
PVOID Arguments[0x11]; // Maximum 17 arguments
KIRQL OldIrql;
ASSERT(TrapFrame->DbgArgMark == 0xBADB0D00);
ASSERT(TrapFrame->Reserved == 0xBADB0D00);
//
// Increase count of system calls
//
Pcr = (PKPCR)KeGetPcr();
Pcr->Prcb->KeSystemCalls++;
Pcr = KeGetPcr();
Pcr->CurrentPrcb->KeSystemCalls++;
//
// Get the system call ID
//
Id = Instruction & 0xFFFFF;
//DPRINT1("[SWI] (%x) %p (%d) \n", Id, Thread, Thread->PreviousMode);
//
// Get the descriptor table
//
@ -113,7 +112,7 @@ KiSystemService(IN PKTHREAD Thread,
Offset = ((Id >> SERVICE_TABLE_SHIFT) & SERVICE_TABLE_MASK);
ServiceTable += Offset;
DescriptorTable = (PVOID)ServiceTable;
//
// Get the service call number and validate it
//
@ -126,12 +125,12 @@ KiSystemService(IN PKTHREAD Thread,
UNIMPLEMENTED;
ASSERT(FALSE);
}
//
// Save the function responsible for handling this system call
//
SystemCall = (PVOID)DescriptorTable->Base[Number];
//
// Check if this is a GUI call
//
@ -143,13 +142,13 @@ KiSystemService(IN PKTHREAD Thread,
UNIMPLEMENTED;
ASSERT(FALSE);
}
//
// Check how many arguments this system call takes
//
ArgumentCount = DescriptorTable->Number[Number] / 4;
ASSERT(ArgumentCount <= 17);
//
// Copy the register-arguments first
// First four arguments are in a1, a2, a3, a4
@ -163,7 +162,7 @@ KiSystemService(IN PKTHREAD Thread,
Arguments[i] = *Argument;
Argument++;
}
//
// If more than four, we'll have some on the user stack
//
@ -178,7 +177,7 @@ KiSystemService(IN PKTHREAD Thread,
// FIXME-USER: Validate the user stack
//
ASSERT(FALSE);
Argument = (PVOID*)TrapFrame->UserSp;
Argument = (PVOID*)TrapFrame->Sp;
}
else
{
@ -200,18 +199,18 @@ KiSystemService(IN PKTHREAD Thread,
Argument++;
}
}
//
// We can safely enable interrupts here
//
_enable();
//
// Do the system call and save result in EAX
//
TrapFrame->R0 = KiSyscallHandlers[ArgumentCount]((PVOID)SystemCall,
(PVOID)Arguments);
//
// Check if this was a user call
//
@ -226,9 +225,9 @@ KiSystemService(IN PKTHREAD Thread,
//
// Forcibly put us in a sane state
//
KeGetPcr()->Irql = 0;
KeGetPcr()->CurrentIrql = 0;
_disable();
//
// Fail
//
@ -238,7 +237,7 @@ KiSystemService(IN PKTHREAD Thread,
0,
0);
}
//
// Make sure we're not attached and that APCs are not disabled
//
@ -255,11 +254,11 @@ KiSystemService(IN PKTHREAD Thread,
0);
}
}
//
// Restore the old trap frame
//
Thread->TrapFrame = (PKTRAP_FRAME)TrapFrame->PreviousTrapFrame;
Thread->TrapFrame = KiGetLinkedTrapFrame(TrapFrame);
}
VOID
@ -275,19 +274,19 @@ KiInitializeUserApc(IN PKEXCEPTION_FRAME ExceptionFrame,
ULONG_PTR Stack;
ULONG ContextLength;
DPRINT1("User APC: %p %p %p\n", NormalContext, SystemArgument1, SystemArgument2);
//
// Build the user mode context
//
Context.ContextFlags = CONTEXT_FULL;
KeTrapFrameToContext(TrapFrame, ExceptionFrame, &Context);
//
// Setup the context on the user stack
//
ContextLength = sizeof(CONTEXT);
Stack = (ULONG_PTR)(Context.Sp & ~7) - ContextLength;
//
// Make sure the stack is valid, and copy the context
//
@ -301,7 +300,40 @@ KiInitializeUserApc(IN PKEXCEPTION_FRAME ExceptionFrame,
TrapFrame->R1 = (ULONG)SystemArgument1;
TrapFrame->R2 = (ULONG)SystemArgument2;
TrapFrame->R3 = (ULONG)NormalRoutine;
TrapFrame->R8 = Stack;
TrapFrame->UserSp = Stack;
TrapFrame->UserLr = (ULONG)KeUserApcDispatcher;
TrapFrame->Sp = Stack;
TrapFrame->Lr = (ULONG)KeUserApcDispatcher;
}
NTSTATUS
NTAPI
KeUserModeCallback(IN ULONG RoutineIndex,
IN PVOID Argument,
IN ULONG ArgumentLength,
OUT PVOID *Result,
OUT PULONG ResultLength)
{
NT_ASSERT(FALSE);
return STATUS_NOT_IMPLEMENTED;
}
NTSTATUS
NTAPI
KiCallUserMode(
IN PVOID *OutputBuffer,
IN PULONG OutputLength)
{
NT_ASSERT(FALSE);
return STATUS_NOT_IMPLEMENTED;
}
NTSTATUS
NTAPI
NtCallbackReturn(
_In_ PVOID Result,
_In_ ULONG ResultLength,
_In_ NTSTATUS CallbackStatus)
{
NT_ASSERT(FALSE);
return STATUS_NOT_IMPLEMENTED;
}

4
reactos/ntoskrnl/ke/ipi.c
View file

@ -167,6 +167,9 @@ KiIpiServiceRoutine(IN PKTRAP_FRAME TrapFrame,
if (InterlockedBitTestAndReset((PLONG)&Prcb->IpiFrozen, IPI_SYNCH_REQUEST))
{
#ifdef _M_ARM
DbgBreakPoint();
#else
(void)InterlockedDecrementUL(&Prcb->SignalDone->CurrentPacket[1]);
if (InterlockedCompareExchangeUL(&Prcb->SignalDone->CurrentPacket[2], 0, 0))
{
@ -179,6 +182,7 @@ KiIpiServiceRoutine(IN PKTRAP_FRAME TrapFrame,
while (0 != InterlockedCompareExchangeUL(&Prcb->SignalDone->TargetSet, 0, 0));
}
(void)InterlockedExchangePointer((PVOID*)&Prcb->SignalDone, NULL);
#endif // _M_ARM
}
#endif
return TRUE;

5
reactos/ntoskrnl/ke/thrdobj.c
View file

@ -530,7 +530,12 @@ KeStartThread(IN OUT PKTHREAD Thread)
NodePrcb = KiProcessorBlock[Process->ThreadSeed];
/* Calculate affinity mask */
#ifdef _M_ARM
DbgBreakPoint();
Set = 0;
#else
Set = ~NodePrcb->MultiThreadProcessorSet;
#endif
Mask = (ULONG)(Node->ProcessorMask & Process->Affinity);
Set &= Mask;
if (Set) Mask = Set;

2
reactos/ntoskrnl/ke/thrdschd.c
View file

@ -725,7 +725,7 @@ KiSetAffinityThread(IN PKTHREAD Thread,
#elif _M_AMD64
#define KiGetCurrentReadySummary() __readgsdword(FIELD_OFFSET(KIPCR, Prcb.ReadySummary))
#else
#error Implement me!
#define KiGetCurrentReadySummary() KeGetCurrentPrcb()->ReadySummary
#endif
/*

4
reactos/ntoskrnl/mm/ARM3/pagfault.c
View file

@ -1555,6 +1555,10 @@ MmArmAccessFault(IN BOOLEAN StoreInstruction,
DbgPrint("MM:***RIP %p, EFL %p\n", TrapFrame->Rip, TrapFrame->EFlags);
DbgPrint("MM:***RAX %p, RCX %p RDX %p\n", TrapFrame->Rax, TrapFrame->Rcx, TrapFrame->Rdx);
DbgPrint("MM:***RBX %p, RSI %p RDI %p\n", TrapFrame->Rbx, TrapFrame->Rsi, TrapFrame->Rdi);
#elif defined(_M_ARM)
DbgPrint("MM:***PC %p\n", TrapFrame->Pc);
DbgPrint("MM:***R0 %p, R1 %p R2 %p, R3 %p\n", TrapFrame->R0, TrapFrame->R1, TrapFrame->R2, TrapFrame->R3);
DbgPrint("MM:***R11 %p, R12 %p SP %p, LR %p\n", TrapFrame->R11, TrapFrame->R12, TrapFrame->Sp, TrapFrame->Lr);
#endif
}

30
reactos/ntoskrnl/mm/arm/page.c
View file

@ -117,6 +117,10 @@ MMPTE DemandZeroPte = {.u.Long = (MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BI
/* Template PTE for prototype page */
MMPTE PrototypePte = {.u.Long = (MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS) | PTE_PROTOTYPE | (MI_PTE_LOOKUP_NEEDED << PAGE_SHIFT)};
MMPTE ValidKernelPteLocal = {{0}};
MMPDE ValidKernelPdeLocal = {{0}};
MMPTE MmDecommittedPte = {{0}};
/* PRIVATE FUNCTIONS **********************************************************/
VOID
@ -290,3 +294,29 @@ MmInitGlobalKernelPageDirectory(VOID)
}
}
VOID
NTAPI
MmGetPageFileMapping(
PEPROCESS Process,
PVOID Address,
SWAPENTRY* SwapEntry)
{
NT_ASSERT(FALSE);
}
BOOLEAN
NTAPI
MmIsDisabledPage(PEPROCESS Process, PVOID Address)
{
NT_ASSERT(FALSE);
return FALSE;
}
VOID
NTAPI
INIT_FUNCTION
MiInitializeSessionSpaceLayout(VOID)
{
NT_ASSERT(FALSE);
}

2
reactos/ntoskrnl/rtl/libsupp.c
View file

@ -506,7 +506,7 @@ RtlWalkFrameChain(OUT PVOID *Callers,
#endif
#ifdef _AMD64_
#if defined(_M_AMD64) || defined(_M_ARM)
VOID
NTAPI
RtlpGetStackLimits(