mirror of
https://github.com/reactos/reactos.git
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[NTOSKRNL]
- Cleanup amd64 mm.h header - Call MiScanMemoryDescriptors earlier, since it doesn't depend on anything except the loader block. - MiComputeColorInformation() and the calculation of the pfn database size are portable, so move them out of MiInitMachineDependent svn path=/trunk/; revision=53838
This commit is contained in:
Timo Kreuzer
parent
62b3a707c7
commit
adaa2b8e63
3 changed files with 115 additions and 145 deletions
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@ -1,16 +1,10 @@
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/*
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* Lowlevel memory managment definitions
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* kernel internal memory managment definitions for amd64
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*/
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#pragma once
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#define _MI_PAGING_LEVELS 4
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/* Helper macros */
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#define PAGE_MASK(x) ((x)&(~0xfff))
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#define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
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/* Memory layout base addresses */
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#define MI_LOWEST_VAD_ADDRESS (PVOID)0x000000007FF00000ULL
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#define MI_HIGHEST_USER_ADDRESS (PVOID)0x000007FFFFFEFFFFULL
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#define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL
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#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL
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@ -28,42 +22,106 @@
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#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
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#define MI_SYSTEM_CACHE_WS_START (PVOID)0xFFFFF78000001000ULL // CHECKME
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#define MI_LOWEST_VAD_ADDRESS (PVOID)0x000000007FF00000ULL
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#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
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#define MM_SYSTEM_RANGE_START_WOW64 0x80000000
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#define MI_SYSTEM_PTE_END (PVOID)((ULONG64)MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
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#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE)
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#define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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#define MI_MAPPING_RANGE_START (ULONG64)HYPER_SPACE
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
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/* Memory sizes */
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
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#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024)
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#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024)
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#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024)
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#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024)
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#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
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MI_SESSION_POOL_SIZE + \
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
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#define MI_NUMBER_SYSTEM_PTES 22000
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
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#define MI_MIN_SECONDARY_COLORS 8
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#define MI_SECONDARY_COLORS 64
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#define MI_MAX_SECONDARY_COLORS 1024
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#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
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#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
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#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
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#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024)
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#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024)
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#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024)
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#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024)
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#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
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MI_SESSION_POOL_SIZE + \
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MI_MIN_SECONDARY_COLORS 8
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#define MI_SECONDARY_COLORS 64
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#define MI_MAX_SECONDARY_COLORS 1024
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/* Misc constants */
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#define _MI_PAGING_LEVELS 4
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#define MI_NUMBER_SYSTEM_PTES 22000
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define NR_SECTION_PAGE_TABLES 1024
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#define NR_SECTION_PAGE_ENTRIES 1024
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + PAGE_SIZE)
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#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + PAGE_SIZE)
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#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + PAGE_SIZE)
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/* FIXME - different architectures have different cache line sizes... */
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#define MM_CACHE_LINE_SIZE 32
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#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
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#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
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#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
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/* Helper macros */
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#define PAGE_MASK(x) ((x)&(~0xfff))
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#define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
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#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
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#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
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#define MM_HIGHEST_VAD_ADDRESS \
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(PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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#define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
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#define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
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#define ADDR_TO_PTE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
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#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
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#define MM_SYSTEM_RANGE_START_WOW64 0x80000000
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#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
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#define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
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#define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
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#define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
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#define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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// FIXME, only copied from x86
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#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
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#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
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#define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
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#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
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#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
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#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
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#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
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#if !defined(CONFIG_SMP)
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
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#else
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
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#endif
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#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
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#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
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#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
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#if !defined(CONFIG_SMP)
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
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#else
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
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#endif
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// FIXME!!!
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#define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
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((x) / (4*1024*1024))
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#define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
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((((x)) % (4*1024*1024)) / (4*1024))
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//#define TEB_BASE 0x7FFDE000
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/* On x86, these two are the same */
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#define MMPDE MMPTE
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#define PMMPDE PMMPTE
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PULONG64
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FORCEINLINE
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@ -151,17 +209,6 @@ MiIsPdeForAddressValid(PVOID Address)
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#define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
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#define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
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#define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
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#define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
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#define ADDR_TO_PTE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
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#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
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#define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
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#define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
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#define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
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#define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
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FORCEINLINE
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VOID
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MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
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@ -178,16 +225,7 @@ MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
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}
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/* Sign extend 48 bits */
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#define MiProtoPteToPte(x) \
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(PMMPTE)((LONG64)(x)->u.Proto.ProtoAddress)
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/* We don't use these hacks */
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VOID
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FORCEINLINE
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MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
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{
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/* Nothing to do */
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}
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#define MiProtoPteToPte(x) (PMMPTE)((LONG64)(x)->u.Proto.ProtoAddress)
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VOID
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FORCEINLINE
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@ -196,65 +234,3 @@ MmInitGlobalKernelPageDirectory(VOID)
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/* Nothing to do */
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}
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#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
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#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
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/* Easy accessing PFN in PTE */
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#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
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// FIXME, only copied from x86
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#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
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#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
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#define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
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#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
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#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
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#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
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#define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
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#if !defined(CONFIG_SMP)
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
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#else
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#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
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#endif
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#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
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#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
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#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
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#if !defined(CONFIG_SMP)
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
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#else
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#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
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#endif
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// FIXME!!!
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#define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
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((x) / (4*1024*1024))
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#define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
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((((x)) % (4*1024*1024)) / (4*1024))
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#define NR_SECTION_PAGE_TABLES 1024
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#define NR_SECTION_PAGE_ENTRIES 1024
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//#define TEB_BASE 0x7FFDE000
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
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MI_HYPERSPACE_PTES * PAGE_SIZE)
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#define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
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PAGE_SIZE)
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#define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \
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PAGE_SIZE)
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#define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \
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PAGE_SIZE)
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/* On x86, these two are the same */
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#define MMPDE MMPTE
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#define PMMPDE PMMPTE
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/*
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* FIXME - different architectures have different cache line sizes...
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*/
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#define MM_CACHE_LINE_SIZE 32
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@ -265,27 +265,6 @@ MiInitMachineDependent(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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/* Compute non paged pool limits and size */
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MiComputeNonPagedPoolVa(MiNumberOfFreePages);
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/* Compute color information (L2 cache-separated paging lists) */
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MiComputeColorInformation();
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//
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// Calculate the number of bytes for the PFN database
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// then add the color tables and convert to pages
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//
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MxPfnAllocation = (MmHighestPhysicalPage + 1) * sizeof(MMPFN);
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MxPfnAllocation += (MmSecondaryColors * sizeof(MMCOLOR_TABLES) * 2);
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MxPfnAllocation >>= PAGE_SHIFT;
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//
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// We have to add one to the count here, because in the process of
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// shifting down to the page size, we actually ended up getting the
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// lower aligned size (so say, 0x5FFFF bytes is now 0x5F pages).
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// Later on, we'll shift this number back into bytes, which would cause
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// us to end up with only 0x5F000 bytes -- when we actually want to have
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// 0x60000 bytes.
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//
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MxPfnAllocation++;
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//
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// Now calculate the nonpaged pool expansion VA region
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//
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@ -1884,6 +1884,9 @@ MmArmInitSystem(IN ULONG Phase,
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IncludeType[LoaderBBTMemory] = FALSE;
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if (Phase == 0)
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{
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/* Count physical pages on the system */
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MiScanMemoryDescriptors(LoaderBlock);
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/* Initialize the phase 0 temporary event */
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KeInitializeEvent(&MiTempEvent, NotificationEvent, FALSE);
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@ -1938,15 +1941,10 @@ MmArmInitSystem(IN ULONG Phase,
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KeInitializeEvent(&MmZeroingPageEvent, SynchronizationEvent, FALSE);
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MmZeroingPageThreadActive = FALSE;
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//
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// Count physical pages on the system
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//
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MiScanMemoryDescriptors(LoaderBlock);
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PageCount = MmNumberOfPhysicalPages;
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//
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// Check if this is a machine with less than 19MB of RAM
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//
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PageCount = MmNumberOfPhysicalPages;
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if (PageCount < MI_MIN_PAGES_FOR_SYSPTE_TUNING)
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{
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//
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@ -2032,6 +2030,23 @@ MmArmInitSystem(IN ULONG Phase,
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if (MmLargeStackSize < KERNEL_STACK_SIZE) MmLargeStackSize = KERNEL_STACK_SIZE;
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}
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/* Compute color information (L2 cache-separated paging lists) */
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MiComputeColorInformation();
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// Calculate the number of bytes for the PFN database
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// then add the color tables and convert to pages
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MxPfnAllocation = (MmHighestPhysicalPage + 1) * sizeof(MMPFN);
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MxPfnAllocation += (MmSecondaryColors * sizeof(MMCOLOR_TABLES) * 2);
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MxPfnAllocation >>= PAGE_SHIFT;
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// We have to add one to the count here, because in the process of
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// shifting down to the page size, we actually ended up getting the
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// lower aligned size (so say, 0x5FFFF bytes is now 0x5F pages).
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// Later on, we'll shift this number back into bytes, which would cause
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// us to end up with only 0x5F000 bytes -- when we actually want to have
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// 0x60000 bytes.
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MxPfnAllocation++;
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/* Initialize the platform-specific parts */
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MiInitMachineDependent(LoaderBlock);
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