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[ARM SDK]: Use real Versatile base addresses instead of the old hacked FreeLDR base addresses.

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svn path=/trunk/; revision=45506
This commit is contained in:
Sir Richard 2010-02-09 01:47:54 +00:00
parent 68410c584a
commit acb344ee2a
3 changed files with 8 additions and 8 deletions
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2
reactos/include/reactos/arm/peripherals/pl011.h
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@ -11,7 +11,7 @@
//
// UART Registers
//
#define UART_BASE (ULONG_PTR)0xE00F1000 /* HACK: freeldr mapped it here */
#define UART_BASE (ULONG_PTR)0x101F1000
#define UART_PL01x_DR (UART_BASE + 0x00)
#define UART_PL01x_RSR (UART_BASE + 0x04)

12
reactos/include/reactos/arm/peripherals/pl190.h
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@ -11,10 +11,10 @@
//
// VIC Registers
//
#define VIC_BASE (ULONG_PTR)0xE0040000 /* HACK: freeldr mapped it here */
#define VIC_BASE (ULONG_PTR)0x10140000
#define VIC_INT_STATUS (VIC_BASE + 0x00)
#define VIC_INT_ENABLE (VIC_BASE + 0x10)
#define VIC_INT_CLEAR (VIC_BASE + 0x14)
#define VIC_SOFT_INT (VIC_BASE + 0x18)
#define VIC_SOFT_INT_CLEAR (VIC_BASE + 0x1C)
#define VIC_INT_STATUS (PULONG)(VIC_BASE + 0x00)
#define VIC_INT_ENABLE (PULONG)(VIC_BASE + 0x10)
#define VIC_INT_CLEAR (PULONG)(VIC_BASE + 0x14)
#define VIC_SOFT_INT (PULONG)(VIC_BASE + 0x18)
#define VIC_SOFT_INT_CLEAR (PULONG)(VIC_BASE + 0x1C)

2
reactos/include/reactos/arm/peripherals/sp804.h
View file

@ -11,7 +11,7 @@
//
// Timer Registers
//
#define TIMER_BASE(x) (ULONG_PTR)(0xE00E2000 + (x * 0x1000)) /* HACK: freeldr mapped it here */
#define TIMER_BASE(x) (ULONG_PTR)(0x101E2000 + (x * 0x1000))
#define TIMER0_LOAD TIMER_BASE(0) + 0x00
#define TIMER0_VALUE TIMER_BASE(0) + 0x04
#define TIMER0_CONTROL TIMER_BASE(0) + 0x08