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[HAL]

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Fix syntax, patch by Victor Martinez

svn path=/trunk/; revision=55496
This commit is contained in:
Timo Kreuzer 2012-02-08 18:29:08 +00:00
parent d964bd32f2
commit a713dd0ea3
1 changed files with 106 additions and 106 deletions
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212
reactos/hal/halx86/up/pic.c
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@ -104,7 +104,7 @@ ULONG KiI8259MaskTable[32] =
0b00000000000000000000000000000000, /* IRQL 1 */ 0b00000000000000000000000000000000, /* IRQL 1 */
0b00000000000000000000000000000000, /* IRQL 2 */ 0b00000000000000000000000000000000, /* IRQL 2 */
0b00000000000000000000000000000000, /* IRQL 3 */ 0b00000000000000000000000000000000, /* IRQL 3 */
/* /*
* These next IRQLs are actually useless from the PIC perspective, because * These next IRQLs are actually useless from the PIC perspective, because
* with only 2 PICs, the mask you can send them is only 8 bits each, for 16 * with only 2 PICs, the mask you can send them is only 8 bits each, for 16
@ -118,7 +118,7 @@ ULONG KiI8259MaskTable[32] =
0b11111111111111000000000000000000, /* IRQL 9 */ 0b11111111111111000000000000000000, /* IRQL 9 */
0b11111111111111100000000000000000, /* IRQL 10 */ 0b11111111111111100000000000000000, /* IRQL 10 */
0b11111111111111110000000000000000, /* IRQL 11 */ 0b11111111111111110000000000000000, /* IRQL 11 */
/* /*
* Okay, now we're finally starting to mask off IRQs on the slave PIC, from * Okay, now we're finally starting to mask off IRQs on the slave PIC, from
* IRQ15 to IRQ8. This means the higher-level IRQs get less priority in the * IRQ15 to IRQ8. This means the higher-level IRQs get less priority in the
@ -132,7 +132,7 @@ ULONG KiI8259MaskTable[32] =
0b11111111111111111111110000000000, /* IRQL 17 */ 0b11111111111111111111110000000000, /* IRQL 17 */
0b11111111111111111111111000000000, /* IRQL 18 */ 0b11111111111111111111111000000000, /* IRQL 18 */
0b11111111111111111111111000000000, /* IRQL 19 */ 0b11111111111111111111111000000000, /* IRQL 19 */
/* /*
* Now we mask off the IRQs on the master. Notice the 0 "droplet"? You might * Now we mask off the IRQs on the master. Notice the 0 "droplet"? You might
* have also seen that IRQL 18 and 19 are essentially equal as far as the * have also seen that IRQL 18 and 19 are essentially equal as far as the
@ -149,7 +149,7 @@ ULONG KiI8259MaskTable[32] =
0b11111111111111111111111011111000, /* IRQL 25 */ 0b11111111111111111111111011111000, /* IRQL 25 */
0b11111111111111111111111011111010, /* IRQL 26 */ 0b11111111111111111111111011111010, /* IRQL 26 */
0b11111111111111111111111111111010, /* IRQL 27 */ 0b11111111111111111111111111111010, /* IRQL 27 */
/* /*
* IRQL 24 and 25 are actually identical, so IRQL 28 is actually the last * IRQL 24 and 25 are actually identical, so IRQL 28 is actually the last
* IRQL to modify a bit on the master PIC. It happens to modify the very * IRQL to modify a bit on the master PIC. It happens to modify the very
@ -160,7 +160,7 @@ ULONG KiI8259MaskTable[32] =
* called CLOCK2_LEVEL, which explains the usage we just explained. * called CLOCK2_LEVEL, which explains the usage we just explained.
*/ */
0b11111111111111111111111111111011, /* IRQL 28 */ 0b11111111111111111111111111111011, /* IRQL 28 */
/* /*
* We have finished off with the PIC so there's nothing left to mask at the * We have finished off with the PIC so there's nothing left to mask at the
* level of these IRQLs, making them only logical IRQLs on x86 machines. * level of these IRQLs, making them only logical IRQLs on x86 machines.
@ -221,13 +221,13 @@ ULONG FindHigherIrqlMask[32] =
0b11111111111111111111111111111110, /* IRQL 0 */ 0b11111111111111111111111111111110, /* IRQL 0 */
0b11111111111111111111111111111100, /* IRQL 1 */ 0b11111111111111111111111111111100, /* IRQL 1 */
0b11111111111111111111111111111000, /* IRQL 2 */ 0b11111111111111111111111111111000, /* IRQL 2 */
/* /*
* IRQL3 means only hardware IRQLs can now preempt. These last 4 zeros will * IRQL3 means only hardware IRQLs can now preempt. These last 4 zeros will
* then continue throughout the rest of the list, trickling down. * then continue throughout the rest of the list, trickling down.
*/ */
0b11111111111111111111111111110000, /* IRQL 3 */ 0b11111111111111111111111111110000, /* IRQL 3 */
/* /*
* Just like in the previous list, these masks don't really mean anything * Just like in the previous list, these masks don't really mean anything
* since we've only got two PICs with 16 possible IRQs total * since we've only got two PICs with 16 possible IRQs total
@ -239,7 +239,7 @@ ULONG FindHigherIrqlMask[32] =
0b00000000011111111111111111110000, /* IRQL 8 */ 0b00000000011111111111111111110000, /* IRQL 8 */
0b00000000001111111111111111110000, /* IRQL 9 */ 0b00000000001111111111111111110000, /* IRQL 9 */
0b00000000000111111111111111110000, /* IRQL 10 */ 0b00000000000111111111111111110000, /* IRQL 10 */
/* /*
* Now we start progressivly limiting which slave PIC interrupts have the * Now we start progressivly limiting which slave PIC interrupts have the
* right to preempt us at each level. * right to preempt us at each level.
@ -253,7 +253,7 @@ ULONG FindHigherIrqlMask[32] =
0b00000000000000000011111111110000, /* IRQL 17 */ 0b00000000000000000011111111110000, /* IRQL 17 */
0b00000000000000000001111111110000, /* IRQL 18 */ 0b00000000000000000001111111110000, /* IRQL 18 */
0b00000000000000000001111111110000, /* IRQL 19 */ 0b00000000000000000001111111110000, /* IRQL 19 */
/* /*
* Also recall from the earlier table that IRQL 18/19 are treated the same * Also recall from the earlier table that IRQL 18/19 are treated the same
* in order to spread the masks better thoughout the 32 IRQLs and to reflect * in order to spread the masks better thoughout the 32 IRQLs and to reflect
@ -269,15 +269,15 @@ ULONG FindHigherIrqlMask[32] =
0b00000000000000000001000001110000, /* IRQL 24 */ 0b00000000000000000001000001110000, /* IRQL 24 */
0b00000000000000000001000000110000, /* IRQL 25 */ 0b00000000000000000001000000110000, /* IRQL 25 */
0b00000000000000000001000000010000, /* IRQL 26 */ 0b00000000000000000001000000010000, /* IRQL 26 */
/* At this point, only the clock (IRQ0) can still preempt... */ /* At this point, only the clock (IRQ0) can still preempt... */
0b00000000000000000000000000010000, /* IRQL 27 */ 0b00000000000000000000000000010000, /* IRQL 27 */
/* And any higher than that there's no relation with hardware PICs anymore */ /* And any higher than that there's no relation with hardware PICs anymore */
0b00000000000000000000000000000000, /* IRQL 28 */ 0b00000000000000000000000000000000, /* IRQL 28 */
0b00000000000000000000000000000000, /* IRQL 29 */ 0b00000000000000000000000000000000, /* IRQL 29 */
0b00000000000000000000000000000000, /* IRQL 30 */ 0b00000000000000000000000000000000, /* IRQL 30 */
0b00000000000000000000000000000000, /* IRQL 31 */ 0b00000000000000000000000000000000 /* IRQL 31 */
#else #else
0xFFFFFFFE, /* IRQL 0 */ 0xFFFFFFFE, /* IRQL 0 */
0xFFFFFFFC, /* IRQL 1 */ 0xFFFFFFFC, /* IRQL 1 */
@ -420,11 +420,11 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
I8259_ICW4 Icw4; I8259_ICW4 Icw4;
EISA_ELCR Elcr; EISA_ELCR Elcr;
ULONG i, j; ULONG i, j;
/* Save EFlags and disable interrupts */ /* Save EFlags and disable interrupts */
EFlags = __readeflags(); EFlags = __readeflags();
_disable(); _disable();
/* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */ /* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */
Icw1.NeedIcw4 = TRUE; Icw1.NeedIcw4 = TRUE;
Icw1.InterruptMode = EdgeTriggered; Icw1.InterruptMode = EdgeTriggered;
@ -433,16 +433,16 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
Icw1.Init = TRUE; Icw1.Init = TRUE;
Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */ Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */
__outbyte(PIC1_CONTROL_PORT, Icw1.Bits); __outbyte(PIC1_CONTROL_PORT, Icw1.Bits);
/* Set interrupt vector base */ /* Set interrupt vector base */
Icw2.Bits = PRIMARY_VECTOR_BASE; Icw2.Bits = PRIMARY_VECTOR_BASE;
__outbyte(PIC1_DATA_PORT, Icw2.Bits); __outbyte(PIC1_DATA_PORT, Icw2.Bits);
/* Connect slave to IRQ 2 */ /* Connect slave to IRQ 2 */
Icw3.Bits = 0; Icw3.Bits = 0;
Icw3.SlaveIrq2 = TRUE; Icw3.SlaveIrq2 = TRUE;
__outbyte(PIC1_DATA_PORT, Icw3.Bits); __outbyte(PIC1_DATA_PORT, Icw3.Bits);
/* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */ /* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
Icw4.Reserved = 0; Icw4.Reserved = 0;
Icw4.SystemMode = New8086Mode; Icw4.SystemMode = New8086Mode;
@ -450,10 +450,10 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
Icw4.BufferedMode = NonBuffered; Icw4.BufferedMode = NonBuffered;
Icw4.SpecialFullyNestedMode = FALSE; Icw4.SpecialFullyNestedMode = FALSE;
__outbyte(PIC1_DATA_PORT, Icw4.Bits); __outbyte(PIC1_DATA_PORT, Icw4.Bits);
/* Mask all interrupts */ /* Mask all interrupts */
__outbyte(PIC1_DATA_PORT, 0xFF); __outbyte(PIC1_DATA_PORT, 0xFF);
/* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */ /* Initialize ICW1 for master, interval 8, edge-triggered mode with ICW4 */
Icw1.NeedIcw4 = TRUE; Icw1.NeedIcw4 = TRUE;
Icw1.InterruptMode = EdgeTriggered; Icw1.InterruptMode = EdgeTriggered;
@ -462,16 +462,16 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
Icw1.Init = TRUE; Icw1.Init = TRUE;
Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */ Icw1.InterruptVectorAddress = 0; /* This is only used in MCS80/85 mode */
__outbyte(PIC2_CONTROL_PORT, Icw1.Bits); __outbyte(PIC2_CONTROL_PORT, Icw1.Bits);
/* Set interrupt vector base */ /* Set interrupt vector base */
Icw2.Bits = PRIMARY_VECTOR_BASE + 8; Icw2.Bits = PRIMARY_VECTOR_BASE + 8;
__outbyte(PIC2_DATA_PORT, Icw2.Bits); __outbyte(PIC2_DATA_PORT, Icw2.Bits);
/* Slave ID */ /* Slave ID */
Icw3.Bits = 0; Icw3.Bits = 0;
Icw3.SlaveId = 2; Icw3.SlaveId = 2;
__outbyte(PIC2_DATA_PORT, Icw3.Bits); __outbyte(PIC2_DATA_PORT, Icw3.Bits);
/* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */ /* Enable 8086 mode, non-automatic EOI, non-buffered mode, non special fully nested mode */
Icw4.Reserved = 0; Icw4.Reserved = 0;
Icw4.SystemMode = New8086Mode; Icw4.SystemMode = New8086Mode;
@ -479,20 +479,20 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
Icw4.BufferedMode = NonBuffered; Icw4.BufferedMode = NonBuffered;
Icw4.SpecialFullyNestedMode = FALSE; Icw4.SpecialFullyNestedMode = FALSE;
__outbyte(PIC2_DATA_PORT, Icw4.Bits); __outbyte(PIC2_DATA_PORT, Icw4.Bits);
/* Mask all interrupts */ /* Mask all interrupts */
__outbyte(PIC2_DATA_PORT, 0xFF); __outbyte(PIC2_DATA_PORT, 0xFF);
/* Read EISA Edge/Level Register for master and slave */ /* Read EISA Edge/Level Register for master and slave */
Elcr.Bits = (__inbyte(EISA_ELCR_SLAVE) << 8) | __inbyte(EISA_ELCR_MASTER); Elcr.Bits = (__inbyte(EISA_ELCR_SLAVE) << 8) | __inbyte(EISA_ELCR_MASTER);
/* IRQs 0, 1, 2, 8, and 13 are system-reserved and must be edge */ /* IRQs 0, 1, 2, 8, and 13 are system-reserved and must be edge */
if (!(Elcr.Master.Irq0Level) && !(Elcr.Master.Irq1Level) && !(Elcr.Master.Irq2Level) && if (!(Elcr.Master.Irq0Level) && !(Elcr.Master.Irq1Level) && !(Elcr.Master.Irq2Level) &&
!(Elcr.Slave.Irq8Level) && !(Elcr.Slave.Irq13Level)) !(Elcr.Slave.Irq8Level) && !(Elcr.Slave.Irq13Level))
{ {
/* ELCR is as it's supposed to be, save it */ /* ELCR is as it's supposed to be, save it */
HalpEisaELCR = Elcr.Bits; HalpEisaELCR = Elcr.Bits;
/* Scan for level interrupts */ /* Scan for level interrupts */
for (i = 1, j = 0; j < 16; i <<= 1, j++) for (i = 1, j = 0; j < 16; i <<= 1, j++)
{ {
@ -506,7 +506,7 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
} }
} }
} }
/* Register IRQ 2 */ /* Register IRQ 2 */
HalpRegisterVector(IDT_INTERNAL, HalpRegisterVector(IDT_INTERNAL,
PRIMARY_VECTOR_BASE + 2, PRIMARY_VECTOR_BASE + 2,
@ -561,11 +561,11 @@ KeRaiseIrqlToDpcLevel(VOID)
{ {
PKPCR Pcr = KeGetPcr(); PKPCR Pcr = KeGetPcr();
KIRQL CurrentIrql; KIRQL CurrentIrql;
/* Save and update IRQL */ /* Save and update IRQL */
CurrentIrql = Pcr->Irql; CurrentIrql = Pcr->Irql;
Pcr->Irql = DISPATCH_LEVEL; Pcr->Irql = DISPATCH_LEVEL;
#if DBG #if DBG
/* Validate correct raise */ /* Validate correct raise */
if (CurrentIrql > DISPATCH_LEVEL) KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL); if (CurrentIrql > DISPATCH_LEVEL) KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
@ -584,11 +584,11 @@ KeRaiseIrqlToSynchLevel(VOID)
{ {
PKPCR Pcr = KeGetPcr(); PKPCR Pcr = KeGetPcr();
KIRQL CurrentIrql; KIRQL CurrentIrql;
/* Save and update IRQL */ /* Save and update IRQL */
CurrentIrql = Pcr->Irql; CurrentIrql = Pcr->Irql;
Pcr->Irql = SYNCH_LEVEL; Pcr->Irql = SYNCH_LEVEL;
#if DBG #if DBG
/* Validate correct raise */ /* Validate correct raise */
if (CurrentIrql > SYNCH_LEVEL) if (CurrentIrql > SYNCH_LEVEL)
@ -618,7 +618,7 @@ KfRaiseIrql(IN KIRQL NewIrql)
/* Read current IRQL */ /* Read current IRQL */
CurrentIrql = Pcr->Irql; CurrentIrql = Pcr->Irql;
#if DBG #if DBG
/* Validate correct raise */ /* Validate correct raise */
if (CurrentIrql > NewIrql) if (CurrentIrql > NewIrql)
@ -631,7 +631,7 @@ KfRaiseIrql(IN KIRQL NewIrql)
/* Set new IRQL */ /* Set new IRQL */
Pcr->Irql = NewIrql; Pcr->Irql = NewIrql;
/* Return old IRQL */ /* Return old IRQL */
return CurrentIrql; return CurrentIrql;
} }
@ -648,7 +648,7 @@ KfLowerIrql(IN KIRQL OldIrql)
ULONG PendingIrql, PendingIrqlMask; ULONG PendingIrql, PendingIrqlMask;
PKPCR Pcr = KeGetPcr(); PKPCR Pcr = KeGetPcr();
PIC_MASK Mask; PIC_MASK Mask;
#if DBG #if DBG
/* Validate correct lower */ /* Validate correct lower */
if (OldIrql > Pcr->Irql) if (OldIrql > Pcr->Irql)
@ -658,7 +658,7 @@ KfLowerIrql(IN KIRQL OldIrql)
KeBugCheck(IRQL_NOT_LESS_OR_EQUAL); KeBugCheck(IRQL_NOT_LESS_OR_EQUAL);
} }
#endif #endif
/* Save EFlags and disable interrupts */ /* Save EFlags and disable interrupts */
EFlags = __readeflags(); EFlags = __readeflags();
_disable(); _disable();
@ -707,18 +707,18 @@ HalRequestSoftwareInterrupt(IN KIRQL Irql)
ULONG EFlags; ULONG EFlags;
PKPCR Pcr = KeGetPcr(); PKPCR Pcr = KeGetPcr();
KIRQL PendingIrql; KIRQL PendingIrql;
/* Save EFlags and disable interrupts */ /* Save EFlags and disable interrupts */
EFlags = __readeflags(); EFlags = __readeflags();
_disable(); _disable();
/* Mask out the requested bit */ /* Mask out the requested bit */
Pcr->IRR |= (1 << Irql); Pcr->IRR |= (1 << Irql);
/* Check for pending software interrupts and compare with current IRQL */ /* Check for pending software interrupts and compare with current IRQL */
PendingIrql = SWInterruptLookUpTable[Pcr->IRR & 3]; PendingIrql = SWInterruptLookUpTable[Pcr->IRR & 3];
if (PendingIrql > Pcr->Irql) SWInterruptHandlerTable[PendingIrql](); if (PendingIrql > Pcr->Irql) SWInterruptHandlerTable[PendingIrql]();
/* Restore interrupt state */ /* Restore interrupt state */
__writeeflags(EFlags); __writeeflags(EFlags);
} }
@ -752,10 +752,10 @@ HalpEndSoftwareInterrupt(IN KIRQL OldIrql,
/* Check for pending software interrupts and compare with current IRQL */ /* Check for pending software interrupts and compare with current IRQL */
PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql]; PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
if (!PendingIrqlMask) return; if (!PendingIrqlMask) return;
/* Check for in-service delayed interrupt */ /* Check for in-service delayed interrupt */
if (Pcr->IrrActive & 0xFFFFFFF0) return; if (Pcr->IrrActive & 0xFFFFFFF0) return;
/* Check if pending IRQL affects hardware state */ /* Check if pending IRQL affects hardware state */
BitScanReverse(&PendingIrql, PendingIrqlMask); BitScanReverse(&PendingIrql, PendingIrqlMask);
if (PendingIrql > DISPATCH_LEVEL) if (PendingIrql > DISPATCH_LEVEL)
@ -769,10 +769,10 @@ HalpEndSoftwareInterrupt(IN KIRQL OldIrql,
PendingIrqMask = (1 << PendingIrql); PendingIrqMask = (1 << PendingIrql);
Pcr->IrrActive |= PendingIrqMask; Pcr->IrrActive |= PendingIrqMask;
Pcr->IRR ^= PendingIrqMask; Pcr->IRR ^= PendingIrqMask;
/* Handle delayed hardware interrupt */ /* Handle delayed hardware interrupt */
SWInterruptHandlerTable[PendingIrql](); SWInterruptHandlerTable[PendingIrql]();
/* Handling complete */ /* Handling complete */
Pcr->IrrActive ^= PendingIrqMask; Pcr->IrrActive ^= PendingIrqMask;
} }
@ -799,14 +799,14 @@ _HalpDismissIrqGeneric(IN KIRQL Irql,
/* First save current IRQL and compare it to the requested one */ /* First save current IRQL and compare it to the requested one */
CurrentIrql = Pcr->Irql; CurrentIrql = Pcr->Irql;
/* Check if this interrupt is really allowed to happen */ /* Check if this interrupt is really allowed to happen */
if (Irql > CurrentIrql) if (Irql > CurrentIrql)
{ {
/* Set the new IRQL and return the current one */ /* Set the new IRQL and return the current one */
Pcr->Irql = Irql; Pcr->Irql = Irql;
*OldIrql = CurrentIrql; *OldIrql = CurrentIrql;
/* Prepare OCW2 for EOI */ /* Prepare OCW2 for EOI */
Ocw2.Bits = 0; Ocw2.Bits = 0;
Ocw2.EoiMode = SpecificEoi; Ocw2.EoiMode = SpecificEoi;
@ -816,7 +816,7 @@ _HalpDismissIrqGeneric(IN KIRQL Irql,
{ {
/* Send the EOI for the IRQ */ /* Send the EOI for the IRQ */
__outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF)); __outbyte(PIC2_CONTROL_PORT, Ocw2.Bits | ((Irq - 8) & 0xFF));
/* Send the EOI for IRQ2 on the master because this was cascaded */ /* Send the EOI for IRQ2 on the master because this was cascaded */
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2); __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
} }
@ -825,20 +825,20 @@ _HalpDismissIrqGeneric(IN KIRQL Irql,
/* Send the EOI for the IRQ */ /* Send the EOI for the IRQ */
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | (Irq &0xFF)); __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | (Irq &0xFF));
} }
/* Enable interrupts and return success */ /* Enable interrupts and return success */
_enable(); _enable();
return TRUE; return TRUE;
} }
/* Update the IRR so that we deliver this interrupt when the IRQL is proper */ /* Update the IRR so that we deliver this interrupt when the IRQL is proper */
Pcr->IRR |= (1 << (Irq + 4)); Pcr->IRR |= (1 << (Irq + 4));
/* Set new PIC mask to real IRQL level, since the optimization is lost now */ /* Set new PIC mask to real IRQL level, since the optimization is lost now */
Mask.Both = (KiI8259MaskTable[CurrentIrql] | Pcr->IDR) & 0xFFFF; Mask.Both = (KiI8259MaskTable[CurrentIrql] | Pcr->IDR) & 0xFFFF;
__outbyte(PIC1_DATA_PORT, Mask.Master); __outbyte(PIC1_DATA_PORT, Mask.Master);
__outbyte(PIC2_DATA_PORT, Mask.Slave); __outbyte(PIC2_DATA_PORT, Mask.Slave);
/* Now lie and say this was spurious */ /* Now lie and say this was spurious */
return FALSE; return FALSE;
} }
@ -862,16 +862,16 @@ HalpDismissIrq15(IN KIRQL Irql,
I8259_OCW3 Ocw3; I8259_OCW3 Ocw3;
I8259_OCW2 Ocw2; I8259_OCW2 Ocw2;
I8259_ISR Isr; I8259_ISR Isr;
/* Request the ISR */ /* Request the ISR */
Ocw3.Bits = 0; Ocw3.Bits = 0;
Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */ Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
Ocw3.ReadRequest = ReadIsr; Ocw3.ReadRequest = ReadIsr;
__outbyte(PIC2_CONTROL_PORT, Ocw3.Bits); __outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
/* Read the ISR */ /* Read the ISR */
Isr.Bits = __inbyte(PIC2_CONTROL_PORT); Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
/* Is IRQ15 really active (this is IR7) */ /* Is IRQ15 really active (this is IR7) */
if (Isr.Irq7 == FALSE) if (Isr.Irq7 == FALSE)
{ {
@ -879,7 +879,7 @@ HalpDismissIrq15(IN KIRQL Irql,
Ocw2.Bits = 0; Ocw2.Bits = 0;
Ocw2.EoiMode = SpecificEoi; Ocw2.EoiMode = SpecificEoi;
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2); __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
/* And now fail since this was spurious */ /* And now fail since this was spurious */
return FALSE; return FALSE;
} }
@ -897,7 +897,7 @@ HalpDismissIrq13(IN KIRQL Irql,
{ {
/* Clear the FPU busy latch */ /* Clear the FPU busy latch */
__outbyte(0xF0, 0); __outbyte(0xF0, 0);
/* Do normal interrupt dismiss */ /* Do normal interrupt dismiss */
return _HalpDismissIrqGeneric(Irql, Irq, OldIrql); return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
} }
@ -910,19 +910,19 @@ HalpDismissIrq07(IN KIRQL Irql,
{ {
I8259_OCW3 Ocw3; I8259_OCW3 Ocw3;
I8259_ISR Isr; I8259_ISR Isr;
/* Request the ISR */ /* Request the ISR */
Ocw3.Bits = 0; Ocw3.Bits = 0;
Ocw3.Sbo = 1; Ocw3.Sbo = 1;
Ocw3.ReadRequest = ReadIsr; Ocw3.ReadRequest = ReadIsr;
__outbyte(PIC1_CONTROL_PORT, Ocw3.Bits); __outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);
/* Read the ISR */ /* Read the ISR */
Isr.Bits = __inbyte(PIC1_CONTROL_PORT); Isr.Bits = __inbyte(PIC1_CONTROL_PORT);
/* Is IRQ 7 really active? If it isn't, this is spurious so fail */ /* Is IRQ 7 really active? If it isn't, this is spurious so fail */
if (Isr.Irq7 == FALSE) return FALSE; if (Isr.Irq7 == FALSE) return FALSE;
/* Do normal interrupt dismiss */ /* Do normal interrupt dismiss */
return _HalpDismissIrqGeneric(Irql, Irq, OldIrql); return _HalpDismissIrqGeneric(Irql, Irq, OldIrql);
} }
@ -944,13 +944,13 @@ _HalpDismissIrqLevel(IN KIRQL Irql,
Mask.Both = (KiI8259MaskTable[Irql] | Pcr->IDR) & 0xFFFF; Mask.Both = (KiI8259MaskTable[Irql] | Pcr->IDR) & 0xFFFF;
__outbyte(PIC1_DATA_PORT, Mask.Master); __outbyte(PIC1_DATA_PORT, Mask.Master);
__outbyte(PIC2_DATA_PORT, Mask.Slave); __outbyte(PIC2_DATA_PORT, Mask.Slave);
/* Update the IRR so that we clear this interrupt when the IRQL is proper */ /* Update the IRR so that we clear this interrupt when the IRQL is proper */
Pcr->IRR |= (1 << (Irq + 4)); Pcr->IRR |= (1 << (Irq + 4));
/* Save current IRQL */ /* Save current IRQL */
CurrentIrql = Pcr->Irql; CurrentIrql = Pcr->Irql;
/* Prepare OCW2 for EOI */ /* Prepare OCW2 for EOI */
Ocw2.Bits = 0; Ocw2.Bits = 0;
Ocw2.EoiMode = SpecificEoi; Ocw2.EoiMode = SpecificEoi;
@ -976,12 +976,12 @@ _HalpDismissIrqLevel(IN KIRQL Irql,
/* Set the new IRQL and return the current one */ /* Set the new IRQL and return the current one */
Pcr->Irql = Irql; Pcr->Irql = Irql;
*OldIrql = CurrentIrql; *OldIrql = CurrentIrql;
/* Enable interrupts and return success */ /* Enable interrupts and return success */
_enable(); _enable();
return TRUE; return TRUE;
} }
/* Now lie and say this was spurious */ /* Now lie and say this was spurious */
return FALSE; return FALSE;
} }
@ -1005,16 +1005,16 @@ HalpDismissIrq15Level(IN KIRQL Irql,
I8259_OCW3 Ocw3; I8259_OCW3 Ocw3;
I8259_OCW2 Ocw2; I8259_OCW2 Ocw2;
I8259_ISR Isr; I8259_ISR Isr;
/* Request the ISR */ /* Request the ISR */
Ocw3.Bits = 0; Ocw3.Bits = 0;
Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */ Ocw3.Sbo = 1; /* This encodes an OCW3 vs. an OCW2 */
Ocw3.ReadRequest = ReadIsr; Ocw3.ReadRequest = ReadIsr;
__outbyte(PIC2_CONTROL_PORT, Ocw3.Bits); __outbyte(PIC2_CONTROL_PORT, Ocw3.Bits);
/* Read the ISR */ /* Read the ISR */
Isr.Bits = __inbyte(PIC2_CONTROL_PORT); Isr.Bits = __inbyte(PIC2_CONTROL_PORT);
/* Is IRQ15 really active (this is IR7) */ /* Is IRQ15 really active (this is IR7) */
if (Isr.Irq7 == FALSE) if (Isr.Irq7 == FALSE)
{ {
@ -1022,7 +1022,7 @@ HalpDismissIrq15Level(IN KIRQL Irql,
Ocw2.Bits = 0; Ocw2.Bits = 0;
Ocw2.EoiMode = SpecificEoi; Ocw2.EoiMode = SpecificEoi;
__outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2); __outbyte(PIC1_CONTROL_PORT, Ocw2.Bits | 2);
/* And now fail since this was spurious */ /* And now fail since this was spurious */
return FALSE; return FALSE;
} }
@ -1039,7 +1039,7 @@ HalpDismissIrq13Level(IN KIRQL Irql,
{ {
/* Clear the FPU busy latch */ /* Clear the FPU busy latch */
__outbyte(0xF0, 0); __outbyte(0xF0, 0);
/* Do normal interrupt dismiss */ /* Do normal interrupt dismiss */
return _HalpDismissIrqLevel(Irql, Irq, OldIrql); return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
} }
@ -1052,19 +1052,19 @@ HalpDismissIrq07Level(IN KIRQL Irql,
{ {
I8259_OCW3 Ocw3; I8259_OCW3 Ocw3;
I8259_ISR Isr; I8259_ISR Isr;
/* Request the ISR */ /* Request the ISR */
Ocw3.Bits = 0; Ocw3.Bits = 0;
Ocw3.Sbo = 1; Ocw3.Sbo = 1;
Ocw3.ReadRequest = ReadIsr; Ocw3.ReadRequest = ReadIsr;
__outbyte(PIC1_CONTROL_PORT, Ocw3.Bits); __outbyte(PIC1_CONTROL_PORT, Ocw3.Bits);
/* Read the ISR */ /* Read the ISR */
Isr.Bits = __inbyte(PIC1_CONTROL_PORT); Isr.Bits = __inbyte(PIC1_CONTROL_PORT);
/* Is IRQ 7 really active? If it isn't, this is spurious so fail */ /* Is IRQ 7 really active? If it isn't, this is spurious so fail */
if (Isr.Irq7 == FALSE) return FALSE; if (Isr.Irq7 == FALSE) return FALSE;
/* Do normal interrupt dismiss */ /* Do normal interrupt dismiss */
return _HalpDismissIrqLevel(Irql, Irq, OldIrql); return _HalpDismissIrqLevel(Irql, Irq, OldIrql);
} }
@ -1074,17 +1074,17 @@ HalpHardwareInterruptLevel(VOID)
{ {
PKPCR Pcr = KeGetPcr(); PKPCR Pcr = KeGetPcr();
ULONG PendingIrqlMask, PendingIrql; ULONG PendingIrqlMask, PendingIrql;
/* Check for pending software interrupts and compare with current IRQL */ /* Check for pending software interrupts and compare with current IRQL */
PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql]; PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql];
if (PendingIrqlMask) if (PendingIrqlMask)
{ {
/* Check for in-service delayed interrupt */ /* Check for in-service delayed interrupt */
if (Pcr->IrrActive & 0xFFFFFFF0) return; if (Pcr->IrrActive & 0xFFFFFFF0) return;
/* Check if pending IRQL affects hardware state */ /* Check if pending IRQL affects hardware state */
BitScanReverse(&PendingIrql, PendingIrqlMask); BitScanReverse(&PendingIrql, PendingIrqlMask);
/* Clear IRR bit */ /* Clear IRR bit */
Pcr->IRR ^= (1 << PendingIrql); Pcr->IRR ^= (1 << PendingIrql);
@ -1107,24 +1107,24 @@ HalEnableSystemInterrupt(IN ULONG Vector,
ULONG Irq; ULONG Irq;
PKPCR Pcr = KeGetPcr(); PKPCR Pcr = KeGetPcr();
PIC_MASK PicMask; PIC_MASK PicMask;
/* Validate the IRQ */ /* Validate the IRQ */
Irq = Vector - PRIMARY_VECTOR_BASE; Irq = Vector - PRIMARY_VECTOR_BASE;
if (Irq >= CLOCK2_LEVEL) return FALSE; if (Irq >= CLOCK2_LEVEL) return FALSE;
/* Check for level interrupt */ /* Check for level interrupt */
if (InterruptMode == LevelSensitive) if (InterruptMode == LevelSensitive)
{ {
/* Switch handler to level */ /* Switch handler to level */
SWInterruptHandlerTable[Irq + 4] = HalpHardwareInterruptLevel; SWInterruptHandlerTable[Irq + 4] = HalpHardwareInterruptLevel;
/* Switch dismiss to level */ /* Switch dismiss to level */
HalpSpecialDismissTable[Irq] = HalpSpecialDismissLevelTable[Irq]; HalpSpecialDismissTable[Irq] = HalpSpecialDismissLevelTable[Irq];
} }
/* Disable interrupts */ /* Disable interrupts */
_disable(); _disable();
/* Update software IDR */ /* Update software IDR */
Pcr->IDR &= ~(1 << Irq); Pcr->IDR &= ~(1 << Irq);
@ -1132,7 +1132,7 @@ HalEnableSystemInterrupt(IN ULONG Vector,
PicMask.Both = (KiI8259MaskTable[Pcr->Irql] | Pcr->IDR) & 0xFFFF; PicMask.Both = (KiI8259MaskTable[Pcr->Irql] | Pcr->IDR) & 0xFFFF;
__outbyte(PIC1_DATA_PORT, PicMask.Master); __outbyte(PIC1_DATA_PORT, PicMask.Master);
__outbyte(PIC2_DATA_PORT, PicMask.Slave); __outbyte(PIC2_DATA_PORT, PicMask.Slave);
/* Enable interrupts and exit */ /* Enable interrupts and exit */
_enable(); _enable();
return TRUE; return TRUE;
@ -1151,24 +1151,24 @@ HalDisableSystemInterrupt(IN ULONG Vector,
/* Compute new combined IRQ mask */ /* Compute new combined IRQ mask */
IrqMask = 1 << (Vector - PRIMARY_VECTOR_BASE); IrqMask = 1 << (Vector - PRIMARY_VECTOR_BASE);
/* Disable interrupts */ /* Disable interrupts */
_disable(); _disable();
/* Update software IDR */ /* Update software IDR */
KeGetPcr()->IDR |= IrqMask; KeGetPcr()->IDR |= IrqMask;
/* Read current interrupt mask */ /* Read current interrupt mask */
PicMask.Master = __inbyte(PIC1_DATA_PORT); PicMask.Master = __inbyte(PIC1_DATA_PORT);
PicMask.Slave = __inbyte(PIC2_DATA_PORT); PicMask.Slave = __inbyte(PIC2_DATA_PORT);
/* Add the new disabled interrupt */ /* Add the new disabled interrupt */
PicMask.Both |= IrqMask; PicMask.Both |= IrqMask;
/* Write new interrupt mask */ /* Write new interrupt mask */
__outbyte(PIC1_DATA_PORT, PicMask.Master); __outbyte(PIC1_DATA_PORT, PicMask.Master);
__outbyte(PIC2_DATA_PORT, PicMask.Slave); __outbyte(PIC2_DATA_PORT, PicMask.Slave);
/* Bring interrupts back */ /* Bring interrupts back */
_enable(); _enable();
} }
@ -1183,7 +1183,7 @@ HalBeginSystemInterrupt(IN KIRQL Irql,
OUT PKIRQL OldIrql) OUT PKIRQL OldIrql)
{ {
ULONG Irq; ULONG Irq;
/* Get the IRQ and call the proper routine to handle it */ /* Get the IRQ and call the proper routine to handle it */
Irq = Vector - PRIMARY_VECTOR_BASE; Irq = Vector - PRIMARY_VECTOR_BASE;
return HalpSpecialDismissTable[Irq](Irql, Irq, OldIrql); return HalpSpecialDismissTable[Irq](Irql, Irq, OldIrql);
@ -1210,7 +1210,7 @@ HalEndSystemInterrupt(IN KIRQL OldIrql,
{ {
/* Check for in-service delayed interrupt */ /* Check for in-service delayed interrupt */
if (Pcr->IrrActive & 0xFFFFFFF0) return; if (Pcr->IrrActive & 0xFFFFFFF0) return;
/* Loop checking for pending interrupts */ /* Loop checking for pending interrupts */
while (TRUE) while (TRUE)
{ {
@ -1222,21 +1222,21 @@ HalEndSystemInterrupt(IN KIRQL OldIrql,
Mask.Both = Pcr->IDR & 0xFFFF; Mask.Both = Pcr->IDR & 0xFFFF;
__outbyte(PIC1_DATA_PORT, Mask.Master); __outbyte(PIC1_DATA_PORT, Mask.Master);
__outbyte(PIC2_DATA_PORT, Mask.Slave); __outbyte(PIC2_DATA_PORT, Mask.Slave);
/* Now check if this specific interrupt is already in-service */ /* Now check if this specific interrupt is already in-service */
PendingIrqMask = (1 << PendingIrql); PendingIrqMask = (1 << PendingIrql);
if (Pcr->IrrActive & PendingIrqMask) return; if (Pcr->IrrActive & PendingIrqMask) return;
/* Set active bit otherwise, and clear it from IRR */ /* Set active bit otherwise, and clear it from IRR */
Pcr->IrrActive |= PendingIrqMask; Pcr->IrrActive |= PendingIrqMask;
Pcr->IRR ^= PendingIrqMask; Pcr->IRR ^= PendingIrqMask;
/* Handle delayed hardware interrupt */ /* Handle delayed hardware interrupt */
SWInterruptHandlerTable[PendingIrql](); SWInterruptHandlerTable[PendingIrql]();
/* Handling complete */ /* Handling complete */
Pcr->IrrActive ^= PendingIrqMask; Pcr->IrrActive ^= PendingIrqMask;
/* Check if there's still interrupts pending */ /* Check if there's still interrupts pending */
PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql]; PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[Pcr->Irql];
if (!PendingIrqlMask) break; if (!PendingIrqlMask) break;
@ -1259,7 +1259,7 @@ _HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame)
{ {
KIRQL CurrentIrql; KIRQL CurrentIrql;
PKPCR Pcr = KeGetPcr(); PKPCR Pcr = KeGetPcr();
/* Save the current IRQL and update it */ /* Save the current IRQL and update it */
CurrentIrql = Pcr->Irql; CurrentIrql = Pcr->Irql;
Pcr->Irql = APC_LEVEL; Pcr->Irql = APC_LEVEL;
@ -1300,10 +1300,10 @@ HalpApcInterruptHandler(IN PKTRAP_FRAME TrapFrame)
TrapFrame->EFlags = __readeflags(); TrapFrame->EFlags = __readeflags();
TrapFrame->SegCs = KGDT_R0_CODE; TrapFrame->SegCs = KGDT_R0_CODE;
TrapFrame->Eip = TrapFrame->Eax; TrapFrame->Eip = TrapFrame->Eax;
/* Build the trap frame */ /* Build the trap frame */
KiEnterInterruptTrap(TrapFrame); KiEnterInterruptTrap(TrapFrame);
/* Do the work */ /* Do the work */
_HalpApcInterruptHandler(TrapFrame); _HalpApcInterruptHandler(TrapFrame);
} }
@ -1314,19 +1314,19 @@ _HalpDispatchInterruptHandler(VOID)
{ {
KIRQL CurrentIrql; KIRQL CurrentIrql;
PKPCR Pcr = KeGetPcr(); PKPCR Pcr = KeGetPcr();
/* Save the current IRQL and update it */ /* Save the current IRQL and update it */
CurrentIrql = Pcr->Irql; CurrentIrql = Pcr->Irql;
Pcr->Irql = DISPATCH_LEVEL; Pcr->Irql = DISPATCH_LEVEL;
/* Remove DPC from IRR */ /* Remove DPC from IRR */
Pcr->IRR &= ~(1 << DISPATCH_LEVEL); Pcr->IRR &= ~(1 << DISPATCH_LEVEL);
/* Enable interrupts and call the kernel's DPC interrupt handler */ /* Enable interrupts and call the kernel's DPC interrupt handler */
_enable(); _enable();
KiDispatchInterrupt(); KiDispatchInterrupt();
_disable(); _disable();
/* Return IRQL */ /* Return IRQL */
return CurrentIrql; return CurrentIrql;
} }
@ -1337,13 +1337,13 @@ FASTCALL
HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame) HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame)
{ {
KIRQL CurrentIrql; KIRQL CurrentIrql;
/* Do the work */ /* Do the work */
CurrentIrql = _HalpDispatchInterruptHandler(); CurrentIrql = _HalpDispatchInterruptHandler();
/* End the interrupt */ /* End the interrupt */
HalpEndSoftwareInterrupt(CurrentIrql, TrapFrame); HalpEndSoftwareInterrupt(CurrentIrql, TrapFrame);
/* Exit the interrupt */ /* Exit the interrupt */
KiEoiHelper(TrapFrame); KiEoiHelper(TrapFrame);
} }
@ -1358,7 +1358,7 @@ HalpDispatchInterrupt2(VOID)
/* Do the work */ /* Do the work */
OldIrql = _HalpDispatchInterruptHandler(); OldIrql = _HalpDispatchInterruptHandler();
/* Restore IRQL */ /* Restore IRQL */
Pcr->Irql = OldIrql; Pcr->Irql = OldIrql;
@ -1374,7 +1374,7 @@ HalpDispatchInterrupt2(VOID)
Mask.Both = Pcr->IDR & 0xFFFF; Mask.Both = Pcr->IDR & 0xFFFF;
__outbyte(PIC1_DATA_PORT, Mask.Master); __outbyte(PIC1_DATA_PORT, Mask.Master);
__outbyte(PIC2_DATA_PORT, Mask.Slave); __outbyte(PIC2_DATA_PORT, Mask.Slave);
/* Clear IRR bit */ /* Clear IRR bit */
Pcr->IRR ^= (1 << PendingIrql); Pcr->IRR ^= (1 << PendingIrql);
} }