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[UNIATA]
Update to 0.45c1. svn path=/trunk/; revision=65108
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@ -4019,10 +4019,15 @@ AtapiEnableInterrupts(
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//}
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}
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chan->ChannelCtrlFlags &= ~CTRFLAGS_INTR_DISABLED;
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} else {
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if(deviceExtension->HwFlags & UNIATA_AHCI) {
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// keep interrupts disabled
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UniataAhciWriteChannelPort4(chan, IDX_AHCI_P_IE, 0);
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} else {
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AtapiWritePort1(chan, IDX_IO2_o_Control,
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IDE_DC_DISABLE_INTERRUPTS /*| IDE_DC_A_4BIT*/ );
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}
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}
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return;
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} // end AtapiEnableInterrupts()
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@ -522,7 +522,8 @@ unknown_dev:
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ScsiPortFreeDeviceBase(HwDeviceExtension,
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deviceExtension->BaseIoAddressBM_0);
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deviceExtension->BaseIoAddressBM_0 = 0;
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deviceExtension->BaseIoAddressBM_0.Addr = 0;
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deviceExtension->BaseIoAddressBM_0.MemIo = 0;
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deviceExtension->BusMaster = DMA_MODE_NONE;
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deviceExtension->MaxTransferMode = ATA_PIO4;
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break;
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@ -1170,22 +1171,61 @@ for_ugly_chips:
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break;
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}
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if(deviceExtension->MaxTransferMode >= ATA_SA150) {
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BOOLEAN OrigAHCI = FALSE;
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GetPciConfig1(0x90, tmp8);
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KdPrint2((PRINT_PREFIX "Intel chip config: %x\n", tmp8));
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/* SATA parts can be either compat or AHCI */
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MemIo = FALSE;
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if(ChipFlags & UNIATA_AHCI) {
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OrigAHCI = TRUE;
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if(tmp8 & 0xc0) {
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//KdPrint2((PRINT_PREFIX "AHCI not supported yet\n"));
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//return FALSE;
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KdPrint2((PRINT_PREFIX "try run AHCI\n"));
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break;
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}
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KdPrint2((PRINT_PREFIX "Compatible mode\n"));
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BaseIoAddressBM = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
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4, 0, sizeof(IDE_BUSMASTER_REGISTERS));
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if(BaseIoAddressBM) {
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KdPrint2((PRINT_PREFIX "Intel BM check at %x\n", BaseIoAddressBM));
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/* check if we really have valid BM registers */
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if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
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KdPrint2((PRINT_PREFIX "MemIo[4]\n"));
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MemIo = TRUE;
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}
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deviceExtension->BaseIoAddressBM_0.Addr = BaseIoAddressBM;
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deviceExtension->BaseIoAddressBM_0.MemIo = MemIo;
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tmp8 = AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),IDX_BM_Status);
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KdPrint2((PRINT_PREFIX "BM status: %x\n", tmp8));
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/* cleanup */
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ScsiPortFreeDeviceBase(HwDeviceExtension, (PCHAR)BaseIoAddressBM);
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deviceExtension->BaseIoAddressBM_0.Addr = 0;
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deviceExtension->BaseIoAddressBM_0.MemIo = 0;
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if(tmp8 == 0xff) {
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KdPrint2((PRINT_PREFIX "invalid BM status, keep AHCI mode\n"));
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break;
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}
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}
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KdPrint2((PRINT_PREFIX "Compatible mode, reallocate LUNs\n"));
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deviceExtension->NumberLuns = 2; // we may be in Legacy mode
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if(!UniataAllocateLunExt(deviceExtension, 2)) {
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KdPrint2((PRINT_PREFIX "can't re-allocate Luns\n"));
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return STATUS_UNSUCCESSFUL;
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}
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}
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deviceExtension->HwFlags &= ~UNIATA_AHCI;
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MemIo = FALSE;
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/* if BAR(5) is IO it should point to SATA interface registers */
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if(OrigAHCI) {
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/* Skip BAR(5) in compatible mode */
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KdPrint2((PRINT_PREFIX "Ignore BAR5 on compatible\n"));
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BaseMemAddress = 0;
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} else
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if(deviceExtension->DevID == 0x28288086 &&
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pciData->u.type0.SubVendorID == 0x106b) {
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/* Skip BAR(5) on ICH8M Apples, system locks up on access. */
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@ -1195,7 +1235,7 @@ for_ugly_chips:
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BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
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5, 0, 0x10);
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if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
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KdPrint2((PRINT_PREFIX "MemIo\n"));
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KdPrint2((PRINT_PREFIX "MemIo[5]\n"));
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MemIo = TRUE;
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}
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}
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@ -1,10 +1,10 @@
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#define UNIATA_VER_STR "45b1"
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#define UNIATA_VER_DOT 0.45.2.1
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#define UNIATA_VER_STR "45c1"
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#define UNIATA_VER_DOT 0.45.3.1
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#define UNIATA_VER_MJ 0
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#define UNIATA_VER_MN 45
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#define UNIATA_VER_SUB_MJ 2
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#define UNIATA_VER_SUB_MN 1
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#define UNIATA_VER_DOT_COMMA 0,45,2,1
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#define UNIATA_VER_DOT_STR "0.45.2.1"
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#define UNIATA_VER_DOT_COMMA 0,45,3,1
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#define UNIATA_VER_DOT_STR "0.45.3.1"
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#define UNIATA_VER_YEAR 2014
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#define UNIATA_VER_YEAR_STR "2014"
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