Update to 0.45c1.

svn path=/trunk/; revision=65108
This commit is contained in:
Sylvain Petreolle 2014-10-29 21:34:01 +00:00
parent a65c5549f9
commit a1baaa2225
3 changed files with 54 additions and 9 deletions

View file

@ -4020,8 +4020,13 @@ AtapiEnableInterrupts(
}
chan->ChannelCtrlFlags &= ~CTRFLAGS_INTR_DISABLED;
} else {
AtapiWritePort1(chan, IDX_IO2_o_Control,
if(deviceExtension->HwFlags & UNIATA_AHCI) {
// keep interrupts disabled
UniataAhciWriteChannelPort4(chan, IDX_AHCI_P_IE, 0);
} else {
AtapiWritePort1(chan, IDX_IO2_o_Control,
IDE_DC_DISABLE_INTERRUPTS /*| IDE_DC_A_4BIT*/ );
}
}
return;
} // end AtapiEnableInterrupts()

View file

@ -522,7 +522,8 @@ unknown_dev:
ScsiPortFreeDeviceBase(HwDeviceExtension,
deviceExtension->BaseIoAddressBM_0);
deviceExtension->BaseIoAddressBM_0 = 0;
deviceExtension->BaseIoAddressBM_0.Addr = 0;
deviceExtension->BaseIoAddressBM_0.MemIo = 0;
deviceExtension->BusMaster = DMA_MODE_NONE;
deviceExtension->MaxTransferMode = ATA_PIO4;
break;
@ -1170,22 +1171,61 @@ for_ugly_chips:
break;
}
if(deviceExtension->MaxTransferMode >= ATA_SA150) {
BOOLEAN OrigAHCI = FALSE;
GetPciConfig1(0x90, tmp8);
KdPrint2((PRINT_PREFIX "Intel chip config: %x\n", tmp8));
/* SATA parts can be either compat or AHCI */
MemIo = FALSE;
if(ChipFlags & UNIATA_AHCI) {
OrigAHCI = TRUE;
if(tmp8 & 0xc0) {
//KdPrint2((PRINT_PREFIX "AHCI not supported yet\n"));
//return FALSE;
KdPrint2((PRINT_PREFIX "try run AHCI\n"));
break;
}
KdPrint2((PRINT_PREFIX "Compatible mode\n"));
BaseIoAddressBM = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
4, 0, sizeof(IDE_BUSMASTER_REGISTERS));
if(BaseIoAddressBM) {
KdPrint2((PRINT_PREFIX "Intel BM check at %x\n", BaseIoAddressBM));
/* check if we really have valid BM registers */
if((*ConfigInfo->AccessRanges)[4].RangeInMemory) {
KdPrint2((PRINT_PREFIX "MemIo[4]\n"));
MemIo = TRUE;
}
deviceExtension->BaseIoAddressBM_0.Addr = BaseIoAddressBM;
deviceExtension->BaseIoAddressBM_0.MemIo = MemIo;
tmp8 = AtapiReadPortEx1(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),IDX_BM_Status);
KdPrint2((PRINT_PREFIX "BM status: %x\n", tmp8));
/* cleanup */
ScsiPortFreeDeviceBase(HwDeviceExtension, (PCHAR)BaseIoAddressBM);
deviceExtension->BaseIoAddressBM_0.Addr = 0;
deviceExtension->BaseIoAddressBM_0.MemIo = 0;
if(tmp8 == 0xff) {
KdPrint2((PRINT_PREFIX "invalid BM status, keep AHCI mode\n"));
break;
}
}
KdPrint2((PRINT_PREFIX "Compatible mode, reallocate LUNs\n"));
deviceExtension->NumberLuns = 2; // we may be in Legacy mode
if(!UniataAllocateLunExt(deviceExtension, 2)) {
KdPrint2((PRINT_PREFIX "can't re-allocate Luns\n"));
return STATUS_UNSUCCESSFUL;
}
}
deviceExtension->HwFlags &= ~UNIATA_AHCI;
MemIo = FALSE;
/* if BAR(5) is IO it should point to SATA interface registers */
if(OrigAHCI) {
/* Skip BAR(5) in compatible mode */
KdPrint2((PRINT_PREFIX "Ignore BAR5 on compatible\n"));
BaseMemAddress = 0;
} else
if(deviceExtension->DevID == 0x28288086 &&
pciData->u.type0.SubVendorID == 0x106b) {
/* Skip BAR(5) on ICH8M Apples, system locks up on access. */
@ -1195,7 +1235,7 @@ for_ugly_chips:
BaseMemAddress = AtapiGetIoRange(HwDeviceExtension, ConfigInfo, pciData, SystemIoBusNumber,
5, 0, 0x10);
if(BaseMemAddress && (*ConfigInfo->AccessRanges)[5].RangeInMemory) {
KdPrint2((PRINT_PREFIX "MemIo\n"));
KdPrint2((PRINT_PREFIX "MemIo[5]\n"));
MemIo = TRUE;
}
}

View file

@ -1,10 +1,10 @@
#define UNIATA_VER_STR "45b1"
#define UNIATA_VER_DOT 0.45.2.1
#define UNIATA_VER_STR "45c1"
#define UNIATA_VER_DOT 0.45.3.1
#define UNIATA_VER_MJ 0
#define UNIATA_VER_MN 45
#define UNIATA_VER_SUB_MJ 2
#define UNIATA_VER_SUB_MN 1
#define UNIATA_VER_DOT_COMMA 0,45,2,1
#define UNIATA_VER_DOT_STR "0.45.2.1"
#define UNIATA_VER_DOT_COMMA 0,45,3,1
#define UNIATA_VER_DOT_STR "0.45.3.1"
#define UNIATA_VER_YEAR 2014
#define UNIATA_VER_YEAR_STR "2014"