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[NDK]: Fix definition of ARM PTE/PDE structure.

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[NTOS]: Fix up ARM code to match recent ARM3 changes.
[NTOS]: Do not use initguid inside every single file to zillionplicate the GUIDs! Why doesn't the x86 linker catch this?!!?
[ARMDDK]: Define some spinlock functions.

svn path=/trunk/; revision=49780
This commit is contained in:
Sir Richard 2010-11-24 17:26:30 +00:00
parent 85adb4ff80
commit a19af9c7cb
10 changed files with 189 additions and 121 deletions
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2
reactos/boot/freeldr/freeldr/windows/arm/wlmemory.c
View file

@ -200,7 +200,7 @@ MempAllocatePageTables(VOID)
PFN_NUMBER Pfn;
/* Setup templates */
TempPte.Accessed = TempPte.Valid = TempLargePte.LargePage = TempLargePte.Accessed = TempPde.Valid = 1;
TempPte.Sbo = TempPte.Valid = TempLargePte.LargePage = TempLargePte.Sbo = TempPde.Valid = 1;
/* Allocate the 1MB "PDR" (Processor Data Region). Must be 1MB aligned */
PdrPage = MmAllocateMemoryAtAddress(sizeof(KPDR_PAGE),

2
reactos/include/ddk/wdm.h
View file

@ -9726,7 +9726,7 @@ KeQuerySystemTime(
OUT PLARGE_INTEGER CurrentTime);
#endif /* !_M_AMD64 */
#if !defined(_X86_)
#if !defined(_X86_) && !defined(_M_ARM)
NTKERNELAPI
KIRQL
NTAPI

74
reactos/include/ndk/arm/mmtypes.h
View file

@ -68,7 +68,7 @@ typedef struct _HARDWARE_LARGE_PTE_ARMV6
ULONG NoExecute:1;
ULONG Domain:4;
ULONG Ecc:1;
ULONG Accessed:1;
ULONG Sbo:1;
ULONG Owner:1;
ULONG CacheAttributes:3;
ULONG ReadOnly:1;
@ -85,7 +85,7 @@ typedef struct _HARDWARE_PTE_ARMV6
ULONG Valid:1;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Accessed:1;
ULONG Sbo:1;
ULONG Owner:1;
ULONG CacheAttributes:3;
ULONG ReadOnly:1;
@ -100,9 +100,9 @@ C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG));
typedef struct _MMPTE_SOFTWARE
{
ULONG Valid:1;
ULONG Valid:2;
ULONG PageFileLow:4;
ULONG Protection:5;
ULONG Protection:4;
ULONG Prototype:1;
ULONG Transition:1;
ULONG PageFileHigh:20;
@ -110,12 +110,12 @@ typedef struct _MMPTE_SOFTWARE
typedef struct _MMPTE_TRANSITION
{
ULONG Valid:1;
ULONG Write:1;
ULONG Valid:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Owner:1;
ULONG WriteThrough:1;
ULONG CacheDisable:1;
ULONG Protection:5;
ULONG Protection:4;
ULONG ReadOnly:1;
ULONG Prototype:1;
ULONG Transition:1;
ULONG PageFrameNumber:20;
@ -123,19 +123,18 @@ typedef struct _MMPTE_TRANSITION
typedef struct _MMPTE_PROTOTYPE
{
ULONG Valid:1;
ULONG Valid:2;
ULONG ProtoAddressLow:7;
ULONG ReadOnly:1;
ULONG WhichPool:1;
ULONG Prototype:1;
ULONG ProtoAddressHigh:21;
} MMPTE_PROTOTYPE;
typedef struct _MMPTE_SUBSECTION
{
ULONG Valid:1;
ULONG Valid:2;
ULONG SubsectionAddressLow:4;
ULONG Protection:5;
ULONG Protection:4;
ULONG Prototype:1;
ULONG SubsectionAddressHigh:20;
ULONG WhichPool:1;
@ -143,47 +142,38 @@ typedef struct _MMPTE_SUBSECTION
typedef struct _MMPTE_LIST
{
ULONG Valid:1;
ULONG Valid:2;
ULONG OneEntry:1;
ULONG filler0:8;
ULONG NextEntry:20;
ULONG Prototype:1;
ULONG filler1:1;
} MMPTE_LIST;
typedef union _MMPTE_HARDWARE
{
struct
{
ULONG NoExecute:1;
ULONG Valid:1;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Access:1;
ULONG Owner:1;
ULONG CacheAttributes:3;
ULONG ReadOnly:1;
ULONG Shared:1;
ULONG NonGlobal:1;
ULONG PageFrameNumber:20;
};
ULONG AsUlong;
ULONG NoExecute:1;
ULONG Valid:1;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Sbo:1;
ULONG Owner:1;
ULONG CacheAttributes:3;
ULONG ReadOnly:1;
ULONG Prototype:1;
ULONG NonGlobal:1;
ULONG PageFrameNumber:20;
} MMPTE_HARDWARE, *PMMPTE_HARDWARE;
typedef union _MMPDE_HARDWARE
{
struct
{
ULONG Valid:1;
ULONG LargePage:1;
ULONG Buffered:1;
ULONG Cached:1;
ULONG NoExecute:1;
ULONG Domain:4;
ULONG Ecc:1;
ULONG PageFrameNumber:22;
};
ULONG AsUlong;
ULONG Valid:1;
ULONG LargePage:1;
ULONG Buffered:1;
ULONG Cached:1;
ULONG NoExecute:1;
ULONG Domain:4;
ULONG Ecc:1;
ULONG PageFrameNumber:22;
} MMPDE_HARDWARE, *PMMPDE_HARDWARE;
typedef struct _MMPDE

29
reactos/include/reactos/arm/armddk.h
View file

@ -252,6 +252,35 @@ KeRaiseIrqlToDpcLevel(
#define KeLowerIrql(NewIrql) KfLowerIrql(NewIrql)
#define KeRaiseIrql(NewIrql, OldIrql) *(OldIrql) = KfRaiseIrql(NewIrql)
NTHALAPI
KIRQL
FASTCALL
KfAcquireSpinLock(
IN OUT PKSPIN_LOCK SpinLock);
#define KeAcquireSpinLock(a,b) *(b) = KfAcquireSpinLock(a)
NTHALAPI
VOID
FASTCALL
KfReleaseSpinLock(
IN OUT PKSPIN_LOCK SpinLock,
IN KIRQL NewIrql);
#define KeReleaseSpinLock(a,b) KfReleaseSpinLock(a,b)
NTKERNELAPI
VOID
FASTCALL
KefAcquireSpinLockAtDpcLevel(
IN OUT PKSPIN_LOCK SpinLock);
#define KeAcquireSpinLockAtDpcLevel(SpinLock) KefAcquireSpinLockAtDpcLevel(SpinLock)
NTKERNELAPI
VOID
FASTCALL
KefReleaseSpinLockFromDpcLevel(
IN OUT PKSPIN_LOCK SpinLock);
#define KeReleaseSpinLockFromDpcLevel(SpinLock) KefReleaseSpinLockFromDpcLevel(SpinLock)
//
// Cache clean and flush
//

2
reactos/ntoskrnl/include/internal/po.h
View file

@ -6,7 +6,7 @@
* PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
*/
#include "initguid.h"
#include <guiddef.h>
#include <poclass.h>
//

13
reactos/ntoskrnl/mm/ARM3/arm/init.c
View file

@ -24,10 +24,7 @@ ULONG MmMaximumNonPagedPoolInBytes;
PVOID MmNonPagedSystemStart;
PVOID MmNonPagedPoolStart;
PVOID MmNonPagedPoolExpansionStart;
PVOID MmNonPagedPoolEnd = MI_NONPAGED_POOL_END;
PVOID MmPagedPoolStart = MI_PAGED_POOL_START;
PVOID MmPagedPoolEnd;
ULONG MmSizeOfPagedPoolInBytes = MI_MIN_INIT_PAGED_POOLSIZE;
PVOID MiSessionSpaceEnd;
PVOID MiSessionImageEnd;
PVOID MiSessionImageStart;
@ -49,7 +46,7 @@ RTL_BITMAP MiPfnBitMap;
PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
ULONG MmNumberOfPhysicalPages, MmHighestPhysicalPage, MmLowestPhysicalPage = -1;
ULONG MmNumberOfPhysicalPages, MmHighestPhysicalPage;
ULONG MmBootImageSize;
ULONG MmUserProbeAddress;
PVOID MmHighestUserAddress;
@ -61,17 +58,17 @@ PVOID MmHyperSpaceEnd;
/* PRIVATE FUNCTIONS **********************************************************/
BOOLEAN
NTSTATUS
NTAPI
MmArmInitSystem(IN ULONG Phase,
IN PLOADER_PARAMETER_BLOCK LoaderBlock)
INIT_FUNCTION
MiInitMachineDependent(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
{
//
// Always return success for now
//
DPRINT1("NEVER TELL ME THE ODDS!\n");
while (TRUE);
return TRUE;
return STATUS_SUCCESS;
}
/* EOF */

20
reactos/ntoskrnl/mm/ARM3/miarm.h
View file

@ -130,12 +130,12 @@ C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
//
// Access Flags
//
#define PTE_READONLY 0
#define PTE_READONLY 0 // Doesn't exist on x86
#define PTE_EXECUTE 0 // Not worrying about NX yet
#define PTE_EXECUTE_READ 0 // Not worrying about NX yet
#define PTE_READWRITE 0x2
#define PTE_WRITECOPY 0x200
#define PTE_EXECUTE_READWRITE 0x0
#define PTE_EXECUTE_READWRITE 0x2 // Not worrying about NX yet
#define PTE_EXECUTE_WRITECOPY 0x200
#define PTE_PROTOTYPE 0x400
//
@ -145,6 +145,20 @@ C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
#define PTE_DISABLE_CACHE 0x10
#define PTE_WRITECOMBINED_CACHE 0x10
#elif defined(_M_ARM)
#define PTE_READONLY 0x200
#define PTE_EXECUTE 0 // Not worrying about NX yet
#define PTE_EXECUTE_READ 0 // Not worrying about NX yet
#define PTE_READWRITE 0 // Doesn't exist on ARM
#define PTE_WRITECOPY 0 // Doesn't exist on ARM
#define PTE_EXECUTE_READWRITE 0 // Not worrying about NX yet
#define PTE_EXECUTE_WRITECOPY 0 // Not worrying about NX yet
#define PTE_PROTOTYPE 0x400 // Using the Shared bit
//
// Cache flags
//
#define PTE_ENABLE_CACHE 0
#define PTE_DISABLE_CACHE 0x10
#define PTE_WRITECOMBINED_CACHE 0x10
#else
#error Define these please!
#endif
@ -179,7 +193,7 @@ extern const ULONG MmProtectToValue[32];
#ifdef _M_IX86
#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
#elif _M_ARM
#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
#define MM_PTE_SOFTWARE_PROTECTION_BITS 6
#elif _M_AMD64
#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
#else

131
reactos/ntoskrnl/mm/arm/page.c
View file

@ -12,10 +12,111 @@
#define NDEBUG
#include <debug.h>
#line 15 "ARM³::ARMPAGE"
#define MODULE_INVOLVED_IN_ARM3
#include "../ARM3/miarm.h"
/* GLOBALS ********************************************************************/
const
ULONG
MmProtectToPteMask[32] =
{
//
// These are the base MM_ protection flags
//
0,
PTE_READONLY | PTE_ENABLE_CACHE,
PTE_EXECUTE | PTE_ENABLE_CACHE,
PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
PTE_READWRITE | PTE_ENABLE_CACHE,
PTE_WRITECOPY | PTE_ENABLE_CACHE,
PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
//
// These OR in the MM_NOCACHE flag
//
0,
PTE_READONLY | PTE_DISABLE_CACHE,
PTE_EXECUTE | PTE_DISABLE_CACHE,
PTE_EXECUTE_READ | PTE_DISABLE_CACHE,
PTE_READWRITE | PTE_DISABLE_CACHE,
PTE_WRITECOPY | PTE_DISABLE_CACHE,
PTE_EXECUTE_READWRITE | PTE_DISABLE_CACHE,
PTE_EXECUTE_WRITECOPY | PTE_DISABLE_CACHE,
//
// These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM
//
0,
PTE_READONLY | PTE_ENABLE_CACHE,
PTE_EXECUTE | PTE_ENABLE_CACHE,
PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
PTE_READWRITE | PTE_ENABLE_CACHE,
PTE_WRITECOPY | PTE_ENABLE_CACHE,
PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
//
// These OR in the MM_NOACCESS flag, which seems to enable WriteCombining?
//
0,
PTE_READONLY | PTE_WRITECOMBINED_CACHE,
PTE_EXECUTE | PTE_WRITECOMBINED_CACHE,
PTE_EXECUTE_READ | PTE_WRITECOMBINED_CACHE,
PTE_READWRITE | PTE_WRITECOMBINED_CACHE,
PTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
PTE_EXECUTE_READWRITE | PTE_WRITECOMBINED_CACHE,
PTE_EXECUTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
};
const
ULONG MmProtectToValue[32] =
{
PAGE_NOACCESS,
PAGE_READONLY,
PAGE_EXECUTE,
PAGE_EXECUTE_READ,
PAGE_READWRITE,
PAGE_WRITECOPY,
PAGE_EXECUTE_READWRITE,
PAGE_EXECUTE_WRITECOPY,
PAGE_NOACCESS,
PAGE_NOCACHE | PAGE_READONLY,
PAGE_NOCACHE | PAGE_EXECUTE,
PAGE_NOCACHE | PAGE_EXECUTE_READ,
PAGE_NOCACHE | PAGE_READWRITE,
PAGE_NOCACHE | PAGE_WRITECOPY,
PAGE_NOCACHE | PAGE_EXECUTE_READWRITE,
PAGE_NOCACHE | PAGE_EXECUTE_WRITECOPY,
PAGE_NOACCESS,
PAGE_GUARD | PAGE_READONLY,
PAGE_GUARD | PAGE_EXECUTE,
PAGE_GUARD | PAGE_EXECUTE_READ,
PAGE_GUARD | PAGE_READWRITE,
PAGE_GUARD | PAGE_WRITECOPY,
PAGE_GUARD | PAGE_EXECUTE_READWRITE,
PAGE_GUARD | PAGE_EXECUTE_WRITECOPY,
PAGE_NOACCESS,
PAGE_WRITECOMBINE | PAGE_READONLY,
PAGE_WRITECOMBINE | PAGE_EXECUTE,
PAGE_WRITECOMBINE | PAGE_EXECUTE_READ,
PAGE_WRITECOMBINE | PAGE_READWRITE,
PAGE_WRITECOMBINE | PAGE_WRITECOPY,
PAGE_WRITECOMBINE | PAGE_EXECUTE_READWRITE,
PAGE_WRITECOMBINE | PAGE_EXECUTE_WRITECOPY
};
ULONG MmGlobalKernelPageDirectory[4096];
MMPDE HyperTemplatePde;
/* Template PTE and PDE for a kernel page */
MMPDE ValidKernelPde = {.u.Hard.Valid = 1};
MMPTE ValidKernelPte = {.u.Hard.Valid = 1, .u.Hard.Sbo = 1};
/* Template PDE for a demand-zero page */
MMPDE DemandZeroPde = {.u.Long = (MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS)};
MMPTE DemandZeroPte = {.u.Long = (MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS)};
/* Template PTE for prototype page */
MMPTE PrototypePte = {.u.Long = (MM_READWRITE << MM_PTE_SOFTWARE_PROTECTION_BITS) | PTE_PROTOTYPE | (MI_PTE_LOOKUP_NEEDED << PAGE_SHIFT)};
/* PRIVATE FUNCTIONS **********************************************************/
@ -49,25 +150,6 @@ MmUpdatePageDir(IN PEPROCESS Process,
return;
}
NTSTATUS
NTAPI
Mmi386ReleaseMmInfo(IN PEPROCESS Process)
{
UNIMPLEMENTED;
while (TRUE);
return 0;
}
NTSTATUS
NTAPI
MmInitializeHandBuiltProcess(IN PEPROCESS Process,
IN PULONG DirectoryTableBase)
{
UNIMPLEMENTED;
while (TRUE);
return STATUS_SUCCESS;
}
PULONG
NTAPI
MmGetPageDirectory(VOID)
@ -246,16 +328,7 @@ MmInitGlobalKernelPageDirectory(VOID)
{
ULONG i;
PULONG CurrentPageDirectory = (PULONG)PDE_BASE;
extern MMPTE HyperTemplatePte;
/* Setup PTE template */
HyperTemplatePte.u.Long = 0;
HyperTemplatePte.u.Hard.Valid = 1;
HyperTemplatePte.u.Hard.Access = 1;
/* Setup PDE template */
HyperTemplatePde.u.Long = 0;
HyperTemplatePde.u.Hard.Valid = 1;
/* Loop the 2GB of address space which belong to the kernel */
for (i = MiGetPdeOffset(MmSystemRangeStart); i < 2048; i++)

36
reactos/ntoskrnl/mm/arm/stubs.c
View file

@ -367,18 +367,6 @@ MmCreateProcessAddressSpace(IN ULONG MinWs,
return TRUE;
}
VOID
NTAPI
MmUpdatePageDir(IN PEPROCESS Process,
IN PVOID Address,
IN ULONG Size)
{
//
// Nothing to do
//
return;
}
NTSTATUS
NTAPI
Mmi386ReleaseMmInfo(IN PEPROCESS Process)
@ -391,30 +379,6 @@ Mmi386ReleaseMmInfo(IN PEPROCESS Process)
return 0;
}
NTSTATUS
NTAPI
MmInitializeHandBuiltProcess(IN PEPROCESS Process,
IN PULONG DirectoryTableBase)
{
//
// Share the directory base with the idle process
//
DirectoryTableBase[0] = PsGetCurrentProcess()->Pcb.DirectoryTableBase[0];
DirectoryTableBase[1] = PsGetCurrentProcess()->Pcb.DirectoryTableBase[1];
//
// Initialize the Addresss Space
//
KeInitializeGuardedMutex(&Process->AddressCreationLock);
Process->VadRoot.BalancedRoot.u1.Parent = NULL;
//
// The process now has an address space
//
Process->HasAddressSpace = TRUE;
return STATUS_SUCCESS;
}
PULONG
NTAPI
MmGetPageDirectory(VOID)

1
reactos/ntoskrnl/po/power.c
View file

@ -9,6 +9,7 @@
/* INCLUDES ******************************************************************/
#include "initguid.h"
#include <ntoskrnl.h>
#define NDEBUG
#include <debug.h>