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[HAL] Fix build with CONFIG_SMP
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d0f6d2cf6e
commit
a0fb02f7f3
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@ -3,7 +3,7 @@
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* LICENSE: GPL - See COPYING in the top level directory
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: boot/freeldr/freeldr/arch/i386/ntoskrnl.c
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* FILE: boot/freeldr/freeldr/arch/i386/ntoskrnl.c
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* PURPOSE: NTOS glue routines for the MINIHAL library
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* PURPOSE: NTOS glue routines for the MINIHAL library
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* PROGRAMMERS: Hervé Poussineau <hpoussin@reactos.org>
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* PROGRAMMERS: Hervé Poussineau <hpoussin@reactos.org>
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*/
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*/
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/* INCLUDES ******************************************************************/
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/* INCLUDES ******************************************************************/
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@ -25,14 +25,7 @@ KeInitializeEvent(
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VOID
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VOID
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FASTCALL
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FASTCALL
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KiAcquireSpinLock(
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KefAcquireSpinLockAtDpcLevel(
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IN PKSPIN_LOCK SpinLock)
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{
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}
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VOID
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FASTCALL
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KiReleaseSpinLock(
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IN PKSPIN_LOCK SpinLock)
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IN PKSPIN_LOCK SpinLock)
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{
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{
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}
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}
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@ -47,12 +47,12 @@
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#include <drivers/acpi/acpi.h>
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#include <drivers/acpi/acpi.h>
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/* Internal kernel headers */
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/* Internal kernel headers */
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#define KeGetCurrentThread _KeGetCurrentThread
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#ifdef _M_AMD64
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#ifdef _M_AMD64
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#include <internal/amd64/ke.h>
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#include <internal/amd64/ke.h>
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#include <internal/amd64/mm.h>
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#include <internal/amd64/mm.h>
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#include "internal/amd64/intrin_i.h"
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#include "internal/amd64/intrin_i.h"
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#else
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#else
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#define KeGetCurrentThread _KeGetCurrentThread
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#include <internal/i386/ke.h>
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#include <internal/i386/ke.h>
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#include <internal/i386/mm.h>
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#include <internal/i386/mm.h>
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#include "internal/i386/intrin_i.h"
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#include "internal/i386/intrin_i.h"
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@ -566,13 +566,6 @@ HalInitializeBios(
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#define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
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#define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
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#define KiEoiHelper(TrapFrame) return /* Just return to the caller */
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#define KiEoiHelper(TrapFrame) return /* Just return to the caller */
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#define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
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#define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
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#ifndef CONFIG_SMP
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/* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
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#define KiAcquireSpinLock(SpinLock)
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#define KiReleaseSpinLock(SpinLock)
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#define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
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#define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
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#endif // !CONFIG_SMP
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#endif // _M_AMD64
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#endif // _M_AMD64
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extern BOOLEAN HalpNMIInProgress;
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extern BOOLEAN HalpNMIInProgress;
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@ -119,8 +119,8 @@ VOID
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NTAPI
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NTAPI
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HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
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HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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OUT PKIRQL OldIrql,
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IN PPCI_TYPE1_CFG_BITS PciCfg1)
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OUT PPCI_TYPE1_CFG_BITS PciCfg1)
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{
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{
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/* Setup the PCI Configuration Register */
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/* Setup the PCI Configuration Register */
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PciCfg1->u.AsULONG = 0;
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PciCfg1->u.AsULONG = 0;
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@ -130,14 +130,14 @@ HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
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PciCfg1->u.bits.Enable = TRUE;
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PciCfg1->u.bits.Enable = TRUE;
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/* Acquire the lock */
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/* Acquire the lock */
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KeRaiseIrql(HIGH_LEVEL, Irql);
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KeRaiseIrql(HIGH_LEVEL, OldIrql);
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KiAcquireSpinLock(&HalpPCIConfigLock);
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KeAcquireSpinLockAtDpcLevel(&HalpPCIConfigLock);
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}
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}
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VOID
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VOID
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NTAPI
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NTAPI
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HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
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HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql)
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IN KIRQL OldIrql)
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{
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{
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PCI_TYPE1_CFG_BITS PciCfg1;
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PCI_TYPE1_CFG_BITS PciCfg1;
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@ -147,8 +147,7 @@ HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
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PciCfg1.u.AsULONG);
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PciCfg1.u.AsULONG);
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/* Release the lock */
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/* Release the lock */
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KiReleaseSpinLock(&HalpPCIConfigLock);
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KeReleaseSpinLock(&HalpPCIConfigLock, OldIrql);
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KeLowerIrql(Irql);
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}
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}
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TYPE1_READ(HalpPCIReadUcharType1, UCHAR)
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TYPE1_READ(HalpPCIReadUcharType1, UCHAR)
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@ -164,8 +163,8 @@ VOID
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NTAPI
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NTAPI
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HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
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HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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OUT PKIRQL OldIrql,
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IN PPCI_TYPE2_ADDRESS_BITS PciCfg)
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OUT PPCI_TYPE2_ADDRESS_BITS PciCfg)
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{
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{
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PCI_TYPE2_CSE_BITS PciCfg2Cse;
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PCI_TYPE2_CSE_BITS PciCfg2Cse;
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PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
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PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
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@ -176,8 +175,8 @@ HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
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PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
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PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
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/* Acquire the lock */
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/* Acquire the lock */
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KeRaiseIrql(HIGH_LEVEL, Irql);
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KeRaiseIrql(HIGH_LEVEL, OldIrql);
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KiAcquireSpinLock(&HalpPCIConfigLock);
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KeAcquireSpinLockAtDpcLevel(&HalpPCIConfigLock);
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/* Setup the CSE Register */
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/* Setup the CSE Register */
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PciCfg2Cse.u.AsUCHAR = 0;
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PciCfg2Cse.u.AsUCHAR = 0;
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@ -194,7 +193,7 @@ HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
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VOID
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VOID
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NTAPI
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NTAPI
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HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler,
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HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql)
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IN KIRQL OldIrql)
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{
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{
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PCI_TYPE2_CSE_BITS PciCfg2Cse;
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PCI_TYPE2_CSE_BITS PciCfg2Cse;
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PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
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PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
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@ -205,8 +204,7 @@ HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler,
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WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
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WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
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/* Release the lock */
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/* Release the lock */
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KiReleaseSpinLock(&HalpPCIConfigLock);
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KeReleaseSpinLock(&HalpPCIConfigLock, OldIrql);
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KeLowerIrql(Irql);
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}
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}
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TYPE2_READ(HalpPCIReadUcharType2, UCHAR)
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TYPE2_READ(HalpPCIReadUcharType2, UCHAR)
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