Intravision/reactos
1
0
Fork 0
mirror of https://github.com/reactos/reactos.git synced 2024-06-29 17:31:31 +00:00
Code Issues Packages Projects Releases Wiki Activity

[HAL] Fix build with CONFIG_SMP

Browse source
This commit is contained in:
Timo Kreuzer 2021-06-06 15:37:47 +02:00
parent d0f6d2cf6e
commit a0fb02f7f3
4 changed files with 15 additions and 31 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
boot/freeldr/freeldr/arch/i386/ntoskrnl.c
View file

@ -3,7 +3,7 @@
* LICENSE: GPL - See COPYING in the top level directory * LICENSE: GPL - See COPYING in the top level directory
* FILE: boot/freeldr/freeldr/arch/i386/ntoskrnl.c * FILE: boot/freeldr/freeldr/arch/i386/ntoskrnl.c
* PURPOSE: NTOS glue routines for the MINIHAL library * PURPOSE: NTOS glue routines for the MINIHAL library
* PROGRAMMERS: Hervé Poussineau <hpoussin@reactos.org> * PROGRAMMERS: Hervé Poussineau <hpoussin@reactos.org>
*/ */
/* INCLUDES ******************************************************************/ /* INCLUDES ******************************************************************/
@ -25,14 +25,7 @@ KeInitializeEvent(
VOID VOID
FASTCALL FASTCALL
KiAcquireSpinLock( KefAcquireSpinLockAtDpcLevel(
IN PKSPIN_LOCK SpinLock)
{
}
VOID
FASTCALL
KiReleaseSpinLock(
IN PKSPIN_LOCK SpinLock) IN PKSPIN_LOCK SpinLock)
{ {
} }

2
hal/halx86/include/hal.h
View file

@ -47,12 +47,12 @@
#include <drivers/acpi/acpi.h> #include <drivers/acpi/acpi.h>
/* Internal kernel headers */ /* Internal kernel headers */
#define KeGetCurrentThread _KeGetCurrentThread
#ifdef _M_AMD64 #ifdef _M_AMD64
#include <internal/amd64/ke.h> #include <internal/amd64/ke.h>
#include <internal/amd64/mm.h> #include <internal/amd64/mm.h>
#include "internal/amd64/intrin_i.h" #include "internal/amd64/intrin_i.h"
#else #else
#define KeGetCurrentThread _KeGetCurrentThread
#include <internal/i386/ke.h> #include <internal/i386/ke.h>
#include <internal/i386/mm.h> #include <internal/i386/mm.h>
#include "internal/i386/intrin_i.h" #include "internal/i386/intrin_i.h"

7
hal/halx86/include/halp.h
View file

@ -566,13 +566,6 @@ HalInitializeBios(
#define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */ #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
#define KiEoiHelper(TrapFrame) return /* Just return to the caller */ #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
#define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE) #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
#ifndef CONFIG_SMP
/* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
#define KiAcquireSpinLock(SpinLock)
#define KiReleaseSpinLock(SpinLock)
#define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
#define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
#endif // !CONFIG_SMP
#endif // _M_AMD64 #endif // _M_AMD64
extern BOOLEAN HalpNMIInProgress; extern BOOLEAN HalpNMIInProgress;

26
hal/halx86/legacy/bus/pcibus.c
View file

@ -119,8 +119,8 @@ VOID
NTAPI NTAPI
HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler, HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot, IN PCI_SLOT_NUMBER Slot,
IN PKIRQL Irql, OUT PKIRQL OldIrql,
IN PPCI_TYPE1_CFG_BITS PciCfg1) OUT PPCI_TYPE1_CFG_BITS PciCfg1)
{ {
/* Setup the PCI Configuration Register */ /* Setup the PCI Configuration Register */
PciCfg1->u.AsULONG = 0; PciCfg1->u.AsULONG = 0;
@ -130,14 +130,14 @@ HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
PciCfg1->u.bits.Enable = TRUE; PciCfg1->u.bits.Enable = TRUE;
/* Acquire the lock */ /* Acquire the lock */
KeRaiseIrql(HIGH_LEVEL, Irql); KeRaiseIrql(HIGH_LEVEL, OldIrql);
KiAcquireSpinLock(&HalpPCIConfigLock); KeAcquireSpinLockAtDpcLevel(&HalpPCIConfigLock);
} }
VOID VOID
NTAPI NTAPI
HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler, HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
IN KIRQL Irql) IN KIRQL OldIrql)
{ {
PCI_TYPE1_CFG_BITS PciCfg1; PCI_TYPE1_CFG_BITS PciCfg1;
@ -147,8 +147,7 @@ HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
PciCfg1.u.AsULONG); PciCfg1.u.AsULONG);
/* Release the lock */ /* Release the lock */
KiReleaseSpinLock(&HalpPCIConfigLock); KeReleaseSpinLock(&HalpPCIConfigLock, OldIrql);
KeLowerIrql(Irql);
} }
TYPE1_READ(HalpPCIReadUcharType1, UCHAR) TYPE1_READ(HalpPCIReadUcharType1, UCHAR)
@ -164,8 +163,8 @@ VOID
NTAPI NTAPI
HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler, HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot, IN PCI_SLOT_NUMBER Slot,
IN PKIRQL Irql, OUT PKIRQL OldIrql,
IN PPCI_TYPE2_ADDRESS_BITS PciCfg) OUT PPCI_TYPE2_ADDRESS_BITS PciCfg)
{ {
PCI_TYPE2_CSE_BITS PciCfg2Cse; PCI_TYPE2_CSE_BITS PciCfg2Cse;
PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData; PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
@ -176,8 +175,8 @@ HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base; PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
/* Acquire the lock */ /* Acquire the lock */
KeRaiseIrql(HIGH_LEVEL, Irql); KeRaiseIrql(HIGH_LEVEL, OldIrql);
KiAcquireSpinLock(&HalpPCIConfigLock); KeAcquireSpinLockAtDpcLevel(&HalpPCIConfigLock);
/* Setup the CSE Register */ /* Setup the CSE Register */
PciCfg2Cse.u.AsUCHAR = 0; PciCfg2Cse.u.AsUCHAR = 0;
@ -194,7 +193,7 @@ HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
VOID VOID
NTAPI NTAPI
HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler, HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler,
IN KIRQL Irql) IN KIRQL OldIrql)
{ {
PCI_TYPE2_CSE_BITS PciCfg2Cse; PCI_TYPE2_CSE_BITS PciCfg2Cse;
PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData; PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
@ -205,8 +204,7 @@ HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler,
WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0); WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
/* Release the lock */ /* Release the lock */
KiReleaseSpinLock(&HalpPCIConfigLock); KeReleaseSpinLock(&HalpPCIConfigLock, OldIrql);
KeLowerIrql(Irql);
} }
TYPE2_READ(HalpPCIReadUcharType2, UCHAR) TYPE2_READ(HalpPCIReadUcharType2, UCHAR)