[HAL] Fix build with CONFIG_SMP

This commit is contained in:
Timo Kreuzer 2021-06-06 15:37:47 +02:00
parent d0f6d2cf6e
commit a0fb02f7f3
4 changed files with 15 additions and 31 deletions

View file

@ -3,7 +3,7 @@
* LICENSE: GPL - See COPYING in the top level directory
* FILE: boot/freeldr/freeldr/arch/i386/ntoskrnl.c
* PURPOSE: NTOS glue routines for the MINIHAL library
* PROGRAMMERS: Hervé Poussineau <hpoussin@reactos.org>
* PROGRAMMERS: Hervé Poussineau <hpoussin@reactos.org>
*/
/* INCLUDES ******************************************************************/
@ -25,14 +25,7 @@ KeInitializeEvent(
VOID
FASTCALL
KiAcquireSpinLock(
IN PKSPIN_LOCK SpinLock)
{
}
VOID
FASTCALL
KiReleaseSpinLock(
KefAcquireSpinLockAtDpcLevel(
IN PKSPIN_LOCK SpinLock)
{
}

View file

@ -47,12 +47,12 @@
#include <drivers/acpi/acpi.h>
/* Internal kernel headers */
#define KeGetCurrentThread _KeGetCurrentThread
#ifdef _M_AMD64
#include <internal/amd64/ke.h>
#include <internal/amd64/mm.h>
#include "internal/amd64/intrin_i.h"
#else
#define KeGetCurrentThread _KeGetCurrentThread
#include <internal/i386/ke.h>
#include <internal/i386/mm.h>
#include "internal/i386/intrin_i.h"

View file

@ -566,13 +566,6 @@ HalInitializeBios(
#define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
#define KiEoiHelper(TrapFrame) return /* Just return to the caller */
#define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
#ifndef CONFIG_SMP
/* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
#define KiAcquireSpinLock(SpinLock)
#define KiReleaseSpinLock(SpinLock)
#define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
#define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
#endif // !CONFIG_SMP
#endif // _M_AMD64
extern BOOLEAN HalpNMIInProgress;

View file

@ -119,8 +119,8 @@ VOID
NTAPI
HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot,
IN PKIRQL Irql,
IN PPCI_TYPE1_CFG_BITS PciCfg1)
OUT PKIRQL OldIrql,
OUT PPCI_TYPE1_CFG_BITS PciCfg1)
{
/* Setup the PCI Configuration Register */
PciCfg1->u.AsULONG = 0;
@ -130,14 +130,14 @@ HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
PciCfg1->u.bits.Enable = TRUE;
/* Acquire the lock */
KeRaiseIrql(HIGH_LEVEL, Irql);
KiAcquireSpinLock(&HalpPCIConfigLock);
KeRaiseIrql(HIGH_LEVEL, OldIrql);
KeAcquireSpinLockAtDpcLevel(&HalpPCIConfigLock);
}
VOID
NTAPI
HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
IN KIRQL Irql)
IN KIRQL OldIrql)
{
PCI_TYPE1_CFG_BITS PciCfg1;
@ -147,8 +147,7 @@ HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
PciCfg1.u.AsULONG);
/* Release the lock */
KiReleaseSpinLock(&HalpPCIConfigLock);
KeLowerIrql(Irql);
KeReleaseSpinLock(&HalpPCIConfigLock, OldIrql);
}
TYPE1_READ(HalpPCIReadUcharType1, UCHAR)
@ -164,8 +163,8 @@ VOID
NTAPI
HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
IN PCI_SLOT_NUMBER Slot,
IN PKIRQL Irql,
IN PPCI_TYPE2_ADDRESS_BITS PciCfg)
OUT PKIRQL OldIrql,
OUT PPCI_TYPE2_ADDRESS_BITS PciCfg)
{
PCI_TYPE2_CSE_BITS PciCfg2Cse;
PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
@ -176,8 +175,8 @@ HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
/* Acquire the lock */
KeRaiseIrql(HIGH_LEVEL, Irql);
KiAcquireSpinLock(&HalpPCIConfigLock);
KeRaiseIrql(HIGH_LEVEL, OldIrql);
KeAcquireSpinLockAtDpcLevel(&HalpPCIConfigLock);
/* Setup the CSE Register */
PciCfg2Cse.u.AsUCHAR = 0;
@ -194,7 +193,7 @@ HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
VOID
NTAPI
HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler,
IN KIRQL Irql)
IN KIRQL OldIrql)
{
PCI_TYPE2_CSE_BITS PciCfg2Cse;
PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
@ -205,8 +204,7 @@ HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler,
WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
/* Release the lock */
KiReleaseSpinLock(&HalpPCIConfigLock);
KeLowerIrql(Irql);
KeReleaseSpinLock(&HalpPCIConfigLock, OldIrql);
}
TYPE2_READ(HalpPCIReadUcharType2, UCHAR)