mirror of
https://github.com/reactos/reactos.git
synced 2024-07-06 20:55:16 +00:00
[UNIATA]
* Sync to 0.44b4. CORE-6563 svn path=/trunk/; revision=57525
This commit is contained in:
parent
6dacc020db
commit
a0d3578e63
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@ -623,6 +623,9 @@ typedef struct _IDE_AHCI_PORT_REGISTERS {
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#define IDX_AHCI_P_TFD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
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#define IDX_AHCI_P_TFD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
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#define IDX_AHCI_P_SIG (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
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#define IDX_AHCI_P_SIG (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
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#define IDX_AHCI_P_CMD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
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#define IDX_AHCI_P_CMD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
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#define IDX_AHCI_P_SStatus (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))
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#define IDX_AHCI_P_SControl (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))
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#define IDX_AHCI_P_SError (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))
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#define IDX_AHCI_P_ACT (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
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#define IDX_AHCI_P_ACT (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
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#define IDX_AHCI_P_SNTF (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
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#define IDX_AHCI_P_SNTF (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))
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@ -6976,11 +6976,16 @@ GetLba2:
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}
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}
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// check if DMA read/write
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// check if DMA read/write
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if(deviceExtension->HwFlags & UNIATA_SATA) {
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if(deviceExtension->HwFlags & UNIATA_AHCI) {
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KdPrint2((PRINT_PREFIX "AtapiSendCommand: force use dma (ahci)\n"));
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KdPrint2((PRINT_PREFIX "AtapiSendCommand: force use dma (ahci)\n"));
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use_dma = TRUE;
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use_dma = TRUE;
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goto setup_dma;
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goto setup_dma;
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} else
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} else
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/* if((deviceExtension->HwFlags & UNIATA_SATA) && (LunExt->OrigTransferMode >= ATA_DMA)) {
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KdPrint2((PRINT_PREFIX "AtapiSendCommand: force use dma (sata)\n"));
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use_dma = TRUE;
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goto setup_dma;
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} else*/
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if(Srb->Cdb[0] == SCSIOP_REQUEST_SENSE) {
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if(Srb->Cdb[0] == SCSIOP_REQUEST_SENSE) {
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KdPrint2((PRINT_PREFIX "AtapiSendCommand: SCSIOP_REQUEST_SENSE, no DMA setup\n"));
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KdPrint2((PRINT_PREFIX "AtapiSendCommand: SCSIOP_REQUEST_SENSE, no DMA setup\n"));
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} else
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} else
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@ -7434,6 +7439,28 @@ make_reset:
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LunExt->IdentifyData.AtapiCmdSize ? 8 : 6,
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LunExt->IdentifyData.AtapiCmdSize ? 8 : 6,
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0);
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0);
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GetStatus(chan, statusByte);
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KdPrint3((PRINT_PREFIX "AtapiSendCommand: cmd status (%#x)\n", statusByte));
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if(statusByte & IDE_STATUS_ERROR) {
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GetBaseStatus(chan, statusByte);
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KdPrint3((PRINT_PREFIX "AtapiSendCommand: Error on cmd: (%#x)\n", statusByte));
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// Read the error reg. to clear it and fail this request.
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AtaReq->ReqState = REQ_STATE_TRANSFER_COMPLETE;
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return MapError(deviceExtension, Srb);
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}
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/* if(statusByte & IDE_STATUS_DSC) {
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KdPrint3((PRINT_PREFIX "AtapiSendCommand: DSC on cmd: (%#x)\n", statusByte));
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// Read the error reg. to clear it and fail this request.
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statusByte = AtapiReadPort1(chan, IDX_IO1_i_Error);
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KdPrint3((PRINT_PREFIX "AtapiSendCommand: Err on cmd: (%#x)\n", statusByte));
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if(statusByte >> 4) {
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GetBaseStatus(chan, statusByte);
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AtaReq->ReqState = REQ_STATE_TRANSFER_COMPLETE;
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return MapError(deviceExtension, Srb);
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}
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}
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*/
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if(chan->ChannelCtrlFlags & CTRFLAGS_DMA_OPERATION) {
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if(chan->ChannelCtrlFlags & CTRFLAGS_DMA_OPERATION) {
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AtapiDmaStart(HwDeviceExtension, DeviceNumber, lChannel, Srb);
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AtapiDmaStart(HwDeviceExtension, DeviceNumber, lChannel, Srb);
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}
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}
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@ -7642,7 +7669,7 @@ default_no_prep:
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// Fill in vendor identification fields.
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// Fill in vendor identification fields.
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for (i = 0; i < 24; i += 2) {
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for (i = 0; i < 24; i += 2) {
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MOV_DW_SWP(inquiryData->VendorId[i], ((PUCHAR)identifyData->ModelNumber)[i]);
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MOV_DW_SWP(inquiryData->DeviceIdentificationString[i], ((PUCHAR)identifyData->ModelNumber)[i]);
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}
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}
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/*
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/*
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// Initialize unused portion of product id.
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// Initialize unused portion of product id.
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@ -10732,6 +10759,8 @@ HalDisplayString (
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PUCHAR String
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PUCHAR String
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);
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);
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#define DEBUG_MSG_BUFFER_SIZE 512
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extern "C"
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extern "C"
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VOID
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VOID
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_cdecl
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_cdecl
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@ -10741,18 +10770,24 @@ _PrintNtConsole(
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)
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)
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{
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{
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int len;
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int len;
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UCHAR dbg_print_tmp_buff[512];
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UCHAR dbg_print_tmp_buff[DEBUG_MSG_BUFFER_SIZE];
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// UNICODE_STRING msgBuff;
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// UNICODE_STRING msgBuff;
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va_list ap;
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va_list ap;
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va_start(ap, DebugMessage);
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va_start(ap, DebugMessage);
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len = _vsnprintf((PCHAR)&dbg_print_tmp_buff[0], 511, DebugMessage, ap);
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len = _vsnprintf((PCHAR)&dbg_print_tmp_buff[0], DEBUG_MSG_BUFFER_SIZE-1, DebugMessage, ap);
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dbg_print_tmp_buff[511] = 0;
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dbg_print_tmp_buff[DEBUG_MSG_BUFFER_SIZE-1] = 0;
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KdPrint(((PCHAR)&(dbg_print_tmp_buff[0])));
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//DbgPrint(((PCHAR)&(dbg_print_tmp_buff[0]))); // already done in KdPrint macro
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HalDisplayString(dbg_print_tmp_buff);
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HalDisplayString(dbg_print_tmp_buff);
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#ifdef _DEBUG
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if(g_LogToDisplay > 1) {
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AtapiStallExecution(g_LogToDisplay*1000);
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}
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#endif // _DEBUG
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va_end(ap);
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va_end(ap);
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} // end PrintNtConsole()
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} // end PrintNtConsole()
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@ -1012,7 +1012,7 @@ AtapiDmaInit(
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/****************/
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/****************/
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KdPrint2((PRINT_PREFIX "SATA Generic\n"));
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KdPrint2((PRINT_PREFIX "SATA Generic\n"));
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if((udmamode >= 5) || (ChipFlags & UNIATA_AHCI) || (chan->MaxTransferMode >= ATA_SA150)) {
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if((udmamode >= 5) || (ChipFlags & UNIATA_AHCI) || ((udmamode >= 0) && (chan->MaxTransferMode >= ATA_SA150))) {
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/* some drives report UDMA6, some UDMA5 */
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/* some drives report UDMA6, some UDMA5 */
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/* ATAPI may not have SataCapabilities set in IDENTIFY DATA */
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/* ATAPI may not have SataCapabilities set in IDENTIFY DATA */
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if(ata_is_sata(&(LunExt->IdentifyData))) {
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if(ata_is_sata(&(LunExt->IdentifyData))) {
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@ -1085,7 +1085,7 @@ for_ugly_chips:
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KdPrint2((PRINT_PREFIX "PATA part\n"));
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KdPrint2((PRINT_PREFIX "PATA part\n"));
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} else {
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} else {
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if(/*(ChipFlags & ICH5) &&*/ BaseMemAddress) {
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if(!(ChipFlags & ICH7) && BaseMemAddress) {
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KdPrint2((PRINT_PREFIX "BaseMemAddress[5] -> indexed\n"));
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KdPrint2((PRINT_PREFIX "BaseMemAddress[5] -> indexed\n"));
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chan->RegTranslation[IDX_INDEXED_ADDR].Addr = BaseMemAddress + 0;
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chan->RegTranslation[IDX_INDEXED_ADDR].Addr = BaseMemAddress + 0;
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chan->RegTranslation[IDX_INDEXED_ADDR].MemIo = MemIo;
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chan->RegTranslation[IDX_INDEXED_ADDR].MemIo = MemIo;
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@ -1094,17 +1094,20 @@ for_ugly_chips:
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}
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}
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if((ChipFlags & ICH5) || BaseMemAddress) {
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if((ChipFlags & ICH5) || BaseMemAddress) {
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KdPrint2((PRINT_PREFIX "io indexed\n"));
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KdPrint2((PRINT_PREFIX "io proc()\n"));
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// Rather interesting way of register access...
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// Rather interesting way of register access...
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ChipType = INTEL_IDX;
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ChipType = INTEL_IDX;
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deviceExtension->HwFlags &= ~CHIPTYPE_MASK;
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deviceExtension->HwFlags &= ~CHIPTYPE_MASK;
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deviceExtension->HwFlags |= ChipType;
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deviceExtension->HwFlags |= ChipType;
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chan->RegTranslation[IDX_SATA_SStatus].Addr = 0x200*c + 0;
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if(ChipFlags & ICH7) {
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KdPrint2((PRINT_PREFIX "ICH7 way\n"));
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}
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chan->RegTranslation[IDX_SATA_SStatus].Addr = 0x200*c + 0; // this is fake non-zero value
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chan->RegTranslation[IDX_SATA_SStatus].Proc = 1;
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chan->RegTranslation[IDX_SATA_SStatus].Proc = 1;
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chan->RegTranslation[IDX_SATA_SError].Addr = 0x200*c + 2;
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chan->RegTranslation[IDX_SATA_SError].Addr = 0x200*c + 2; // this is fake non-zero value
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chan->RegTranslation[IDX_SATA_SError].Proc = 1;
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chan->RegTranslation[IDX_SATA_SError].Proc = 1;
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chan->RegTranslation[IDX_SATA_SControl].Addr = 0x200*c + 1;
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chan->RegTranslation[IDX_SATA_SControl].Addr = 0x200*c + 1; // this is fake non-zero value
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chan->RegTranslation[IDX_SATA_SControl].Proc = 1;
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chan->RegTranslation[IDX_SATA_SControl].Proc = 1;
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}
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}
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}
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}
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@ -1835,7 +1838,7 @@ AtapiChipInit(
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ChangePciConfig4(0x94, (a | (1 << 9)));
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ChangePciConfig4(0x94, (a | (1 << 9)));
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/* Set Ports Implemented register bits. */
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/* Set Ports Implemented register bits. */
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AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c,
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AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c,
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AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c) | 0xff);
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AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c) | 0x0f);
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}
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}
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/* enable PCI interrupt */
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/* enable PCI interrupt */
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ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
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ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
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@ -1883,24 +1886,29 @@ AtapiChipInit(
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KdPrint2((PRINT_PREFIX "other Intel\n"));
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KdPrint2((PRINT_PREFIX "other Intel\n"));
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switch(tmp8 & 0x03) {
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switch(tmp8 & 0x03) {
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case 0:
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case 0:
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KdPrint2((PRINT_PREFIX "0 -> %d/%d\n", 0+c, 2+c));
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chan->lun[0]->SATA_lun_map = 0+c;
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chan->lun[0]->SATA_lun_map = 0+c;
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chan->lun[1]->SATA_lun_map = 2+c;
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chan->lun[1]->SATA_lun_map = 2+c;
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break;
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break;
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case 2:
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case 2:
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if(c==0) {
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if(c==0) {
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KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 0, 2));
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chan->lun[0]->SATA_lun_map = 0;
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chan->lun[0]->SATA_lun_map = 0;
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chan->lun[1]->SATA_lun_map = 2;
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chan->lun[1]->SATA_lun_map = 2;
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} else {
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} else {
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// PATA
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// PATA
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KdPrint2((PRINT_PREFIX "PATA\n"));
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IsPata = TRUE;
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IsPata = TRUE;
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}
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}
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break;
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break;
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case 1:
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case 1:
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if(c==1) {
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if(c==1) {
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KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 1, 3));
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chan->lun[0]->SATA_lun_map = 1;
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chan->lun[0]->SATA_lun_map = 1;
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chan->lun[1]->SATA_lun_map = 3;
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chan->lun[1]->SATA_lun_map = 3;
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} else {
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} else {
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// PATA
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// PATA
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KdPrint2((PRINT_PREFIX "PATA\n"));
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IsPata = TRUE;
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IsPata = TRUE;
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}
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}
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break;
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break;
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@ -93,11 +93,15 @@ UniataEnableIoPCI(
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{
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{
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ULONG i;
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ULONG i;
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ULONG busDataRead;
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ULONG busDataRead;
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USHORT CmdOrig;
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// Enable Busmastering, IO-space and Mem-space
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// Enable Busmastering, IO-space and Mem-space
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// Note: write to CONFIG *may* cause controller to interrupt (not handled yet)
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// even if no bits are updated. Was observed on ICH7
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KdPrint2((PRINT_PREFIX "Enabling Mem/Io spaces and busmastering...\n"));
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KdPrint2((PRINT_PREFIX "Enabling Mem/Io spaces and busmastering...\n"));
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KdPrint2((PRINT_PREFIX "Initial pciData.Command = %#x\n", pciData->Command));
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KdPrint2((PRINT_PREFIX "Initial pciData.Command = %#x\n", pciData->Command));
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for(i=0; i<3; i++) {
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for(i=0; i<3; i++) {
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CmdOrig = pciData->Command;
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switch(i) {
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switch(i) {
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case 0:
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case 0:
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KdPrint2((PRINT_PREFIX "PCI_ENABLE_IO_SPACE\n"));
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KdPrint2((PRINT_PREFIX "PCI_ENABLE_IO_SPACE\n"));
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@ -112,17 +116,20 @@ UniataEnableIoPCI(
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pciData->Command |= PCI_ENABLE_BUS_MASTER;
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pciData->Command |= PCI_ENABLE_BUS_MASTER;
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break;
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break;
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}
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}
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if(CmdOrig == pciData->Command) {
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continue;
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}
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HalSetBusDataByOffset( PCIConfiguration, busNumber, slotNumber,
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HalSetBusDataByOffset( PCIConfiguration, busNumber, slotNumber,
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&(pciData->Command),
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&(pciData->Command),
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offsetof(PCI_COMMON_CONFIG, Command),
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offsetof(PCI_COMMON_CONFIG, Command),
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sizeof(pciData->Command));
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sizeof(pciData->Command));
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KdPrint2((PRINT_PREFIX "InterruptLine = %#x\n", pciData->u.type0.InterruptLine));
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// reread config space
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// reread config space
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busDataRead = HalGetBusData(PCIConfiguration, busNumber, slotNumber,
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busDataRead = HalGetBusData(PCIConfiguration, busNumber, slotNumber,
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pciData, PCI_COMMON_HDR_LENGTH);
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pciData, PCI_COMMON_HDR_LENGTH);
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KdPrint2((PRINT_PREFIX "New pciData.Command = %#x\n", pciData->Command));
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KdPrint2((PRINT_PREFIX "New pciData.Command = %#x\n", pciData->Command));
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}
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}
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KdPrint2((PRINT_PREFIX "InterruptLine = %#x\n", pciData->u.type0.InterruptLine));
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KdPrint2((PRINT_PREFIX "Final pciData.Command = %#x\n", pciData->Command));
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KdPrint2((PRINT_PREFIX "Final pciData.Command = %#x\n", pciData->Command));
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return pciData->Command;
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return pciData->Command;
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} // end UniataEnableIoPCI()
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} // end UniataEnableIoPCI()
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@ -1635,7 +1642,7 @@ UniataFindBusMasterController(
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AtapiStallExecution(10);
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AtapiStallExecution(10);
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GetBaseStatus(chan, statusByte);
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GetBaseStatus(chan, statusByte);
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skip_find_dev = FALSE;
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skip_find_dev = FALSE;
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if(!(deviceExtension->HwFlags & UNIATA_NO_SLAVE)) {
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if(!(deviceExtension->HwFlags & UNIATA_NO_SLAVE) && (deviceExtension->NumberLuns > 1)) {
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if ((statusByte & 0xf8) == 0xf8 ||
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if ((statusByte & 0xf8) == 0xf8 ||
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(statusByte == 0xa5)) {
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(statusByte == 0xa5)) {
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// Check slave.
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// Check slave.
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@ -1668,6 +1675,32 @@ UniataFindBusMasterController(
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}
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}
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//#ifdef UNIATA_INIT_ON_PROBE
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//#ifdef UNIATA_INIT_ON_PROBE
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// }
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// }
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#else //UNIATA_INIT_ON_PROBE
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KdPrint2((PRINT_PREFIX "clean IDE intr 0\n"));
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SelectDrive(chan, 0);
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AtapiStallExecution(10);
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GetBaseStatus(chan, statusByte);
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if(!(deviceExtension->HwFlags & UNIATA_NO_SLAVE) && (deviceExtension->NumberLuns > 1)) {
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KdPrint2((PRINT_PREFIX "clean IDE intr 1\n"));
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SelectDrive(chan, 1);
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AtapiStallExecution(1);
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GetBaseStatus(chan, statusByte);
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SelectDrive(chan, 0);
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}
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statusByte = GetDmaStatus(deviceExtension, c);
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KdPrint2((PRINT_PREFIX " DMA status %#x\n", statusByte));
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if(statusByte & BM_STATUS_INTR) {
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// bullshit, we have DMA interrupt, but had never initiate DMA operation
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KdPrint2((PRINT_PREFIX " clear unexpected DMA intr\n"));
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AtapiDmaDone(deviceExtension, 0, c, NULL);
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GetBaseStatus(chan, statusByte);
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}
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#endif //UNIATA_INIT_ON_PROBE
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#endif //UNIATA_INIT_ON_PROBE
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}
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}
|
||||||
found = TRUE;
|
found = TRUE;
|
||||||
|
|
|
@ -302,6 +302,24 @@ UniataSataReadPort4(
|
||||||
SetPciConfig4(0xa0, offs);
|
SetPciConfig4(0xa0, offs);
|
||||||
GetPciConfig4(0xa4, offs);
|
GetPciConfig4(0xa4, offs);
|
||||||
return offs;
|
return offs;
|
||||||
|
} else
|
||||||
|
if(deviceExtension->HwFlags & ICH7) {
|
||||||
|
offs = 0x100+chan->lun[p]->SATA_lun_map*0x80;
|
||||||
|
KdPrint3((PRINT_PREFIX " ICH7 way, offs %#x\n", offs));
|
||||||
|
switch(io_port_ndx) {
|
||||||
|
case IDX_SATA_SStatus:
|
||||||
|
offs += IDX_AHCI_P_SStatus;
|
||||||
|
break;
|
||||||
|
case IDX_SATA_SError:
|
||||||
|
offs += IDX_AHCI_P_SError;
|
||||||
|
break;
|
||||||
|
case IDX_SATA_SControl:
|
||||||
|
offs += IDX_AHCI_P_SControl;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), offs);
|
||||||
} else {
|
} else {
|
||||||
offs = ((deviceExtension->Channel+chan->lChannel)*2+p) * 0x100;
|
offs = ((deviceExtension->Channel+chan->lChannel)*2+p) * 0x100;
|
||||||
KdPrint3((PRINT_PREFIX " def way, offs %#x\n", offs));
|
KdPrint3((PRINT_PREFIX " def way, offs %#x\n", offs));
|
||||||
|
@ -372,6 +390,25 @@ UniataSataWritePort4(
|
||||||
SetPciConfig4(0xa0, offs);
|
SetPciConfig4(0xa0, offs);
|
||||||
SetPciConfig4(0xa4, data);
|
SetPciConfig4(0xa4, data);
|
||||||
return;
|
return;
|
||||||
|
} else
|
||||||
|
if(deviceExtension->HwFlags & ICH7) {
|
||||||
|
offs = 0x100+chan->lun[p]->SATA_lun_map*0x80;
|
||||||
|
KdPrint3((PRINT_PREFIX " ICH7 way, offs %#x\n", offs));
|
||||||
|
switch(io_port_ndx) {
|
||||||
|
case IDX_SATA_SStatus:
|
||||||
|
offs += IDX_AHCI_P_SStatus;
|
||||||
|
break;
|
||||||
|
case IDX_SATA_SError:
|
||||||
|
offs += IDX_AHCI_P_SError;
|
||||||
|
break;
|
||||||
|
case IDX_SATA_SControl:
|
||||||
|
offs += IDX_AHCI_P_SControl;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), offs, data);
|
||||||
|
return;
|
||||||
} else {
|
} else {
|
||||||
offs = ((deviceExtension->Channel+chan->lChannel)*2+p) * 0x100;
|
offs = ((deviceExtension->Channel+chan->lChannel)*2+p) * 0x100;
|
||||||
KdPrint3((PRINT_PREFIX " def way, offs %#x\n", offs));
|
KdPrint3((PRINT_PREFIX " def way, offs %#x\n", offs));
|
||||||
|
|
|
@ -1100,9 +1100,14 @@ typedef struct _INQUIRYDATA {
|
||||||
UCHAR Wide16Bit : 1;
|
UCHAR Wide16Bit : 1;
|
||||||
UCHAR Wide32Bit : 1;
|
UCHAR Wide32Bit : 1;
|
||||||
UCHAR RelativeAddressing : 1;
|
UCHAR RelativeAddressing : 1;
|
||||||
|
union {
|
||||||
|
UCHAR DeviceIdentificationString[28];
|
||||||
|
struct {
|
||||||
UCHAR VendorId[8];
|
UCHAR VendorId[8];
|
||||||
UCHAR ProductId[16];
|
UCHAR ProductId[16];
|
||||||
UCHAR ProductRevisionLevel[4];
|
UCHAR ProductRevisionLevel[4];
|
||||||
|
};
|
||||||
|
};
|
||||||
UCHAR VendorSpecific[20];
|
UCHAR VendorSpecific[20];
|
||||||
UCHAR Reserved3[40];
|
UCHAR Reserved3[40];
|
||||||
} INQUIRYDATA, *PINQUIRYDATA;
|
} INQUIRYDATA, *PINQUIRYDATA;
|
||||||
|
|
|
@ -1,10 +1,10 @@
|
||||||
#define UNIATA_VER_STR "43f5"
|
#define UNIATA_VER_STR "44b1"
|
||||||
#define UNIATA_VER_DOT 0.43.6.5
|
#define UNIATA_VER_DOT 0.44.2.1
|
||||||
#define UNIATA_VER_MJ 0
|
#define UNIATA_VER_MJ 0
|
||||||
#define UNIATA_VER_MN 43
|
#define UNIATA_VER_MN 44
|
||||||
#define UNIATA_VER_SUB_MJ 6
|
#define UNIATA_VER_SUB_MJ 2
|
||||||
#define UNIATA_VER_SUB_MN 5
|
#define UNIATA_VER_SUB_MN 1
|
||||||
#define UNIATA_VER_DOT_COMMA 0,43,6,5
|
#define UNIATA_VER_DOT_COMMA 0,44,2,1
|
||||||
#define UNIATA_VER_DOT_STR "0.43.6.5"
|
#define UNIATA_VER_DOT_STR "0.44.2.1"
|
||||||
#define UNIATA_VER_YEAR 2012
|
#define UNIATA_VER_YEAR 2012
|
||||||
#define UNIATA_VER_YEAR_STR "2012"
|
#define UNIATA_VER_YEAR_STR "2012"
|
||||||
|
|
Loading…
Reference in a new issue