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[UNIATA]

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* Sync to 0.44b4.
CORE-6563

svn path=/trunk/; revision=57525
This commit is contained in:
Amine Khaldi 2012-10-09 21:02:00 +00:00
parent 6dacc020db
commit a0d3578e63
8 changed files with 146 additions and 25 deletions
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3
reactos/drivers/storage/ide/uniata/bsmaster.h
View file

@ -623,6 +623,9 @@ typedef struct _IDE_AHCI_PORT_REGISTERS {
#define IDX_AHCI_P_TFD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, TFD))
#define IDX_AHCI_P_SIG (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SIG))
#define IDX_AHCI_P_CMD (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CMD))
#define IDX_AHCI_P_SStatus (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SStatus))
#define IDX_AHCI_P_SControl (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SControl))
#define IDX_AHCI_P_SError (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SError))
#define IDX_AHCI_P_ACT (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SACT))
#define IDX_AHCI_P_SNTF (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, SNTF))

47
reactos/drivers/storage/ide/uniata/id_ata.cpp
View file

@ -6976,11 +6976,16 @@ GetLba2:
}
// check if DMA read/write
if(deviceExtension->HwFlags & UNIATA_SATA) {
if(deviceExtension->HwFlags & UNIATA_AHCI) {
KdPrint2((PRINT_PREFIX "AtapiSendCommand: force use dma (ahci)\n"));
use_dma = TRUE;
goto setup_dma;
} else
/* if((deviceExtension->HwFlags & UNIATA_SATA) && (LunExt->OrigTransferMode >= ATA_DMA)) {
KdPrint2((PRINT_PREFIX "AtapiSendCommand: force use dma (sata)\n"));
use_dma = TRUE;
goto setup_dma;
} else*/
if(Srb->Cdb[0] == SCSIOP_REQUEST_SENSE) {
KdPrint2((PRINT_PREFIX "AtapiSendCommand: SCSIOP_REQUEST_SENSE, no DMA setup\n"));
} else
@ -7434,6 +7439,28 @@ make_reset:
LunExt->IdentifyData.AtapiCmdSize ? 8 : 6,
0);
GetStatus(chan, statusByte);
KdPrint3((PRINT_PREFIX "AtapiSendCommand: cmd status (%#x)\n", statusByte));
if(statusByte & IDE_STATUS_ERROR) {
GetBaseStatus(chan, statusByte);
KdPrint3((PRINT_PREFIX "AtapiSendCommand: Error on cmd: (%#x)\n", statusByte));
// Read the error reg. to clear it and fail this request.
AtaReq->ReqState = REQ_STATE_TRANSFER_COMPLETE;
return MapError(deviceExtension, Srb);
}
/* if(statusByte & IDE_STATUS_DSC) {
KdPrint3((PRINT_PREFIX "AtapiSendCommand: DSC on cmd: (%#x)\n", statusByte));
// Read the error reg. to clear it and fail this request.
statusByte = AtapiReadPort1(chan, IDX_IO1_i_Error);
KdPrint3((PRINT_PREFIX "AtapiSendCommand: Err on cmd: (%#x)\n", statusByte));
if(statusByte >> 4) {
GetBaseStatus(chan, statusByte);
AtaReq->ReqState = REQ_STATE_TRANSFER_COMPLETE;
return MapError(deviceExtension, Srb);
}
}
*/
if(chan->ChannelCtrlFlags & CTRFLAGS_DMA_OPERATION) {
AtapiDmaStart(HwDeviceExtension, DeviceNumber, lChannel, Srb);
}
@ -7642,7 +7669,7 @@ default_no_prep:
// Fill in vendor identification fields.
for (i = 0; i < 24; i += 2) {
MOV_DW_SWP(inquiryData->VendorId[i], ((PUCHAR)identifyData->ModelNumber)[i]);
MOV_DW_SWP(inquiryData->DeviceIdentificationString[i], ((PUCHAR)identifyData->ModelNumber)[i]);
}
/*
// Initialize unused portion of product id.
@ -10732,6 +10759,8 @@ HalDisplayString (
PUCHAR String
);
#define DEBUG_MSG_BUFFER_SIZE 512
extern "C"
VOID
_cdecl
@ -10741,18 +10770,24 @@ _PrintNtConsole(
)
{
int len;
UCHAR dbg_print_tmp_buff[512];
UCHAR dbg_print_tmp_buff[DEBUG_MSG_BUFFER_SIZE];
// UNICODE_STRING msgBuff;
va_list ap;
va_start(ap, DebugMessage);
len = _vsnprintf((PCHAR)&dbg_print_tmp_buff[0], 511, DebugMessage, ap);
len = _vsnprintf((PCHAR)&dbg_print_tmp_buff[0], DEBUG_MSG_BUFFER_SIZE-1, DebugMessage, ap);
dbg_print_tmp_buff[511] = 0;
dbg_print_tmp_buff[DEBUG_MSG_BUFFER_SIZE-1] = 0;
KdPrint(((PCHAR)&(dbg_print_tmp_buff[0])));
//DbgPrint(((PCHAR)&(dbg_print_tmp_buff[0]))); // already done in KdPrint macro
HalDisplayString(dbg_print_tmp_buff);
#ifdef _DEBUG
if(g_LogToDisplay > 1) {
AtapiStallExecution(g_LogToDisplay*1000);
}
#endif // _DEBUG
va_end(ap);
} // end PrintNtConsole()

2
reactos/drivers/storage/ide/uniata/id_dma.cpp
View file

@ -1012,7 +1012,7 @@ AtapiDmaInit(
/****************/
KdPrint2((PRINT_PREFIX "SATA Generic\n"));
if((udmamode >= 5) || (ChipFlags & UNIATA_AHCI) || (chan->MaxTransferMode >= ATA_SA150)) {
if((udmamode >= 5) || (ChipFlags & UNIATA_AHCI) || ((udmamode >= 0) && (chan->MaxTransferMode >= ATA_SA150))) {
/* some drives report UDMA6, some UDMA5 */
/* ATAPI may not have SataCapabilities set in IDENTIFY DATA */
if(ata_is_sata(&(LunExt->IdentifyData))) {

20
reactos/drivers/storage/ide/uniata/id_init.cpp
View file

@ -1085,7 +1085,7 @@ for_ugly_chips:
KdPrint2((PRINT_PREFIX "PATA part\n"));
} else {
if(/*(ChipFlags & ICH5) &&*/ BaseMemAddress) {
if(!(ChipFlags & ICH7) && BaseMemAddress) {
KdPrint2((PRINT_PREFIX "BaseMemAddress[5] -> indexed\n"));
chan->RegTranslation[IDX_INDEXED_ADDR].Addr = BaseMemAddress + 0;
chan->RegTranslation[IDX_INDEXED_ADDR].MemIo = MemIo;
@ -1094,17 +1094,20 @@ for_ugly_chips:
}
if((ChipFlags & ICH5) || BaseMemAddress) {
KdPrint2((PRINT_PREFIX "io indexed\n"));
KdPrint2((PRINT_PREFIX "io proc()\n"));
// Rather interesting way of register access...
ChipType = INTEL_IDX;
deviceExtension->HwFlags &= ~CHIPTYPE_MASK;
deviceExtension->HwFlags |= ChipType;
chan->RegTranslation[IDX_SATA_SStatus].Addr = 0x200*c + 0;
if(ChipFlags & ICH7) {
KdPrint2((PRINT_PREFIX "ICH7 way\n"));
}
chan->RegTranslation[IDX_SATA_SStatus].Addr = 0x200*c + 0; // this is fake non-zero value
chan->RegTranslation[IDX_SATA_SStatus].Proc = 1;
chan->RegTranslation[IDX_SATA_SError].Addr = 0x200*c + 2;
chan->RegTranslation[IDX_SATA_SError].Addr = 0x200*c + 2; // this is fake non-zero value
chan->RegTranslation[IDX_SATA_SError].Proc = 1;
chan->RegTranslation[IDX_SATA_SControl].Addr = 0x200*c + 1;
chan->RegTranslation[IDX_SATA_SControl].Addr = 0x200*c + 1; // this is fake non-zero value
chan->RegTranslation[IDX_SATA_SControl].Proc = 1;
}
}
@ -1835,7 +1838,7 @@ AtapiChipInit(
ChangePciConfig4(0x94, (a | (1 << 9)));
/* Set Ports Implemented register bits. */
AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c,
AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c) | 0xff);
AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), 0x0c) | 0x0f);
}
/* enable PCI interrupt */
ChangePciConfig2(offsetof(PCI_COMMON_CONFIG, Command), (a & ~0x0400));
@ -1883,24 +1886,29 @@ AtapiChipInit(
KdPrint2((PRINT_PREFIX "other Intel\n"));
switch(tmp8 & 0x03) {
case 0:
KdPrint2((PRINT_PREFIX "0 -> %d/%d\n", 0+c, 2+c));
chan->lun[0]->SATA_lun_map = 0+c;
chan->lun[1]->SATA_lun_map = 2+c;
break;
case 2:
if(c==0) {
KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 0, 2));
chan->lun[0]->SATA_lun_map = 0;
chan->lun[1]->SATA_lun_map = 2;
} else {
// PATA
KdPrint2((PRINT_PREFIX "PATA\n"));
IsPata = TRUE;
}
break;
case 1:
if(c==1) {
KdPrint2((PRINT_PREFIX "2 -> %d/%d\n", 1, 3));
chan->lun[0]->SATA_lun_map = 1;
chan->lun[1]->SATA_lun_map = 3;
} else {
// PATA
KdPrint2((PRINT_PREFIX "PATA\n"));
IsPata = TRUE;
}
break;

37
reactos/drivers/storage/ide/uniata/id_probe.cpp
View file

@ -93,11 +93,15 @@ UniataEnableIoPCI(
{
ULONG i;
ULONG busDataRead;
USHORT CmdOrig;
// Enable Busmastering, IO-space and Mem-space
// Note: write to CONFIG *may* cause controller to interrupt (not handled yet)
// even if no bits are updated. Was observed on ICH7
KdPrint2((PRINT_PREFIX "Enabling Mem/Io spaces and busmastering...\n"));
KdPrint2((PRINT_PREFIX "Initial pciData.Command = %#x\n", pciData->Command));
for(i=0; i<3; i++) {
CmdOrig = pciData->Command;
switch(i) {
case 0:
KdPrint2((PRINT_PREFIX "PCI_ENABLE_IO_SPACE\n"));
@ -112,17 +116,20 @@ UniataEnableIoPCI(
pciData->Command |= PCI_ENABLE_BUS_MASTER;
break;
}
if(CmdOrig == pciData->Command) {
continue;
}
HalSetBusDataByOffset( PCIConfiguration, busNumber, slotNumber,
&(pciData->Command),
offsetof(PCI_COMMON_CONFIG, Command),
sizeof(pciData->Command));
KdPrint2((PRINT_PREFIX "InterruptLine = %#x\n", pciData->u.type0.InterruptLine));
// reread config space
busDataRead = HalGetBusData(PCIConfiguration, busNumber, slotNumber,
pciData, PCI_COMMON_HDR_LENGTH);
KdPrint2((PRINT_PREFIX "New pciData.Command = %#x\n", pciData->Command));
}
KdPrint2((PRINT_PREFIX "InterruptLine = %#x\n", pciData->u.type0.InterruptLine));
KdPrint2((PRINT_PREFIX "Final pciData.Command = %#x\n", pciData->Command));
return pciData->Command;
} // end UniataEnableIoPCI()
@ -1635,7 +1642,7 @@ UniataFindBusMasterController(
AtapiStallExecution(10);
GetBaseStatus(chan, statusByte);
skip_find_dev = FALSE;
if(!(deviceExtension->HwFlags & UNIATA_NO_SLAVE)) {
if(!(deviceExtension->HwFlags & UNIATA_NO_SLAVE) && (deviceExtension->NumberLuns > 1)) {
if ((statusByte & 0xf8) == 0xf8 ||
(statusByte == 0xa5)) {
// Check slave.
@ -1668,6 +1675,32 @@ UniataFindBusMasterController(
}
//#ifdef UNIATA_INIT_ON_PROBE
// }
#else //UNIATA_INIT_ON_PROBE
KdPrint2((PRINT_PREFIX "clean IDE intr 0\n"));
SelectDrive(chan, 0);
AtapiStallExecution(10);
GetBaseStatus(chan, statusByte);
if(!(deviceExtension->HwFlags & UNIATA_NO_SLAVE) && (deviceExtension->NumberLuns > 1)) {
KdPrint2((PRINT_PREFIX "clean IDE intr 1\n"));
SelectDrive(chan, 1);
AtapiStallExecution(1);
GetBaseStatus(chan, statusByte);
SelectDrive(chan, 0);
}
statusByte = GetDmaStatus(deviceExtension, c);
KdPrint2((PRINT_PREFIX " DMA status %#x\n", statusByte));
if(statusByte & BM_STATUS_INTR) {
// bullshit, we have DMA interrupt, but had never initiate DMA operation
KdPrint2((PRINT_PREFIX " clear unexpected DMA intr\n"));
AtapiDmaDone(deviceExtension, 0, c, NULL);
GetBaseStatus(chan, statusByte);
}
#endif //UNIATA_INIT_ON_PROBE
}
found = TRUE;

37
reactos/drivers/storage/ide/uniata/id_sata.cpp
View file

@ -302,6 +302,24 @@ UniataSataReadPort4(
SetPciConfig4(0xa0, offs);
GetPciConfig4(0xa4, offs);
return offs;
} else
if(deviceExtension->HwFlags & ICH7) {
offs = 0x100+chan->lun[p]->SATA_lun_map*0x80;
KdPrint3((PRINT_PREFIX " ICH7 way, offs %#x\n", offs));
switch(io_port_ndx) {
case IDX_SATA_SStatus:
offs += IDX_AHCI_P_SStatus;
break;
case IDX_SATA_SError:
offs += IDX_AHCI_P_SError;
break;
case IDX_SATA_SControl:
offs += IDX_AHCI_P_SControl;
break;
default:
return -1;
}
return AtapiReadPortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), offs);
} else {
offs = ((deviceExtension->Channel+chan->lChannel)*2+p) * 0x100;
KdPrint3((PRINT_PREFIX " def way, offs %#x\n", offs));
@ -372,6 +390,25 @@ UniataSataWritePort4(
SetPciConfig4(0xa0, offs);
SetPciConfig4(0xa4, data);
return;
} else
if(deviceExtension->HwFlags & ICH7) {
offs = 0x100+chan->lun[p]->SATA_lun_map*0x80;
KdPrint3((PRINT_PREFIX " ICH7 way, offs %#x\n", offs));
switch(io_port_ndx) {
case IDX_SATA_SStatus:
offs += IDX_AHCI_P_SStatus;
break;
case IDX_SATA_SError:
offs += IDX_AHCI_P_SError;
break;
case IDX_SATA_SControl:
offs += IDX_AHCI_P_SControl;
break;
default:
return;
}
AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressSATA_0), offs, data);
return;
} else {
offs = ((deviceExtension->Channel+chan->lChannel)*2+p) * 0x100;
KdPrint3((PRINT_PREFIX " def way, offs %#x\n", offs));

11
reactos/drivers/storage/ide/uniata/scsi.h
View file

@ -1100,9 +1100,14 @@ typedef struct _INQUIRYDATA {
UCHAR Wide16Bit : 1;
UCHAR Wide32Bit : 1;
UCHAR RelativeAddressing : 1;
UCHAR VendorId[8];
UCHAR ProductId[16];
UCHAR ProductRevisionLevel[4];
union {
UCHAR DeviceIdentificationString[28];
struct {
UCHAR VendorId[8];
UCHAR ProductId[16];
UCHAR ProductRevisionLevel[4];
};
};
UCHAR VendorSpecific[20];
UCHAR Reserved3[40];
} INQUIRYDATA, *PINQUIRYDATA;

14
reactos/drivers/storage/ide/uniata/uniata_ver.h
View file

@ -1,10 +1,10 @@
#define UNIATA_VER_STR "43f5"
#define UNIATA_VER_DOT 0.43.6.5
#define UNIATA_VER_STR "44b1"
#define UNIATA_VER_DOT 0.44.2.1
#define UNIATA_VER_MJ 0
#define UNIATA_VER_MN 43
#define UNIATA_VER_SUB_MJ 6
#define UNIATA_VER_SUB_MN 5
#define UNIATA_VER_DOT_COMMA 0,43,6,5
#define UNIATA_VER_DOT_STR "0.43.6.5"
#define UNIATA_VER_MN 44
#define UNIATA_VER_SUB_MJ 2
#define UNIATA_VER_SUB_MN 1
#define UNIATA_VER_DOT_COMMA 0,44,2,1
#define UNIATA_VER_DOT_STR "0.44.2.1"
#define UNIATA_VER_YEAR 2012
#define UNIATA_VER_YEAR_STR "2012"