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[HAL]: Document and implement KiI8259MaskTable in C using actual bit positions. Each mapping is best to the best of my ability.
[HAL]: Implement KfRaiseIrql in C, remove ASM version. svn path=/trunk/; revision=45235
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Sir Richard
parent
575fd458f2
commit
9c976d58e7
3 changed files with 150 additions and 61 deletions
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@ -624,67 +624,6 @@ DoCall3:
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ret
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.endfunc
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.globl @KfRaiseIrql@4
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.func @KfRaiseIrql@4
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_@KfRaiseIrql@4:
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@KfRaiseIrql@4:
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/* Get the IRQL */
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movzx ecx, cl
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mov eax, PCR[KPCR_IRQL]
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#if DBG
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/* Validate it */
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cmp eax, ecx
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ja InvalidKfRaise
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#endif
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/* Check if it's in the software level */
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cmp cl, DISPATCH_LEVEL
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jbe SetIrql
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/* Save the current IRQL */
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mov edx, eax
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/* It's a hardware IRQL, so disable interrupts */
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pushf
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cli
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/* Set the new IRQL */
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mov PCR[KPCR_IRQL], ecx
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/* Mask the interrupts in the PIC */
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mov eax, KiI8259MaskTable[ecx*4]
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or eax, PCR[KPCR_IDR]
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out 0x21, al
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shr eax, 8
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out 0xA1, al
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/* Restore interrupts and return old IRQL */
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popf
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mov eax, edx
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ret
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SetIrql:
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/* Set the IRQL and return */
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mov PCR[KPCR_IRQL], ecx
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ret
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#if DBG
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InvalidKfRaise:
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/* Set to passive */
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mov dword ptr PCR[KPCR_IRQL], PASSIVE_LEVEL
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/* Bugcheck the system */
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push 9
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push 0
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push ecx
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push eax
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push IRQL_NOT_GREATER_OR_EQUAL
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call _KeBugCheckEx@20
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#endif
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.endfunc
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.globl _HalpApcInterrupt
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.func HalpApcInterrupt
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TRAP_FIXUPS hapc_a, hapc_t, DoFixupV86, DoFixupAbios
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@ -14,6 +14,87 @@
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/* GLOBALS ********************************************************************/
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/* This table contains the static x86 PIC mapping between IRQLs and IRQs */
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ULONG KiI8259MaskTable[32] =
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{
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/*
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* It Device IRQLs only start at 4 or higher, so these are just software
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* IRQLs that don't really change anything on the hardware
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*/
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0b00000000000000000000000000000000, /* IRQL 0 */
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0b00000000000000000000000000000000, /* IRQL 1 */
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0b00000000000000000000000000000000, /* IRQL 2 */
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0b00000000000000000000000000000000, /* IRQL 3 */
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/*
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* These next IRQLs are actually useless from the PIC perspective, because
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* with only 2 PICs, the mask you can send them is only 8 bits each, for 16
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* bits total, so these IRQLs are masking off a phantom PIC.
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*/
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0b11111111100000000000000000000000, /* IRQL 4 */
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0b11111111110000000000000000000000, /* IRQL 5 */
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0b11111111111000000000000000000000, /* IRQL 6 */
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0b11111111111100000000000000000000, /* IRQL 7 */
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0b11111111111110000000000000000000, /* IRQL 8 */
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0b11111111111111000000000000000000, /* IRQL 9 */
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0b11111111111111100000000000000000, /* IRQL 10 */
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0b11111111111111110000000000000000, /* IRQL 11 */
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/*
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* Okay, now we're finally starting to mask off IRQs on the slave PIC, from
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* IRQ15 to IRQ8. This means the higher-level IRQs get less priority in the
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* IRQL sense.
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*/
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0b11111111111111111000000000000000, /* IRQL 12 */
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0b11111111111111111100000000000000, /* IRQL 13 */
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0b11111111111111111110000000000000, /* IRQL 14 */
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0b11111111111111111111000000000000, /* IRQL 15 */
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0b11111111111111111111100000000000, /* IRQL 16 */
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0b11111111111111111111110000000000, /* IRQL 17 */
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0b11111111111111111111111000000000, /* IRQL 18 */
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0b11111111111111111111111000000000, /* IRQL 19 */
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/*
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* Now we mask off the IRQs on the master. Notice the 0 "droplet"? You might
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* have also seen that IRQL 18 and 19 are essentially equal as far as the
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* PIC is concerned. That bit is actually IRQ8, which happens to be the RTC.
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* The RTC will keep firing as long as we don't reach PROFILE_LEVEL which
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* actually kills it. The RTC clock (unlike the system clock) is used by the
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* profiling APIs in the HAL, so that explains the logic.
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*/
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0b11111111111111111111111010000000, /* IRQL 20 */
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0b11111111111111111111111011000000, /* IRQL 21 */
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0b11111111111111111111111011100000, /* IRQL 22 */
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0b11111111111111111111111011110000, /* IRQL 23 */
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0b11111111111111111111111011111000, /* IRQL 24 */
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0b11111111111111111111111011111000, /* IRQL 25 */
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0b11111111111111111111111011111010, /* IRQL 26 */
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0b11111111111111111111111111111010, /* IRQL 27 */
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/*
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* IRQL 24 and 25 are actually identical, so IRQL 28 is actually the last
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* IRQL to modify a bit on the master PIC. It happens to modify the very
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* last of the IRQs, IRQ0, which corresponds to the system clock interval
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* timer that keeps track of time (the Windows heartbeat). We only want to
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* turn this off at a high-enough IRQL, which is why IRQLs 24 and 25 are the
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* same to give this guy a chance to come up higher. Note that IRQL 28 is
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* called CLOCK2_LEVEL, which explains the usage we just explained.
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*/
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0b11111111111111111111111111111011, /* IRQL 28 */
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/*
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* We have finished off with the PIC so there's nothing left to mask at the
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* level of these IRQLs, making them only logical IRQLs on x86 machines.
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* Note that we have another 0 "droplet" you might've caught since IRQL 26.
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* In this case, it's the 2nd bit that never gets turned off, which is IRQ2,
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* the cascade IRQ that we use to bridge the slave PIC with the master PIC.
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* We never want to turn it off, so no matter the IRQL, it will be set to 0.
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*/
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0b11111111111111111111111111111011, /* IRQL 29 */
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0b11111111111111111111111111111011, /* IRQL 30 */
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0b11111111111111111111111111111011 /* IRQL 31 */
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};
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USHORT HalpEisaELCR;
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/* FUNCTIONS ******************************************************************/
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@ -191,6 +272,62 @@ KeRaiseIrqlToSynchLevel(VOID)
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return CurrentIrql;
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}
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/*
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* @implemented
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*/
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KIRQL
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FASTCALL
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KfRaiseIrql(IN KIRQL NewIrql)
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{
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PKPCR Pcr = KeGetPcr();
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ULONG EFlags;
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KIRQL CurrentIrql;
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PIC_MASK Mask;
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/* Read current IRQL */
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CurrentIrql = Pcr->Irql;
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#ifdef IRQL_DEBUG
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/* Validate correct raise */
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if (CurrentIrql > NewIrql)
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{
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/* Crash system */
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Pcr->Irql = PASSIVE_LEVEL;
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KeBugCheckEx(IRQL_NOT_GREATER_OR_EQUAL,
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CurrentIrql,
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NewIrql,
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0,
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9);
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}
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#endif
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/* Check if new IRQL affects hardware state */
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if (NewIrql > DISPATCH_LEVEL)
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{
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/* Save current interrupt state and disable interrupts */
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EFlags = __readeflags();
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_disable();
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/* Update the IRQL */
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Pcr->Irql = NewIrql;
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/* Set new PIC mask */
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Mask.Both = KiI8259MaskTable[NewIrql] | Pcr->IDR;
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__outbyte(PIC1_DATA_PORT, Mask.Master);
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__outbyte(PIC2_DATA_PORT, Mask.Slave);
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/* Restore interrupt state */
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__writeeflags(EFlags);
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}
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else
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{
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/* Set new IRQL */
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Pcr->Irql = NewIrql;
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}
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/* Return old IRQL */
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return CurrentIrql;
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}
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/* SOFTWARE INTERRUPTS ********************************************************/
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@ -282,6 +282,19 @@ typedef union _EISA_ELCR
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USHORT Bits;
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} EISA_ELCR, *PEISA_ELCR;
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typedef struct _PIC_MASK
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{
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union
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{
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struct
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{
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UCHAR Master;
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UCHAR Slave;
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};
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USHORT Both;
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};
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} PIC_MASK, *PPIC_MASK;
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//
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// Mm PTE/PDE to Hal PTE/PDE
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//
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