From 9bbc1250d2dd618878a8fc45651125cc036a246b Mon Sep 17 00:00:00 2001 From: Timo Kreuzer Date: Thu, 3 Jun 2010 23:08:40 +0000 Subject: [PATCH] [DDK] In an incredibly daring move, add even more types to ntddk.h svn path=/trunk/; revision=47556 --- reactos/include/ddk/ntddk.h | 261 ++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) diff --git a/reactos/include/ddk/ntddk.h b/reactos/include/ddk/ntddk.h index 7e3e9bab789..f8d1d3c1c29 100644 --- a/reactos/include/ddk/ntddk.h +++ b/reactos/include/ddk/ntddk.h @@ -703,6 +703,267 @@ typedef union _PCI_EXPRESS_SLOT_CONTROL_REGISTER { USHORT AsUSHORT; } PCI_EXPRESS_SLOT_CONTROL_REGISTER, *PPCI_EXPRESS_SLOT_CONTROL_REGISTER; +typedef union _PCI_EXPRESS_SLOT_STATUS_REGISTER { + struct { + USHORT AttentionButtonPressed:1; + USHORT PowerFaultDetected:1; + USHORT MRLSensorChanged:1; + USHORT PresenceDetectChanged:1; + USHORT CommandCompleted:1; + USHORT MRLSensorState:1; + USHORT PresenceDetectState:1; + USHORT ElectromechanicalLockEngaged:1; + USHORT DataLinkStateChanged:1; + USHORT Rsvd:7; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_SLOT_STATUS_REGISTER, *PPCI_EXPRESS_SLOT_STATUS_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_CONTROL_REGISTER { + struct { + USHORT CorrectableSerrEnable:1; + USHORT NonFatalSerrEnable:1; + USHORT FatalSerrEnable:1; + USHORT PMEInterruptEnable:1; + USHORT CRSSoftwareVisibilityEnable:1; + USHORT Rsvd:11; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_ROOT_CONTROL_REGISTER, *PPCI_EXPRESS_ROOT_CONTROL_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER { + struct { + USHORT CRSSoftwareVisibility:1; + USHORT Rsvd:15; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER, *PPCI_EXPRESS_ROOT_CAPABILITIES_REGISTER; + +typedef union _PCI_EXPRESS_ROOT_STATUS_REGISTER { + struct { + ULONG PMERequestorId:16; + ULONG PMEStatus:1; + ULONG PMEPending:1; + ULONG Rsvd:14; + } DUMMYSTRUCTNAME; + ULONG AsULONG; +} PCI_EXPRESS_ROOT_STATUS_REGISTER, *PPCI_EXPRESS_ROOT_STATUS_REGISTER; + +typedef struct _PCI_EXPRESS_CAPABILITY { + PCI_CAPABILITIES_HEADER Header; + PCI_EXPRESS_CAPABILITIES_REGISTER ExpressCapabilities; + PCI_EXPRESS_DEVICE_CAPABILITIES_REGISTER DeviceCapabilities; + PCI_EXPRESS_DEVICE_CONTROL_REGISTER DeviceControl; + PCI_EXPRESS_DEVICE_STATUS_REGISTER DeviceStatus; + PCI_EXPRESS_LINK_CAPABILITIES_REGISTER LinkCapabilities; + PCI_EXPRESS_LINK_CONTROL_REGISTER LinkControl; + PCI_EXPRESS_LINK_STATUS_REGISTER LinkStatus; + PCI_EXPRESS_SLOT_CAPABILITIES_REGISTER SlotCapabilities; + PCI_EXPRESS_SLOT_CONTROL_REGISTER SlotControl; + PCI_EXPRESS_SLOT_STATUS_REGISTER SlotStatus; + PCI_EXPRESS_ROOT_CONTROL_REGISTER RootControl; + PCI_EXPRESS_ROOT_CAPABILITIES_REGISTER RootCapabilities; + PCI_EXPRESS_ROOT_STATUS_REGISTER RootStatus; +} PCI_EXPRESS_CAPABILITY, *PPCI_EXPRESS_CAPABILITY; + +typedef enum { + MRLClosed = 0, + MRLOpen +} PCI_EXPRESS_MRL_STATE; + +typedef enum { + SlotEmpty = 0, + CardPresent +} PCI_EXPRESS_CARD_PRESENCE; + +typedef enum { + IndicatorOn = 1, + IndicatorBlink, + IndicatorOff +} PCI_EXPRESS_INDICATOR_STATE; + +typedef enum { + PowerOn = 0, + PowerOff +} PCI_EXPRESS_POWER_STATE; + +typedef enum { + L0sEntrySupport = 1, + L0sAndL1EntrySupport = 3 +} PCI_EXPRESS_ASPM_SUPPORT; + +typedef enum { + L0sAndL1EntryDisabled, + L0sEntryEnabled, + L1EntryEnabled, + L0sAndL1EntryEnabled +} PCI_EXPRESS_ASPM_CONTROL; + +typedef enum { + L0s_Below64ns = 0, + L0s_64ns_128ns, + L0s_128ns_256ns, + L0s_256ns_512ns, + L0s_512ns_1us, + L0s_1us_2us, + L0s_2us_4us, + L0s_Above4us +} PCI_EXPRESS_L0s_EXIT_LATENCY; + +typedef enum { + L1_Below1us = 0, + L1_1us_2us, + L1_2us_4us, + L1_4us_8us, + L1_8us_16us, + L1_16us_32us, + L1_32us_64us, + L1_Above64us +} PCI_EXPRESS_L1_EXIT_LATENCY; + +typedef enum { + PciExpressEndpoint = 0, + PciExpressLegacyEndpoint, + PciExpressRootPort = 4, + PciExpressUpstreamSwitchPort, + PciExpressDownstreamSwitchPort, + PciExpressToPciXBridge, + PciXToExpressBridge, + PciExpressRootComplexIntegratedEndpoint, + PciExpressRootComplexEventCollector +} PCI_EXPRESS_DEVICE_TYPE; + +typedef enum { + MaxPayload128Bytes = 0, + MaxPayload256Bytes, + MaxPayload512Bytes, + MaxPayload1024Bytes, + MaxPayload2048Bytes, + MaxPayload4096Bytes +} PCI_EXPRESS_MAX_PAYLOAD_SIZE; + +typedef union _PCI_EXPRESS_PME_REQUESTOR_ID { + struct { + USHORT FunctionNumber:3; + USHORT DeviceNumber:5; + USHORT BusNumber:8; + } DUMMYSTRUCTNAME; + USHORT AsUSHORT; +} PCI_EXPRESS_PME_REQUESTOR_ID, *PPCI_EXPRESS_PME_REQUESTOR_ID; + +#if defined(_WIN64) + +#ifndef USE_DMA_MACROS +#define USE_DMA_MACROS +#endif + +#ifndef NO_LEGACY_DRIVERS +#define NO_LEGACY_DRIVERS +#endif + +#endif /* defined(_WIN64) */ + +typedef enum _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE { + ResourceTypeSingle = 0, + ResourceTypeRange, + ResourceTypeExtendedCounterConfiguration, + ResourceTypeOverflow, + ResourceTypeMax +} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE; + +typedef struct _PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR { + PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR_TYPE Type; + ULONG Flags; + union { + ULONG CounterIndex; + ULONG ExtendedRegisterAddress; + struct { + ULONG Begin; + ULONG End; + } Range; + } u; +} PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR, *PPHYSICAL_COUNTER_RESOURCE_DESCRIPTOR; + +typedef struct _PHYSICAL_COUNTER_RESOURCE_LIST { + ULONG Count; + PHYSICAL_COUNTER_RESOURCE_DESCRIPTOR Descriptors[ANYSIZE_ARRAY]; +} PHYSICAL_COUNTER_RESOURCE_LIST, *PPHYSICAL_COUNTER_RESOURCE_LIST; + +#ifndef _PCIINTRF_X_ +#define _PCIINTRF_X_ + +typedef ULONG +(NTAPI *PCI_READ_WRITE_CONFIG)( + IN PVOID Context, + IN ULONG BusOffset, + IN ULONG Slot, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length); + +typedef VOID +(NTAPI *PCI_PIN_TO_LINE)( + IN PVOID Context, + IN PPCI_COMMON_CONFIG PciData); + +typedef VOID +(NTAPI *PCI_LINE_TO_PIN)( + IN PVOID Context, + IN PPCI_COMMON_CONFIG PciNewData, + IN PPCI_COMMON_CONFIG PciOldData); + +typedef VOID +(NTAPI *PCI_ROOT_BUS_CAPABILITY)( + IN PVOID Context, + OUT PPCI_ROOT_BUS_HARDWARE_CAPABILITY HardwareCapability); + +typedef VOID +(NTAPI *PCI_EXPRESS_WAKE_CONTROL)( + IN PVOID Context, + IN BOOLEAN EnableWake); + +typedef struct _PCI_BUS_INTERFACE_STANDARD { + USHORT Size; + USHORT Version; + PVOID Context; + PINTERFACE_REFERENCE InterfaceReference; + PINTERFACE_DEREFERENCE InterfaceDereference; + PCI_READ_WRITE_CONFIG ReadConfig; + PCI_READ_WRITE_CONFIG WriteConfig; + PCI_PIN_TO_LINE PinToLine; + PCI_LINE_TO_PIN LineToPin; + PCI_ROOT_BUS_CAPABILITY RootBusCapability; + PCI_EXPRESS_WAKE_CONTROL ExpressWakeControl; +} PCI_BUS_INTERFACE_STANDARD, *PPCI_BUS_INTERFACE_STANDARD; + +#define PCI_BUS_INTERFACE_STANDARD_VERSION 1 + +#endif /* _PCIINTRF_X_ */ + +#if (NTDDI_VERSION >= NTDDI_WIN7) + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX 0x00004000 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX 0x00008000 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX \ + (FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX | \ + FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX) + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_DEPRECATED 0x00000200 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_DEPRECATED 0x00000300 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_DEPRECATED 0x00000300 + +#else + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL 0x00000200 +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL 0x00000300 +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK 0x00000300 + +#define FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_ORDERLY_REMOVAL +#define FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL_EX FILE_CHARACTERISTICS_EXPECT_SURPRISE_REMOVAL +#define FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK_EX FILE_CHARACTERISTICS_REMOVAL_POLICY_MASK + +#endif /* (NTDDI_VERSION >= NTDDI_WIN7) */ + typedef enum _HAL_QUERY_INFORMATION_CLASS { HalInstalledBusInformation, HalProfileSourceInformation,