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https://github.com/reactos/reactos.git
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[USBEHCI_NEW]
- Add flags and structures needed for communicating with controller and handling schedules. - Add support routines for modifying operational registers on controller. - Implement getting the controller capabilties, starting and stopping the controller. svn path=/branches/usb-bringup/; revision=51365
This commit is contained in:
Michael Martin
parent
a61d852c84
commit
9b44c5121d
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@ -10,6 +10,13 @@
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#define INITGUID
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#include "usbehci.h"
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#include "hardware.h"
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BOOLEAN
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NTAPI
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InterruptServiceRoutine(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext);
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class CUSBHardwareDevice : public IUSBHardwareDevice
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{
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@ -40,6 +47,8 @@ public:
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NTSTATUS GetDeviceDetails(PULONG VendorId, PULONG DeviceId, PULONG NumberOfPorts, PULONG Speed);
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NTSTATUS GetDmaMemoryManager(OUT struct IDMAMemoryManager **OutMemoryManager);
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NTSTATUS GetUSBQueue(OUT struct IUSBQueue **OutUsbQueue);
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NTSTATUS StartController();
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NTSTATUS StopController();
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NTSTATUS ResetController();
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NTSTATUS ResetPort(ULONG PortIndex);
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KIRQL AcquireDeviceLock(void);
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@ -65,6 +74,21 @@ protected:
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PULONG m_Base;
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PDMA_ADAPTER m_Adapter;
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ULONG m_MapRegisters;
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PQUEUE_HEAD AsyncListQueueHead;
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EHCI_CAPS m_Capabilities;
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VOID SetCommandRegister(PEHCI_USBCMD_CONTENT UsbCmd);
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VOID GetCommandRegister(PEHCI_USBCMD_CONTENT UsbCmd);
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VOID SetStatusRegister(PEHCI_USBSTS_CONTENT UsbSts);
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VOID GetStatusRegister(PEHCI_USBSTS_CONTENT UsbSts);
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//VOID SetPortRegister(PEHCI_USBPORTSC_CONTENT UsbPort);
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//VOID GetPortRegister(PEHCI_USBPORTSC_CONTENT UsbPort);
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ULONG EHCI_READ_REGISTER_ULONG(ULONG Offset);
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ULONG EHCI_READ_REGISTER_USHORT(ULONG Offset);
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ULONG EHCI_READ_REGISTER_UCHAR(ULONG Offset);
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VOID EHCI_WRITE_REGISTER_ULONG(ULONG Offset, ULONG Value);
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VOID EHCI_WRITE_REGISTER_USHORT(ULONG Offset, ULONG Value);
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VOID EHCI_WRITE_REGISTER_UCHAR(ULONG Offset, ULONG Value);
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};
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//=================================================================================================
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@ -112,13 +136,81 @@ CUSBHardwareDevice::Initialize(
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return STATUS_SUCCESS;
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}
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VOID
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CUSBHardwareDevice::SetCommandRegister(PEHCI_USBCMD_CONTENT UsbCmd)
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{
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PULONG Register;
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Register = (PULONG)UsbCmd;
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WRITE_REGISTER_ULONG((PULONG)((ULONG)m_Base + EHCI_USBCMD), *Register);
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}
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VOID
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CUSBHardwareDevice::GetCommandRegister(PEHCI_USBCMD_CONTENT UsbCmd)
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{
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PULONG Register;
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Register = (PULONG)UsbCmd;
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*Register = READ_REGISTER_ULONG((PULONG)((ULONG)m_Base + EHCI_USBCMD));
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}
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VOID
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CUSBHardwareDevice::SetStatusRegister(PEHCI_USBSTS_CONTENT UsbSts)
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{
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PULONG Register;
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Register = (PULONG)UsbSts;
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WRITE_REGISTER_ULONG((PULONG)((ULONG)m_Base + EHCI_USBSTS), *Register);
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}
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VOID
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CUSBHardwareDevice::GetStatusRegister(PEHCI_USBSTS_CONTENT UsbSts)
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{
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PULONG CmdRegister;
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CmdRegister = (PULONG)UsbSts;
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*CmdRegister = READ_REGISTER_ULONG((PULONG)((ULONG)m_Base + EHCI_USBSTS));
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}
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ULONG
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CUSBHardwareDevice::EHCI_READ_REGISTER_ULONG(ULONG Offset)
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{
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return READ_REGISTER_ULONG((PULONG)((ULONG)m_Base + Offset));
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}
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ULONG
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CUSBHardwareDevice::EHCI_READ_REGISTER_USHORT(ULONG Offset)
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{
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return READ_REGISTER_USHORT((PUSHORT)((ULONG)m_Base + Offset));
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}
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ULONG
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CUSBHardwareDevice::EHCI_READ_REGISTER_UCHAR(ULONG Offset)
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{
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return READ_REGISTER_UCHAR((PUCHAR)((ULONG)m_Base + Offset));
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}
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VOID
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CUSBHardwareDevice::EHCI_WRITE_REGISTER_ULONG(ULONG Offset, ULONG Value)
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{
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WRITE_REGISTER_ULONG((PULONG)((ULONG)m_Base + Offset), Value);
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}
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VOID
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CUSBHardwareDevice::EHCI_WRITE_REGISTER_USHORT(ULONG Offset, ULONG Value)
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{
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WRITE_REGISTER_USHORT((PUSHORT)((ULONG)m_Base + Offset), Value);
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}
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VOID
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CUSBHardwareDevice::EHCI_WRITE_REGISTER_UCHAR(ULONG Offset, ULONG Value)
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{
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WRITE_REGISTER_UCHAR((PUCHAR)((ULONG)m_Base + Offset), Value);
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}
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NTSTATUS
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CUSBHardwareDevice::PnpStart(
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PCM_RESOURCE_LIST RawResources,
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PCM_RESOURCE_LIST TranslatedResources)
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{
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ULONG Index;
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ULONG Index, Count;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR ResourceDescriptor;
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DEVICE_DESCRIPTION DeviceDescription;
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PVOID ResourceBase;
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@ -174,8 +266,26 @@ CUSBHardwareDevice::PnpStart(
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}
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//
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//FIXME: query capabilities and update m_Base
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// Get controllers capabilities
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//
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m_Capabilities.Length = READ_REGISTER_UCHAR((PUCHAR)ResourceBase);
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m_Capabilities.HCIVersion = READ_REGISTER_USHORT((PUSHORT)((ULONG)ResourceBase + 2));
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m_Capabilities.HCSParamsLong = READ_REGISTER_ULONG((PULONG)((ULONG)ResourceBase + 4));
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m_Capabilities.HCCParamsLong = READ_REGISTER_ULONG((PULONG)((ULONG)ResourceBase + 8));
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DPRINT1("Controller has %d Ports\n", m_Capabilities.HCSParams.PortCount);
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if (m_Capabilities.HCSParams.PortRouteRules)
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{
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for (Count = 0; Count < m_Capabilities.HCSParams.PortCount; Count++)
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{
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m_Capabilities.PortRoute[Count] = READ_REGISTER_UCHAR((PUCHAR)(ULONG)ResourceBase + 12 + Count);
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}
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}
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//
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// Set m_Base to the address of Operational Register Space
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//
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m_Base = (PULONG)((ULONG)ResourceBase + m_Capabilities.Length);
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break;
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}
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}
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@ -211,7 +321,16 @@ CUSBHardwareDevice::PnpStart(
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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return STATUS_SUCCESS;
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//
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// FIXME: Create a QueueHead that will always be the address of the AsyncList
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//
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AsyncListQueueHead = NULL;
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//
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// Start the controller
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//
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DPRINT1("Starting Controller\n");
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return StartController();
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}
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NTSTATUS
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@ -258,6 +377,140 @@ CUSBHardwareDevice::GetUSBQueue(
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return STATUS_NOT_IMPLEMENTED;
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}
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NTSTATUS
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CUSBHardwareDevice::StartController(void)
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{
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EHCI_USBCMD_CONTENT UsbCmd;
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EHCI_USBSTS_CONTENT UsbSts;
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LONG FailSafe;
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//
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// Stop the controller if its running
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//
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GetStatusRegister(&UsbSts);
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if (UsbSts.HCHalted)
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StopController();
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//
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// Reset the device. Bit is set to 0 on completion.
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//
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SetCommandRegister(&UsbCmd);
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UsbCmd.HCReset = TRUE;
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SetCommandRegister(&UsbCmd);
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//
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// Check that the controller reset
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//
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for (FailSafe = 100; FailSafe > 1; FailSafe--)
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{
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KeStallExecutionProcessor(10);
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GetCommandRegister(&UsbCmd);
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if (!UsbCmd.HCReset)
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{
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break;
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}
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}
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//
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// If the controller did not reset then fail
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//
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if (UsbCmd.HCReset)
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{
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DPRINT1("EHCI ERROR: Controller failed to reset. Hardware problem!\n");
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return STATUS_UNSUCCESSFUL;
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}
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//
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// Disable Interrupts and clear status
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//
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EHCI_WRITE_REGISTER_ULONG(EHCI_USBINTR, 0);
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EHCI_WRITE_REGISTER_ULONG(EHCI_USBSTS, 0x0000001f);
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//
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// FIXME: Assign the AsyncList Register
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//
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//
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// Set Schedules to Enable and Interrupt Threshold to 1ms.
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//
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GetCommandRegister(&UsbCmd);
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UsbCmd.PeriodicEnable = FALSE;
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UsbCmd.AsyncEnable = FALSE; //FIXME: Need USB Memory Manager
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UsbCmd.IntThreshold = 1;
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// FIXME: Set framlistsize when periodic is implemented.
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SetCommandRegister(&UsbCmd);
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//
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// Enable Interrupts and start execution
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//
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EHCI_WRITE_REGISTER_ULONG(EHCI_USBINTR, EHCI_USBINTR_INTE | EHCI_USBINTR_ERR | EHCI_USBINTR_ASYNC | EHCI_USBINTR_HSERR
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/*| EHCI_USBINTR_FLROVR*/ | EHCI_USBINTR_PC);
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UsbCmd.Run = TRUE;
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SetCommandRegister(&UsbCmd);
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//
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// Wait for execution to start
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//
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for (FailSafe = 100; FailSafe > 1; FailSafe--)
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{
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KeStallExecutionProcessor(10);
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GetStatusRegister(&UsbSts);
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if (!UsbSts.HCHalted)
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{
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break;
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}
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}
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if (!UsbSts.HCHalted)
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{
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DPRINT1("Could not start execution on the controller\n");
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return STATUS_UNSUCCESSFUL;
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}
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//
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// Set port routing to EHCI controller
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//
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EHCI_WRITE_REGISTER_ULONG(EHCI_CONFIGFLAG, 1);
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DPRINT1("EHCI Started!\n");
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return STATUS_SUCCESS;
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}
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NTSTATUS
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CUSBHardwareDevice::StopController(void)
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{
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EHCI_USBCMD_CONTENT UsbCmd;
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EHCI_USBSTS_CONTENT UsbSts;
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LONG FailSafe;
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//
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// Disable Interrupts and stop execution
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EHCI_WRITE_REGISTER_ULONG (EHCI_USBINTR, 0);
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GetCommandRegister(&UsbCmd);
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UsbCmd.Run = FALSE;
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SetCommandRegister(&UsbCmd);
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for (FailSafe = 100; FailSafe > 1; FailSafe--)
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{
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KeStallExecutionProcessor(10);
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GetStatusRegister(&UsbSts);
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if (UsbSts.HCHalted)
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{
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break;
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}
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}
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if (!UsbSts.HCHalted)
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{
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DPRINT1("EHCI ERROR: Controller is not responding to Stop request!\n");
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return STATUS_UNSUCCESSFUL;
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}
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return STATUS_SUCCESS;
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}
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NTSTATUS
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CUSBHardwareDevice::ResetController(void)
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@ -314,7 +567,8 @@ CreateUSBHardware(
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{
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PUSBHARDWAREDEVICE This;
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This = new(NonPagedPool, 0) CUSBHardwareDevice(0);
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This = new(NonPagedPool, TAG_USBEHCI) CUSBHardwareDevice(0);
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if (!This)
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return STATUS_INSUFFICIENT_RESOURCES;
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306
drivers/usb/usbehci_new/hardware.h
Normal file
306
drivers/usb/usbehci_new/hardware.h
Normal file
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@ -0,0 +1,306 @@
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#pragma once
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#include <ntddk.h>
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//
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// EHCI Operational Registers
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//
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#define EHCI_USBCMD 0x00
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#define EHCI_USBSTS 0x04
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#define EHCI_USBINTR 0x08
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#define EHCI_FRINDEX 0x0C
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#define EHCI_CTRLDSSEGMENT 0x10
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#define EHCI_PERIODICLISTBASE 0x14
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#define EHCI_ASYNCLISTBASE 0x18
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#define EHCI_CONFIGFLAG 0x40
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#define EHCI_PORTSC 0x44
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//
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// Interrupt Register Flags
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//
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#define EHCI_USBINTR_INTE 0x01
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#define EHCI_USBINTR_ERR 0x02
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#define EHCI_USBINTR_PC 0x04
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#define EHCI_USBINTR_FLROVR 0x08
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#define EHCI_USBINTR_HSERR 0x10
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#define EHCI_USBINTR_ASYNC 0x20
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// Bits 6:31 Reserved
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//
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// Status Register Flags
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//
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#define EHCI_STS_INT 0x01
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#define EHCI_STS_ERR 0x02
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#define EHCI_STS_PCD 0x04
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#define EHCI_STS_FLR 0x08
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#define EHCI_STS_FATAL 0x10
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#define EHCI_STS_IAA 0x20
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// Bits 11:6 Reserved
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#define EHCI_STS_HALT 0x1000
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#define EHCI_STS_RECL 0x2000
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#define EHCI_STS_PSS 0x4000
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#define EHCI_STS_ASS 0x8000
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#define EHCI_ERROR_INT (EHCI_STS_FATAL | EHCI_STS_ERR)
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//
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// Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
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//
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#define TERMINATE_POINTER 0x01
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//
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// QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
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//
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//
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// Token Flags
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//
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#define PID_CODE_OUT_TOKEN 0x00
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#define PID_CODE_IN_TOKEN 0x01
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#define PID_CODE_SETUP_TOKEN 0x02
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#define DO_START_SPLIT 0x00
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#define DO_COMPLETE_SPLIT 0x01
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#define PING_STATE_DO_OUT 0x00
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#define PING_STATE_DO_PING 0x01
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typedef struct _PERIODICFRAMELIST
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{
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PULONG VirtualAddr;
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PHYSICAL_ADDRESS PhysicalAddr;
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ULONG Size;
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} PERIODICFRAMELIST, *PPERIODICFRAMELIST;
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//
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// QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
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//
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typedef struct _QETD_TOKEN_BITS
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{
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ULONG PingState:1;
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ULONG SplitTransactionState:1;
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ULONG MissedMicroFrame:1;
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ULONG TransactionError:1;
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ULONG BabbleDetected:1;
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ULONG DataBufferError:1;
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ULONG Halted:1;
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ULONG Active:1;
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ULONG PIDCode:2;
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ULONG ErrorCounter:2;
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ULONG CurrentPage:3;
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ULONG InterruptOnComplete:1;
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ULONG TotalBytesToTransfer:15;
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ULONG DataToggle:1;
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} QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
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//
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// QUEUE ELEMENT TRANSFER DESCRIPTOR
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//
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typedef struct _QUEUE_TRANSFER_DESCRIPTOR
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{
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//Hardware
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ULONG NextPointer;
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ULONG AlternateNextPointer;
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union
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{
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QETD_TOKEN_BITS Bits;
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ULONG DWord;
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} Token;
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ULONG BufferPointer[5];
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//Software
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ULONG PhysicalAddr;
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struct _QUEUE_TRANSFER_DESCRIPTOR *PreviousDescriptor;
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struct _QUEUE_TRANSFER_DESCRIPTOR *NextDescriptor;
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} QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
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//
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// EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
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//
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#define QH_ENDPOINT_FULLSPEED 0x00
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#define QH_ENDPOINT_LOWSPEED 0x01
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#define QH_ENDPOINT_HIGHSPEED 0x02
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typedef struct _END_POINT_CHARACTERISTICS
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{
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ULONG DeviceAddress:7;
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ULONG InactiveOnNextTransaction:1;
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ULONG EndPointNumber:4;
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ULONG EndPointSpeed:2;
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ULONG QEDTDataToggleControl:1;
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ULONG HeadOfReclamation:1;
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ULONG MaximumPacketLength:11;
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ULONG ControlEndPointFlag:1;
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ULONG NakCountReload:4;
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} END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
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//
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// Capabilities
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//
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typedef struct _END_POINT_CAPABILITIES
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{
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ULONG InterruptScheduleMask:8;
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ULONG SplitCompletionMask:8;
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ULONG HubAddr:6;
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ULONG PortNumber:6;
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ULONG NumberOfTransactionPerFrame:2;
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} END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
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//
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// QUEUE HEAD Flags and Struct
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//
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#define QH_TYPE_IDT 0x00
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#define QH_TYPE_QH 0x02
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#define QH_TYPE_SITD 0x04
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||||
#define QH_TYPE_FSTN 0x06
|
||||
|
||||
typedef struct _QUEUE_HEAD
|
||||
{
|
||||
//Hardware
|
||||
ULONG HorizontalLinkPointer;
|
||||
END_POINT_CHARACTERISTICS EndPointCharacteristics;
|
||||
END_POINT_CAPABILITIES EndPointCapabilities;
|
||||
// TERMINATE_POINTER not valid for this member
|
||||
ULONG CurrentLinkPointer;
|
||||
// TERMINATE_POINTER valid
|
||||
ULONG NextPointer;
|
||||
// TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
|
||||
ULONG AlternateNextPointer;
|
||||
// Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
|
||||
union
|
||||
{
|
||||
QETD_TOKEN_BITS Bits;
|
||||
ULONG DWord;
|
||||
} Token;
|
||||
ULONG BufferPointer[5];
|
||||
|
||||
//Software
|
||||
ULONG PhysicalAddr;
|
||||
struct _QUEUE_HEAD *PreviousQueueHead;
|
||||
struct _QUEUE_HEAD *NextQueueHead;
|
||||
PQUEUE_TRANSFER_DESCRIPTOR TransferDescriptor;
|
||||
PIRP IrpToComplete;
|
||||
PMDL MdlToFree;
|
||||
PKEVENT Event;
|
||||
} QUEUE_HEAD, *PQUEUE_HEAD;
|
||||
|
||||
//
|
||||
// Command register content
|
||||
//
|
||||
typedef struct _EHCI_USBCMD_CONTENT
|
||||
{
|
||||
ULONG Run : 1;
|
||||
ULONG HCReset : 1;
|
||||
ULONG FrameListSize : 2;
|
||||
ULONG PeriodicEnable : 1;
|
||||
ULONG AsyncEnable : 1;
|
||||
ULONG DoorBell : 1;
|
||||
ULONG LightReset : 1;
|
||||
ULONG AsyncParkCount : 2;
|
||||
ULONG Reserved : 1;
|
||||
ULONG AsyncParkEnable : 1;
|
||||
ULONG Reserved1 : 4;
|
||||
ULONG IntThreshold : 8;
|
||||
ULONG Reserved2 : 8;
|
||||
} EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
|
||||
|
||||
//
|
||||
// Status register content
|
||||
//
|
||||
typedef struct _EHCI_USBSTS_CONTENT
|
||||
{
|
||||
ULONG USBInterrupt:1;
|
||||
ULONG ErrorInterrupt:1;
|
||||
ULONG DetectChangeInterrupt:1;
|
||||
ULONG FrameListRolloverInterrupt:1;
|
||||
ULONG HostSystemErrorInterrupt:1;
|
||||
ULONG AsyncAdvanceInterrupt:1;
|
||||
ULONG Reserved:6;
|
||||
ULONG HCHalted:1;
|
||||
ULONG Reclamation:1;
|
||||
ULONG PeriodicScheduleStatus:1;
|
||||
ULONG AsynchronousScheduleStatus:1;
|
||||
} EHCI_USBSTS_CONTENT, *PEHCI_USBSTS_CONTENT;
|
||||
|
||||
typedef struct _EHCI_USBPORTSC_CONTENT
|
||||
{
|
||||
ULONG CurrentConnectStatus:1;
|
||||
ULONG ConnectStatusChange:1;
|
||||
ULONG PortEnabled:1;
|
||||
ULONG PortEnableChanged:1;
|
||||
ULONG OverCurrentActive:1;
|
||||
ULONG OverCurrentChange:1;
|
||||
ULONG ForcePortResume:1;
|
||||
ULONG Suspend:1;
|
||||
ULONG PortReset:1;
|
||||
ULONG Reserved:1;
|
||||
ULONG LineStatus:2;
|
||||
ULONG PortPower:1;
|
||||
ULONG PortOwner:1;
|
||||
} EHCI_USBPORTSC_CONTENT, *PEHCI_USBPORTSC_CONTENT;
|
||||
|
||||
typedef struct _EHCI_HCS_CONTENT
|
||||
{
|
||||
ULONG PortCount : 4;
|
||||
ULONG PortPowerControl: 1;
|
||||
ULONG Reserved : 2;
|
||||
ULONG PortRouteRules : 1;
|
||||
ULONG PortPerCHC : 4;
|
||||
ULONG CHCCount : 4;
|
||||
ULONG PortIndicator : 1;
|
||||
ULONG Reserved2 : 3;
|
||||
ULONG DbgPortNum : 4;
|
||||
ULONG Reserved3 : 8;
|
||||
|
||||
} EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
|
||||
|
||||
typedef struct _EHCI_HCC_CONTENT
|
||||
{
|
||||
ULONG CurAddrBits : 1;
|
||||
ULONG VarFrameList : 1;
|
||||
ULONG ParkMode : 1;
|
||||
ULONG Reserved : 1;
|
||||
ULONG IsoSchedThreshold : 4;
|
||||
ULONG EECPCapable : 8;
|
||||
ULONG Reserved2 : 16;
|
||||
|
||||
} EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
|
||||
|
||||
typedef struct _EHCI_CAPS {
|
||||
UCHAR Length;
|
||||
UCHAR Reserved;
|
||||
USHORT HCIVersion;
|
||||
union
|
||||
{
|
||||
EHCI_HCS_CONTENT HCSParams;
|
||||
ULONG HCSParamsLong;
|
||||
};
|
||||
union
|
||||
{
|
||||
EHCI_HCC_CONTENT HCCParams;
|
||||
ULONG HCCParamsLong;
|
||||
};
|
||||
UCHAR PortRoute [8];
|
||||
} EHCI_CAPS, *PEHCI_CAPS;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
PKSPIN_LOCK Lock;
|
||||
RTL_BITMAP Bitmap;
|
||||
PULONG BitmapBuffer;
|
||||
ULONG BlockSize;
|
||||
PVOID VirtualBase;
|
||||
PHYSICAL_ADDRESS PhysicalBase;
|
||||
ULONG Length;
|
||||
}DMA_MEMORY_ALLOCATOR, *LPDMA_MEMORY_ALLOCATOR;
|
||||
|
||||
typedef struct _EHCI_HOST_CONTROLLER
|
||||
{
|
||||
ULONG OpRegisters;
|
||||
EHCI_CAPS ECHICaps;
|
||||
PVOID CommonBufferVA;
|
||||
PHYSICAL_ADDRESS CommonBufferPA;
|
||||
ULONG CommonBufferSize;
|
||||
PQUEUE_HEAD AsyncListQueue;
|
||||
KSPIN_LOCK Lock;
|
||||
LPDMA_MEMORY_ALLOCATOR DmaMemAllocator;
|
||||
} EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;
|
||||
Loading…
Reference in a new issue