mirror of
https://github.com/reactos/reactos.git
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[NTOS]
Add internal amd64 headers. svn path=/trunk/; revision=46620
This commit is contained in:
Timo Kreuzer
parent
fbf4909187
commit
99e6ad789f
7 changed files with 672 additions and 0 deletions
81
reactos/ntoskrnl/include/internal/amd64/asmmacro.S
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81
reactos/ntoskrnl/include/internal/amd64/asmmacro.S
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@ -0,0 +1,81 @@
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/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS Kernel
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* FILE: ntoskrnl/include/amd64/asmmacro.S
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* PURPOSE: Macros for x64 assembly
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* PROGRAMMERS: Timo Kreuzer (timo.kreuzer@reactos.org)
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*/
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.intel_syntax noprefix
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.code64
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/* Macros for x64 stack unwind OPs */
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.macro .proc name
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.func name
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.global _\name
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_\name:
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.cfi_startproc
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.equ cfa_current_offset, -8
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.endm
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.macro .endproc
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.cfi_endproc
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.endfunc
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.endm
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.macro .allocstack size
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.cfi_adjust_cfa_offset \size
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.set cfa_current_offset, cfa_current_offset - \size
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.endm
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.macro .pushframe code
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.if (\code == 0)
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.cfi_adjust_cfa_offset 0x28
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.set cfa_current_offset, cfa_current_offset - 0x28
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.else
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.cfi_adjust_cfa_offset 0x30
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.set cfa_current_offset, cfa_current_offset - 0x30
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.endif
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.endm
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.macro .pushreg reg
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.cfi_adjust_cfa_offset 8
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.equ cfa_current_offset, cfa_current_offset - 8
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.cfi_offset \reg, cfa_current_offset
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.endm
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.macro .savereg reg, offset
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// checkme!!!
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.cfi_offset \reg, \offset
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.endm
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.macro .savexmm128 reg, offset
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// checkme!!!
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.cfi_offset \reg, \offset
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.endm
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.macro .setframe reg, offset
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.cfi_def_cfa reg, \offset
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.equ cfa_current_offset, \offset
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.endm
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.macro .endprolog
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.endm
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.macro UNIMPLEMENTED2 line, func
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jmp 3f
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.equ expr, 12
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1: .asciz "\func"
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2: .asciz __FILE__
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3:
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sub rsp, 0x20
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lea rcx, _MsgUnimplemented[rip]
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lea rdx, 1b[rip]
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lea r8, 2b[rip]
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mov r9, \line
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call _DbgPrint
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add rsp, 0x20
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.endm
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#define UNIMPLEMENTED UNIMPLEMENTED2 __LINE__,
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128
reactos/ntoskrnl/include/internal/amd64/intrin_i.h
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128
reactos/ntoskrnl/include/internal/amd64/intrin_i.h
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@ -0,0 +1,128 @@
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#ifndef _INTRIN_INTERNAL_
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#define _INTRIN_INTERNAL_
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VOID
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FORCEINLINE
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KeSetCurrentIrql(KIRQL Irql)
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{
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__writecr8(Irql);
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}
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PKGDTENTRY64
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FORCEINLINE
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KiGetGdtEntry(PVOID pGdt, USHORT Selector)
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{
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return (PKGDTENTRY64)((ULONG64)pGdt + (Selector & ~RPL_MASK));
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}
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PVOID
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FORCEINLINE
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KiGetGdtDescriptorBase(PKGDTENTRY Entry)
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{
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return (PVOID)((ULONG64)Entry->BaseLow |
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(ULONG64)Entry->Bytes.BaseMiddle << 16 |
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(ULONG64)Entry->Bytes.BaseHigh << 24 |
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(ULONG64)Entry->BaseUpper << 32);
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}
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VOID
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FORCEINLINE
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KiSetGdtDescriptorBase(PKGDTENTRY Entry, ULONG64 Base)
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{
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Entry->BaseLow = Base & 0xffff;
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Entry->Bits.BaseMiddle = (Base >> 16) & 0xff;
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Entry->Bits.BaseHigh = (Base >> 24) & 0xff;
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Entry->BaseUpper = Base >> 32;
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}
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VOID
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FORCEINLINE
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KiSetGdtDescriptorLimit(PKGDTENTRY Entry, ULONG Limit)
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{
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Entry->LimitLow = Limit & 0xffff;
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Entry->Bits.LimitHigh = Limit >> 16;
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}
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VOID
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FORCEINLINE
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KiInitGdtEntry(PKGDTENTRY64 Entry, ULONG64 Base, ULONG Size, UCHAR Type, UCHAR Dpl)
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{
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KiSetGdtDescriptorBase(Entry, Base);
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KiSetGdtDescriptorLimit(Entry, Size - 1);
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Entry->Bits.Type = Type;
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Entry->Bits.Dpl = Dpl;
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Entry->Bits.Present = 1;
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Entry->Bits.System = 0;
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Entry->Bits.LongMode = 0;
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Entry->Bits.DefaultBig = 0;
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Entry->Bits.Granularity = 0;
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Entry->MustBeZero = 0;
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}
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#if defined(__GNUC__)
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static __inline__ __attribute__((always_inline)) void __lgdt(void *Source)
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{
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__asm__ __volatile__("lgdt %0" : : "m"(*(short*)Source));
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}
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static __inline__ __attribute__((always_inline)) void __sgdt(void *Destination)
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{
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__asm__ __volatile__("sgdt %0" : : "m"(*(short*)Destination) : "memory");
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}
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static __inline__ __attribute__((always_inline)) void __lldt(unsigned short Value)
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{
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__asm__ __volatile__("lldt %0" : : "rm"(Value));
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}
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static __inline__ __attribute__((always_inline)) void __sldt(void *Destination)
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{
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__asm__ __volatile__("sldt %0" : : "m"(*(short*)Destination) : "memory");
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}
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static __inline__ __attribute__((always_inline)) void __ldmxcsr(unsigned long *Source)
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{
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__asm__ __volatile__("ldmxcsr %0" : : "m"(*Source));
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}
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static __inline__ __attribute__((always_inline)) void __stmxcsr(unsigned long *Destination)
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{
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__asm__ __volatile__("stmxcsr %0" : : "m"(*Destination) : "memory");
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}
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static __inline__ __attribute__((always_inline)) void __ltr(unsigned short Source)
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{
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__asm__ __volatile__("ltr %0" : : "rm"(Source));
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}
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static __inline__ __attribute__((always_inline)) void __str(unsigned short *Destination)
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{
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__asm__ __volatile__("str %0" : : "m"(*Destination) : "memory");
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}
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#elif defined(_MSC_VER)
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#define UNIMPLEMENTED DbgPrint("%s is unimplemented!!!\n", __FUNCTION__);
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void __lgdt(void *Source);
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void __sgdt(void *Destination);
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void __lldt(unsigned short Value);
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void __sldt(void *Destination);
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void __ltr(unsigned short Source);
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void __str(unsigned short *Destination);
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#else
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#error Unknown compiler for inline assembler
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#endif
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#endif
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/* EOF */
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268
reactos/ntoskrnl/include/internal/amd64/ke.h
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268
reactos/ntoskrnl/include/internal/amd64/ke.h
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@ -0,0 +1,268 @@
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#ifndef __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H
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#define __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H
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#define X86_EFLAGS_TF 0x00000100 /* Trap flag */
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#define X86_EFLAGS_IF 0x00000200 /* Interrupt Enable flag */
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#define X86_EFLAGS_IOPL 0x00003000 /* I/O Privilege Level bits */
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#define X86_EFLAGS_NT 0x00004000 /* Nested Task flag */
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#define X86_EFLAGS_RF 0x00010000 /* Resume flag */
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#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
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#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
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#define X86_CR0_PE 0x00000001 /* enable Protected Mode */
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#define X86_CR0_NE 0x00000020 /* enable native FPU error reporting */
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#define X86_CR0_TS 0x00000008 /* enable exception on FPU instruction for task switch */
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#define X86_CR0_EM 0x00000004 /* enable FPU emulation (disable FPU) */
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#define X86_CR0_MP 0x00000002 /* enable FPU monitoring */
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#define X86_CR0_WP 0x00010000 /* enable Write Protect (copy on write) */
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#define X86_CR0_PG 0x80000000 /* enable Paging */
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#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
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#define X86_CR4_PGE 0x00000080 /* enable global pages */
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#define X86_CR4_OSFXSR 0x00000200 /* enable FXSAVE/FXRSTOR instructions */
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#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable #XF exception */
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#define X86_FEATURE_VME 0x00000002 /* Virtual 8086 Extensions are present */
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#define X86_FEATURE_TSC 0x00000010 /* time stamp counters are present */
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#define X86_FEATURE_PAE 0x00000040 /* physical address extension is present */
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#define X86_FEATURE_CX8 0x00000100 /* CMPXCHG8B instruction present */
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#define X86_FEATURE_SYSCALL 0x00000800 /* SYSCALL/SYSRET support present */
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#define X86_FEATURE_PGE 0x00002000 /* Page Global Enable */
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#define X86_FEATURE_MMX 0x00800000 /* MMX extension present */
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#define X86_FEATURE_FXSR 0x01000000 /* FXSAVE/FXRSTOR instructions present */
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#define X86_FEATURE_SSE 0x02000000 /* SSE extension present */
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#define X86_FEATURE_SSE2 0x04000000 /* SSE2 extension present */
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#define X86_FEATURE_HT 0x10000000 /* Hyper-Threading present */
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#define X86_EXT_FEATURE_SSE3 0x00000001 /* SSE3 extension present */
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#define X86_EXT_FEATURE_3DNOW 0x40000000 /* 3DNOW! extension present */
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#define FRAME_EDITED 0xFFF8
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#define X86_MSR_GSBASE 0xC0000101
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#define X86_MSR_KERNEL_GSBASE 0xC0000102
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#define X86_MSR_EFER 0xC0000080
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#define X86_MSR_STAR 0xC0000081
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#define X86_MSR_LSTAR 0xC0000082
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#define X86_MSR_CSTAR 0xC0000083
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#define X86_MSR_SFMASK 0xC0000084
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#define EFER_SCE 0x01
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#define EFER_LME 0x10
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#define EFER_LMA 0x40
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#define EFER_NXE 0x80
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#define EFER_SVME 0x100
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#define EFER_FFXSR 0x400
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#define AMD64_TSS 9
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#ifndef __ASM__
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#include "intrin_i.h"
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typedef struct _KIDT_INIT
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{
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UCHAR InterruptId;
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UCHAR Dpl;
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UCHAR IstIndex;
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PVOID ServiceRoutine;
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} KIDT_INIT, *PKIDT_INIT;
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extern ULONG Ke386CacheAlignment;
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extern ULONG KeI386NpxPresent;
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extern ULONG KeI386XMMIPresent;
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extern ULONG KeI386FxsrPresent;
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extern ULONG KeI386CpuType;
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extern ULONG KeI386CpuStep;
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#define IMAGE_FILE_MACHINE_ARCHITECTURE IMAGE_FILE_MACHINE_AMD64
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//
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// INT3 is 1 byte long
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//
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#define KD_BREAKPOINT_TYPE UCHAR
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#define KD_BREAKPOINT_SIZE sizeof(UCHAR)
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#define KD_BREAKPOINT_VALUE 0xCC
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//
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// Macros for getting and setting special purpose registers in portable code
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//
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#define KeGetContextPc(Context) \
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((Context)->Rip)
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#define KeSetContextPc(Context, ProgramCounter) \
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((Context)->Rip = (ProgramCounter))
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#define KeGetTrapFramePc(TrapFrame) \
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((TrapFrame)->Rip)
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#define KeGetContextReturnRegister(Context) \
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((Context)->Rax)
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#define KeSetContextReturnRegister(Context, ReturnValue) \
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((Context)->Rax = (ReturnValue))
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//
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// Macro to get trap and exception frame from a thread stack
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//
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#define KeGetTrapFrame(Thread) \
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(PKTRAP_FRAME)((ULONG_PTR)((Thread)->InitialStack) - \
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sizeof(KTRAP_FRAME))
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//
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// Macro to get context switches from the PRCB
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// All architectures but x86 have it in the PRCB's KeContextSwitches
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//
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#define KeGetContextSwitches(Prcb) \
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(Prcb->KeContextSwitches)
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#define KeGetExceptionFrame(Thread) \
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(PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \
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sizeof(KEXCEPTION_FRAME))
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//
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// Returns the Interrupt State from a Trap Frame.
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// ON = TRUE, OFF = FALSE
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//
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#define KeGetTrapFrameInterruptState(TrapFrame) \
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BooleanFlagOn((TrapFrame)->EFlags, EFLAGS_INTERRUPT_MASK)
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//
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// Invalidates the TLB entry for a specified address
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//
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FORCEINLINE
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VOID
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KeInvalidateTlbEntry(IN PVOID Address)
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{
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/* Invalidate the TLB entry for this address */
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__invlpg(Address);
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}
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FORCEINLINE
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VOID
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KeFlushProcessTb(VOID)
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{
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/* Flush the TLB by resetting CR3 */
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__writecr3(__readcr3());
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}
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FORCEINLINE
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VOID
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KiRundownThread(IN PKTHREAD Thread)
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{
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#ifndef CONFIG_SMP
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DbgPrint("KiRundownThread is unimplemented\n");
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#else
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/* Nothing to do */
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#endif
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}
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|
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VOID
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FORCEINLINE
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KiEndInterrupt(IN KIRQL Irql,
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IN PKTRAP_FRAME TrapFrame)
|
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{
|
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DbgPrint("KiEndInterrupt is unimplemented\n");
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}
|
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|
||||
#define Ki386PerfEnd(x)
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|
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struct _KPCR;
|
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|
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VOID
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FASTCALL
|
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KiInitializeTss(IN PKTSS Tss, IN UINT64 Stack);
|
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|
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VOID KiDivideErrorFault();
|
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VOID KiDebugTrapOrFault();
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VOID KiNmiInterrupt();
|
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VOID KiBreakpointTrap();
|
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VOID KiOverflowTrap();
|
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VOID KiBoundFault();
|
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VOID KiInvalidOpcodeFault();
|
||||
VOID KiNpxNotAvailableFault();
|
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VOID KiDoubleFaultAbort();
|
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VOID KiNpxSegmentOverrunAbort();
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VOID KiInvalidTssFault();
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VOID KiSegmentNotPresentFault();
|
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VOID KiStackFault();
|
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VOID KiGeneralProtectionFault();
|
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VOID KiPageFault();
|
||||
VOID KiFloatingErrorFault();
|
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VOID KiAlignmentFault();
|
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VOID KiMcheckAbort();
|
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VOID KiXmmException();
|
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VOID KiApcInterrupt();
|
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VOID KiRaiseAssertion();
|
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VOID KiDebugServiceTrap();
|
||||
VOID KiDpcInterrupt();
|
||||
VOID KiIpiInterrupt();
|
||||
|
||||
VOID
|
||||
KiGdtPrepareForApplicationProcessorInit(ULONG Id);
|
||||
VOID
|
||||
Ki386InitializeLdt(VOID);
|
||||
VOID
|
||||
Ki386SetProcessorFeatures(VOID);
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
KiGetCacheInformation(VOID);
|
||||
|
||||
BOOLEAN
|
||||
NTAPI
|
||||
KiIsNpxPresent(
|
||||
VOID
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
NTAPI
|
||||
KiIsNpxErrataPresent(
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
KiSetProcessorType(VOID);
|
||||
|
||||
ULONG
|
||||
NTAPI
|
||||
KiGetFeatureBits(VOID);
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
KiInitializeCpuFeatures();
|
||||
|
||||
ULONG KeAllocateGdtSelector(ULONG Desc[2]);
|
||||
VOID KeFreeGdtSelector(ULONG Entry);
|
||||
VOID
|
||||
NtEarlyInitVdm(VOID);
|
||||
VOID
|
||||
KeApplicationProcessorInitDispatcher(VOID);
|
||||
VOID
|
||||
KeCreateApplicationProcessorIdleThread(ULONG Id);
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
Ke386InitThreadWithContext(PKTHREAD Thread,
|
||||
PKSYSTEM_ROUTINE SystemRoutine,
|
||||
PKSTART_ROUTINE StartRoutine,
|
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PVOID StartContext,
|
||||
PCONTEXT Context);
|
||||
#define KeArchInitThreadWithContext(Thread,SystemRoutine,StartRoutine,StartContext,Context) \
|
||||
Ke386InitThreadWithContext(Thread,SystemRoutine,StartRoutine,StartContext,Context)
|
||||
|
||||
#ifdef _NTOSKRNL_ /* FIXME: Move flags above to NDK instead of here */
|
||||
VOID
|
||||
NTAPI
|
||||
KiThreadStartup(PKSYSTEM_ROUTINE SystemRoutine,
|
||||
PKSTART_ROUTINE StartRoutine,
|
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PVOID StartContext,
|
||||
BOOLEAN UserThread,
|
||||
KTRAP_FRAME TrapFrame);
|
||||
#endif
|
||||
|
||||
#endif
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||||
#endif /* __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H */
|
||||
|
||||
/* EOF */
|
||||
189
reactos/ntoskrnl/include/internal/amd64/mm.h
Normal file
189
reactos/ntoskrnl/include/internal/amd64/mm.h
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* Lowlevel memory managment definitions
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/* Helper macros */
|
||||
#define PAGE_MASK(x) ((x)&(~0xfff))
|
||||
#define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
|
||||
|
||||
/* Memory layout base addresses */
|
||||
#define HYPER_SPACE 0xFFFFF70000000000ULL
|
||||
#define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
|
||||
#define MI_SESSION_SPACE_MINIMUM (PVOID)0xFFFFF90000000000ULL
|
||||
#define MI_SESSION_VIEW_END (PVOID)0xFFFFF97FFF000000ULL
|
||||
#define MI_SESSION_SPACE_END (PVOID)0xFFFFF98000000000ULL
|
||||
#define MI_SYSTEM_PTE_START (PVOID)0xFFFFFAA000000000ULL
|
||||
#define MI_PAGED_POOL_START (PVOID)0xFFFFFA8000000000ULL
|
||||
#define MI_NON_PAGED_SYSTEM_START_MIN 0xFFFFFAA000000000ULL
|
||||
#define MI_PFN_DATABASE (PVOID)0xFFFFFAC000000000ULL
|
||||
#define MI_NONPAGED_POOL_END (PVOID)0xFFFFFAE000000000ULL
|
||||
#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
|
||||
#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
|
||||
#define MI_SYSTEM_CACHE_WS_START (PVOID)0xFFFFF78000001000ULL // CHECKME
|
||||
|
||||
/* Memory sizes */
|
||||
#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
|
||||
#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
|
||||
#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
|
||||
#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
|
||||
#define MI_MAX_FREE_PAGE_LISTS 4
|
||||
#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
|
||||
#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024)
|
||||
#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024)
|
||||
#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024)
|
||||
#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024)
|
||||
#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
|
||||
MI_SESSION_POOL_SIZE + \
|
||||
MI_SESSION_IMAGE_SIZE + \
|
||||
MI_SESSION_WORKING_SET_SIZE)
|
||||
#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
|
||||
#define MI_NUMBER_SYSTEM_PTES 22000
|
||||
|
||||
PULONG64
|
||||
FORCEINLINE
|
||||
MmGetPageDirectory(VOID)
|
||||
{
|
||||
return (PULONG64)__readcr3();
|
||||
}
|
||||
|
||||
PMMPTE
|
||||
FORCEINLINE
|
||||
MiAddressToPxe(PVOID Address)
|
||||
{
|
||||
ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
|
||||
Offset &= PXI_MASK << 3;
|
||||
return (PMMPTE)(PXE_BASE + Offset);
|
||||
}
|
||||
|
||||
PMMPTE
|
||||
FORCEINLINE
|
||||
MiAddressToPpe(PVOID Address)
|
||||
{
|
||||
ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
|
||||
Offset &= 0x3FFFF << 3;
|
||||
return (PMMPTE)(PPE_BASE + Offset);
|
||||
}
|
||||
|
||||
PMMPTE
|
||||
FORCEINLINE
|
||||
_MiAddressToPde(PVOID Address)
|
||||
{
|
||||
ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
|
||||
Offset &= 0x7FFFFFF << 3;
|
||||
return (PMMPTE)(PDE_BASE + Offset);
|
||||
}
|
||||
#define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
|
||||
|
||||
PMMPTE
|
||||
FORCEINLINE
|
||||
_MiAddressToPte(PVOID Address)
|
||||
{
|
||||
ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
|
||||
Offset &= 0xFFFFFFFFFULL << 3;
|
||||
return (PMMPTE)(PTE_BASE + Offset);
|
||||
}
|
||||
#define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
|
||||
|
||||
/* Convert a PTE into a corresponding address */
|
||||
PVOID
|
||||
FORCEINLINE
|
||||
MiPteToAddress(PMMPTE Pte)
|
||||
{
|
||||
/* Use signed math */
|
||||
LONG64 Temp = (LONG64)Pte;
|
||||
Temp <<= 25;
|
||||
Temp >>= 16;
|
||||
return (PVOID)Temp;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
FORCEINLINE
|
||||
MiIsPdeForAddressValid(PVOID Address)
|
||||
{
|
||||
return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
|
||||
(MiAddressToPpe(Address)->u.Hard.Valid) &&
|
||||
(MiAddressToPde(Address)->u.Hard.Valid));
|
||||
}
|
||||
|
||||
#define ADDR_TO_PAGE_TABLE(v) (((ULONG_PTR)(v)) / (512 * PAGE_SIZE))
|
||||
#define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
|
||||
#define ADDR_TO_PTE_OFFSET(v) ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE)
|
||||
|
||||
#define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
|
||||
#define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
|
||||
#define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
|
||||
#define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
|
||||
|
||||
/* We don't use these hacks */
|
||||
VOID
|
||||
FORCEINLINE
|
||||
MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
VOID
|
||||
FORCEINLINE
|
||||
MmInitGlobalKernelPageDirectory(VOID)
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
#define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
|
||||
#define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
|
||||
|
||||
/* Easy accessing PFN in PTE */
|
||||
#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
|
||||
|
||||
// FIXME, only copied from x86
|
||||
#define MI_MAKE_LOCAL_PAGE(x) ((x)->u.Hard.Global = 0)
|
||||
#define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
|
||||
#define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
|
||||
#define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
|
||||
#define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
|
||||
#if !defined(CONFIG_SMP)
|
||||
#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
|
||||
#else
|
||||
#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
|
||||
#endif
|
||||
#define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
|
||||
#define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
|
||||
#define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
|
||||
#if !defined(CONFIG_SMP)
|
||||
#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
|
||||
#else
|
||||
#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
|
||||
#endif
|
||||
|
||||
// FIXME!!!
|
||||
#define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
|
||||
((x) / (4*1024*1024))
|
||||
|
||||
#define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
|
||||
((((x)) % (4*1024*1024)) / (4*1024))
|
||||
|
||||
#define NR_SECTION_PAGE_TABLES 1024
|
||||
#define NR_SECTION_PAGE_ENTRIES 1024
|
||||
|
||||
//#define TEB_BASE 0x7FFDE000
|
||||
|
||||
#define MI_HYPERSPACE_PTES (256 - 1)
|
||||
#define MI_ZERO_PTES (32)
|
||||
#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE
|
||||
#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \
|
||||
MI_HYPERSPACE_PTES * PAGE_SIZE)
|
||||
#define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \
|
||||
PAGE_SIZE)
|
||||
|
||||
/* On x86, these two are the same */
|
||||
#define MMPDE MMPTE
|
||||
#define PMMPDE PMMPTE
|
||||
|
||||
/*
|
||||
* FIXME - different architectures have different cache line sizes...
|
||||
*/
|
||||
#define MM_CACHE_LINE_SIZE 32
|
||||
|
||||
|
|
@ -27,6 +27,8 @@
|
|||
#include "../mips/intrin_i.h"
|
||||
#elif defined(_M_ARM)
|
||||
#include "../arm/intrin_i.h"
|
||||
#elif defined(_M_AMD64)
|
||||
#include "../amd64/intrin_i.h"
|
||||
#else
|
||||
#error "Unknown processor"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@
|
|||
#include "../mips/ke.h"
|
||||
#elif defined(_M_ARM)
|
||||
#include "../arm/ke.h"
|
||||
#elif defined(_M_AMD64)
|
||||
#include "../amd64/ke.h"
|
||||
#else
|
||||
#error "Unknown processor"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@
|
|||
#include <internal/mips/mm.h>
|
||||
#elif defined(_M_ARM)
|
||||
#include <internal/arm/mm.h>
|
||||
#elif defined(_M_AMD64)
|
||||
#include <internal/amd64/mm.h>
|
||||
#else
|
||||
#error "Unknown processor"
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue