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[ROSLOAD] Disable some arch-specific code for arm

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Mark Jansen 2019-08-18 19:02:46 +02:00
parent 28b866cc9c
commit 9592728f55
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GPG key ID: B39240EE84BEAE8B
1 changed files with 12 additions and 3 deletions
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15
boot/environ/app/rosload/rosload.c
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@ -882,7 +882,7 @@ ArchRestoreProcessorFeatures (
if (ArchXCr0BitsToClear) if (ArchXCr0BitsToClear)
{ {
/* Clear them */ /* Clear them */
#if defined(_MSC_VER) && !defined(__clang__) #if defined(_MSC_VER) && !defined(__clang__) && !defined(_M_ARM)
__xsetbv(0, __xgetbv(0) & ~ArchXCr0BitsToClear); __xsetbv(0, __xgetbv(0) & ~ArchXCr0BitsToClear);
#endif #endif
ArchXCr0BitsToClear = 0; ArchXCr0BitsToClear = 0;
@ -892,7 +892,9 @@ ArchRestoreProcessorFeatures (
if (ArchCr4BitsToClear) if (ArchCr4BitsToClear)
{ {
/* Clear them */ /* Clear them */
#if !defined(_M_ARM)
__writecr4(__readcr4() & ~ArchCr4BitsToClear); __writecr4(__readcr4() & ~ArchCr4BitsToClear);
#endif
ArchCr4BitsToClear = 0; ArchCr4BitsToClear = 0;
} }
} }
@ -979,10 +981,11 @@ OslpMain (
_Out_ PULONG ReturnFlags _Out_ PULONG ReturnFlags
) )
{ {
CPU_INFO CpuInfo;
BOOLEAN NxEnabled;
NTSTATUS Status; NTSTATUS Status;
BOOLEAN ExecuteJump; BOOLEAN ExecuteJump;
#if !defined(_M_ARM)
CPU_INFO CpuInfo;
BOOLEAN NxEnabled;
LARGE_INTEGER MiscMsr; LARGE_INTEGER MiscMsr;
/* Check if the CPU supports NX */ /* Check if the CPU supports NX */
@ -1006,6 +1009,8 @@ OslpMain (
/* Turn on NX support with the CPU-generic MSR */ /* Turn on NX support with the CPU-generic MSR */
__writemsr(MSR_EFER, __readmsr(MSR_EFER) | MSR_NXE); __writemsr(MSR_EFER, __readmsr(MSR_EFER) | MSR_NXE);
#endif
/* Load the kernel */ /* Load the kernel */
Status = OslPrepareTarget(ReturnFlags, &ExecuteJump); Status = OslPrepareTarget(ReturnFlags, &ExecuteJump);
if (NT_SUCCESS(Status) && (ExecuteJump)) if (NT_SUCCESS(Status) && (ExecuteJump))
@ -1014,6 +1019,7 @@ OslpMain (
Status = OslExecuteTransition(); Status = OslExecuteTransition();
} }
#if !defined(_M_ARM)
/* Retore NX support */ /* Retore NX support */
__writemsr(MSR_EFER, __readmsr(MSR_EFER) ^ MSR_NXE); __writemsr(MSR_EFER, __readmsr(MSR_EFER) ^ MSR_NXE);
@ -1026,6 +1032,7 @@ OslpMain (
__writemsr(MSR_IA32_MISC_ENABLE, MiscMsr.QuadPart); __writemsr(MSR_IA32_MISC_ENABLE, MiscMsr.QuadPart);
} }
#endif
/* Go back */ /* Go back */
return Status; return Status;
} }
@ -1073,6 +1080,7 @@ OslMain (
goto Quickie; goto Quickie;
} }
#if !defined(_M_ARM)
/* Check if CPUID 01h is supported */ /* Check if CPUID 01h is supported */
if (BlArchIsCpuIdFunctionSupported(1)) if (BlArchIsCpuIdFunctionSupported(1))
{ {
@ -1085,6 +1093,7 @@ OslMain (
EfiPrintf(L"PAE Supported, but won't be used\r\n"); EfiPrintf(L"PAE Supported, but won't be used\r\n");
} }
} }
#endif
/* Setup the boot library parameters for this application */ /* Setup the boot library parameters for this application */
BlSetupDefaultParameters(&LibraryParameters); BlSetupDefaultParameters(&LibraryParameters);