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[FAST486]
Fix Fast486FpuArithmeticOperation. It doesn't really matter for the operation itself which operand is the source/destination, because the FPU actually always performs the operation on ST0 and something else. So, FDIV/FDIVR were never really reversed here, it's just that FDIV always divides ST0 by something and FDIVR always divides something by ST0. svn path=/trunk/; revision=67828
This commit is contained in:
Aleksandar Andrejevic
parent
94d8c8c4b2
commit
904dcace9b
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@ -1273,9 +1273,11 @@ Fast486FpuCalculateCosine(PFAST486_STATE State,
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static inline VOID FASTCALL
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Fast486FpuArithmeticOperation(PFAST486_STATE State,
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INT Operation,
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PFAST486_FPU_DATA_REG SourceOperand,
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PFAST486_FPU_DATA_REG DestOperand)
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PFAST486_FPU_DATA_REG Operand,
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BOOLEAN TopDestination)
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{
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PFAST486_FPU_DATA_REG DestOperand = TopDestination ? &FPU_ST(0) : Operand;
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ASSERT(!(Operation & ~7));
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/* Check the operation */
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@ -1284,14 +1286,14 @@ Fast486FpuArithmeticOperation(PFAST486_STATE State,
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/* FADD */
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case 0:
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{
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Fast486FpuAdd(State, DestOperand, SourceOperand, DestOperand);
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Fast486FpuAdd(State, &FPU_ST(0), Operand, DestOperand);
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break;
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}
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/* FMUL */
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case 1:
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{
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Fast486FpuMultiply(State, DestOperand, SourceOperand, DestOperand);
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Fast486FpuMultiply(State, &FPU_ST(0), Operand, DestOperand);
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break;
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}
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@ -1300,7 +1302,7 @@ Fast486FpuArithmeticOperation(PFAST486_STATE State,
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/* FCOMP */
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case 3:
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{
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Fast486FpuCompare(State, DestOperand, SourceOperand);
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Fast486FpuCompare(State, &FPU_ST(0), Operand);
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if (Operation == 3) Fast486FpuPop(State);
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break;
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@ -1309,28 +1311,28 @@ Fast486FpuArithmeticOperation(PFAST486_STATE State,
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/* FSUB */
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case 4:
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{
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Fast486FpuSubtract(State, DestOperand, SourceOperand, DestOperand);
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Fast486FpuSubtract(State, &FPU_ST(0), Operand, DestOperand);
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break;
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}
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/* FSUBR */
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case 5:
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{
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Fast486FpuSubtract(State, SourceOperand, DestOperand, DestOperand);
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Fast486FpuSubtract(State, Operand, &FPU_ST(0), DestOperand);
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break;
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}
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/* FDIV */
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case 6:
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{
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Fast486FpuDivide(State, SourceOperand, DestOperand, DestOperand);
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Fast486FpuDivide(State, &FPU_ST(0), Operand, DestOperand);
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break;
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}
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/* FDIVR */
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case 7:
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{
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Fast486FpuDivide(State, DestOperand, SourceOperand, DestOperand);
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Fast486FpuDivide(State, Operand, &FPU_ST(0), DestOperand);
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break;
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}
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}
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@ -1425,7 +1427,7 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeD8)
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FAST486_MOD_REG_RM ModRegRm;
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BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
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#ifndef FAST486_NO_FPU
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PFAST486_FPU_DATA_REG SourceOperand, DestOperand;
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PFAST486_FPU_DATA_REG Operand;
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FAST486_FPU_DATA_REG MemoryData;
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#endif
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@ -1444,9 +1446,6 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeD8)
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FPU_SAVE_LAST_INST();
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/* The destination operand is ST0 */
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DestOperand = &FPU_ST(0);
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if (FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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{
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/* Raise the invalid operation exception */
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@ -1455,9 +1454,9 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeD8)
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if (State->FpuControl.Im)
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{
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/* Return the indefinite NaN */
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DestOperand->Sign = TRUE;
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DestOperand->Exponent = FPU_MAX_EXPONENT + 1;
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DestOperand->Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_ST(0).Sign = TRUE;
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FPU_ST(0).Exponent = FPU_MAX_EXPONENT + 1;
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FPU_ST(0).Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_SET_TAG(0, FPU_TAG_SPECIAL);
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}
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@ -1478,7 +1477,7 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeD8)
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}
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Fast486FpuFromSingleReal(State, Value, &MemoryData);
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SourceOperand = &MemoryData;
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Operand = &MemoryData;
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FPU_SAVE_LAST_OPERAND();
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}
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@ -1492,9 +1491,9 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeD8)
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if (State->FpuControl.Im)
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{
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/* Return the indefinite NaN */
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DestOperand->Sign = TRUE;
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DestOperand->Exponent = FPU_MAX_EXPONENT + 1;
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DestOperand->Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_ST(0).Sign = TRUE;
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FPU_ST(0).Exponent = FPU_MAX_EXPONENT + 1;
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FPU_ST(0).Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_SET_TAG(0, FPU_TAG_SPECIAL);
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}
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@ -1504,11 +1503,11 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeD8)
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}
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/* Load the source operand from an FPU register */
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SourceOperand = &FPU_ST(ModRegRm.SecondRegister);
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Operand = &FPU_ST(ModRegRm.SecondRegister);
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}
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/* Perform the requested operation */
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Fast486FpuArithmeticOperation(State, ModRegRm.Register, SourceOperand, DestOperand);
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Fast486FpuArithmeticOperation(State, ModRegRm.Register, Operand, TRUE);
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#endif
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}
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@ -2291,7 +2290,6 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDA)
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FAST486_MOD_REG_RM ModRegRm;
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BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
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#ifndef FAST486_NO_FPU
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PFAST486_FPU_DATA_REG SourceOperand, DestOperand;
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LONG Value;
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FAST486_FPU_DATA_REG MemoryData;
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#endif
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@ -2348,9 +2346,6 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDA)
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return;
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}
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/* The destination operand is always ST0 */
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DestOperand = &FPU_ST(0);
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if (FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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{
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/* Raise the invalid operation exception */
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@ -2359,9 +2354,9 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDA)
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if (State->FpuControl.Im)
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{
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/* Return the indefinite NaN */
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DestOperand->Sign = TRUE;
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DestOperand->Exponent = FPU_MAX_EXPONENT + 1;
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DestOperand->Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_ST(0).Sign = TRUE;
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FPU_ST(0).Exponent = FPU_MAX_EXPONENT + 1;
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FPU_ST(0).Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_SET_TAG(0, FPU_TAG_SPECIAL);
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}
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@ -2371,10 +2366,9 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDA)
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}
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Fast486FpuFromInteger(State, (LONGLONG)Value, &MemoryData);
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SourceOperand = &MemoryData;
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/* Perform the requested operation */
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Fast486FpuArithmeticOperation(State, ModRegRm.Register, SourceOperand, DestOperand);
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Fast486FpuArithmeticOperation(State, ModRegRm.Register, &MemoryData, TRUE);
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#endif
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}
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@ -2614,7 +2608,7 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDC)
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FAST486_MOD_REG_RM ModRegRm;
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BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
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#ifndef FAST486_NO_FPU
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PFAST486_FPU_DATA_REG SourceOperand, DestOperand;
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PFAST486_FPU_DATA_REG Operand;
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FAST486_FPU_DATA_REG MemoryData;
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#endif
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@ -2637,9 +2631,6 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDC)
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{
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ULONGLONG Value;
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/* The destination operand is ST0 */
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DestOperand = &FPU_ST(0);
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if (FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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{
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/* Raise the invalid operation exception */
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@ -2648,9 +2639,9 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDC)
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if (State->FpuControl.Im)
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{
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/* Return the indefinite NaN */
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DestOperand->Sign = TRUE;
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DestOperand->Exponent = FPU_MAX_EXPONENT + 1;
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DestOperand->Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_ST(0).Sign = TRUE;
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FPU_ST(0).Exponent = FPU_MAX_EXPONENT + 1;
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FPU_ST(0).Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_SET_TAG(0, FPU_TAG_SPECIAL);
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}
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@ -2673,17 +2664,14 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDC)
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}
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Fast486FpuFromDoubleReal(State, Value, &MemoryData);
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SourceOperand = &MemoryData;
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Operand = &MemoryData;
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FPU_SAVE_LAST_OPERAND();
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}
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else
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{
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/* The source operand is ST0 */
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SourceOperand = &FPU_ST(0);
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/* Load the destination operand from an FPU register */
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DestOperand = &FPU_ST(ModRegRm.SecondRegister);
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Operand = &FPU_ST(ModRegRm.SecondRegister);
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if ((FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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|| (FPU_GET_TAG(ModRegRm.SecondRegister) == FPU_TAG_EMPTY))
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@ -2694,9 +2682,9 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDC)
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if (State->FpuControl.Im)
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{
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/* Return the indefinite NaN */
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DestOperand->Sign = TRUE;
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DestOperand->Exponent = FPU_MAX_EXPONENT + 1;
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DestOperand->Mantissa = FPU_INDEFINITE_MANTISSA;
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Operand->Sign = TRUE;
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Operand->Exponent = FPU_MAX_EXPONENT + 1;
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Operand->Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_SET_TAG(ModRegRm.SecondRegister, FPU_TAG_SPECIAL);
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}
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@ -2707,7 +2695,7 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDC)
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}
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/* Perform the requested operation */
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Fast486FpuArithmeticOperation(State, ModRegRm.Register, SourceOperand, DestOperand);
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Fast486FpuArithmeticOperation(State, ModRegRm.Register, Operand, ModRegRm.Memory);
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#endif
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}
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@ -2992,7 +2980,7 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDE)
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FAST486_MOD_REG_RM ModRegRm;
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BOOLEAN AddressSize = State->SegmentRegs[FAST486_REG_CS].Size;
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#ifndef FAST486_NO_FPU
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PFAST486_FPU_DATA_REG SourceOperand, DestOperand;
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PFAST486_FPU_DATA_REG Operand;
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FAST486_FPU_DATA_REG MemoryData;
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#endif
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@ -3015,9 +3003,6 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDE)
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{
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SHORT Value;
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/* The destination operand is ST0 */
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DestOperand = &FPU_ST(0);
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if (FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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{
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/* Raise the invalid operation exception */
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@ -3026,9 +3011,9 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDE)
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if (State->FpuControl.Im)
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{
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/* Return the indefinite NaN */
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DestOperand->Sign = TRUE;
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DestOperand->Exponent = FPU_MAX_EXPONENT + 1;
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DestOperand->Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_ST(0).Sign = TRUE;
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FPU_ST(0).Exponent = FPU_MAX_EXPONENT + 1;
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FPU_ST(0).Mantissa = FPU_INDEFINITE_MANTISSA;
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FPU_SET_TAG(0, FPU_TAG_SPECIAL);
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}
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@ -3045,7 +3030,7 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDE)
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}
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Fast486FpuFromInteger(State, (LONGLONG)Value, &MemoryData);
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SourceOperand = &MemoryData;
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Operand = &MemoryData;
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FPU_SAVE_LAST_OPERAND();
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}
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@ -3059,11 +3044,8 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDE)
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return;
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}
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/* The source operand is ST0 */
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SourceOperand = &FPU_ST(0);
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/* Load the destination operand from a register */
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DestOperand = &FPU_ST(ModRegRm.SecondRegister);
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Operand = &FPU_ST(ModRegRm.SecondRegister);
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if ((FPU_GET_TAG(0) == FPU_TAG_EMPTY)
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|| (FPU_GET_TAG(ModRegRm.SecondRegister) == FPU_TAG_EMPTY))
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@ -3077,7 +3059,7 @@ FAST486_OPCODE_HANDLER(Fast486FpuOpcodeDE)
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}
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/* Perform the requested operation */
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Fast486FpuArithmeticOperation(State, ModRegRm.Register, SourceOperand, DestOperand);
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Fast486FpuArithmeticOperation(State, ModRegRm.Register, Operand, ModRegRm.Memory);
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if (!ModRegRm.Memory) Fast486FpuPop(State);
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#endif
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