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https://github.com/reactos/reactos.git
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[NTOS]
- Implement KiInitializeCpuFeatures amd call it early in the boot process - fix KeProcessorArchitecture - sumplify KiGetCpuVendor - fix and enable __lldt - remove some legacy code svn path=/branches/ros-amd64-bringup/; revision=45095
This commit is contained in:
parent
7185241ed4
commit
8a429f3d78
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@ -72,9 +72,9 @@ static __inline__ __attribute__((always_inline)) void __sgdt(void *Destination)
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__asm__ __volatile__("sgdt %0" : : "m"(*(short*)Destination) : "memory");
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}
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static __inline__ __attribute__((always_inline)) void __lldt(void *Source)
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static __inline__ __attribute__((always_inline)) void __lldt(unsigned short Value)
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{
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__asm__ __volatile__("lldt %0" : : "m"(*(short*)Source));
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__asm__ __volatile__("lldt %0" : : "rm"(Value));
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}
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static __inline__ __attribute__((always_inline)) void __sldt(void *Destination)
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@ -33,8 +33,6 @@ ULONG KeProcessorRevision;
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ULONG KeFeatureBits;
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ULONG KeI386MachineType;
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ULONG KeI386NpxPresent = 1;
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ULONG KeI386XMMIPresent = 0;
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ULONG KeI386FxsrPresent = 0;
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ULONG KeLargestCacheLine = 0x40;
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ULONG KiDmaIoCoherency = 0;
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CHAR KeNumberProcessors = 0;
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@ -127,26 +125,15 @@ KiGetCpuVendor(VOID)
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{
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PKPRCB Prcb = KeGetCurrentPrcb();
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INT Vendor[5];
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ULONG Temp;
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/* Assume no Vendor ID and fail if no CPUID Support. */
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Prcb->VendorString[0] = 0;
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if (!Prcb->CpuID) return 0;
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/* Get the Vendor ID and null-terminate it */
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__cpuid(Vendor, 0);
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Vendor[4] = 0;
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/* Re-arrange vendor string */
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Temp = Vendor[2];
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Vendor[2] = Vendor[3];
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Vendor[3] = Temp;
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/* Copy it to the PRCB and null-terminate it again */
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RtlCopyMemory(Prcb->VendorString,
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&Vendor[1],
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sizeof(Prcb->VendorString) - sizeof(CHAR));
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Prcb->VendorString[sizeof(Prcb->VendorString) - sizeof(CHAR)] = ANSI_NULL;
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/* Copy it to the PRCB and null-terminate it */
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*(ULONG*)&Prcb->VendorString[0] = Vendor[1]; // ebx
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*(ULONG*)&Prcb->VendorString[4] = Vendor[3]; // edx
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*(ULONG*)&Prcb->VendorString[8] = Vendor[2]; // ecx
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*(ULONG*)&Prcb->VendorString[12] = 0;
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/* Now check the CPU Type */
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if (!strcmp((PCHAR)Prcb->VendorString, CmpIntelID))
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@ -223,6 +210,15 @@ KiGetFeatureBits(VOID)
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if (CpuFeatures & 0x02000000) FeatureBits |= KF_XMMI;
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if (CpuFeatures & 0x04000000) FeatureBits |= KF_XMMI64;
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#if 0
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if (Reg[2] & 0x00000001) FeatureBits |= KF_SSE3NEW;
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if (Reg[2] & 0x00000008) FeatureBits |= KF_MONITOR;
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if (Reg[2] & 0x00000200) FeatureBits |= KF_SSE3SUP;
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if (Reg[2] & 0x00002000) FeatureBits |= KF_CMPXCHG16B;
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if (Reg[2] & 0x00080000) FeatureBits |= KF_SSE41;
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if (Reg[2] & 0x00800000) FeatureBits |= KF_POPCNT;
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#endif
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/* Check if the CPU has hyper-threading */
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if (CpuFeatures & 0x10000000)
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{
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@ -267,18 +263,6 @@ KiGetFeatureBits(VOID)
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return FeatureBits;
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}
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VOID
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NTAPI
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KiInitializeCpuFeatures()
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{
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/* Enable Write-Protection */
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__writecr0(__readcr0() | CR0_WP);
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/* Disable fpu monitoring */
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__writecr0(__readcr0() & ~CR0_MP);
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}
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VOID
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NTAPI
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KiGetCacheInformation(VOID)
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@ -36,19 +36,6 @@ VOID
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NTAPI
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KiInitMachineDependent(VOID)
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{
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#if 0
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ULONG Protect;
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ULONG CpuCount;
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BOOLEAN FbCaching = FALSE;
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NTSTATUS Status;
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ULONG ReturnLength;
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ULONG i, Affinity, Sample = 0;
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PFX_SAVE_AREA FxSaveArea;
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ULONG MXCsrMask = 0xFFBF;
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ULONG Dummy[4];
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KI_SAMPLE_MAP Samples[4];
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PKI_SAMPLE_MAP CurrentSample = Samples;
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/* Check for large page support */
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if (KeFeatureBits & KF_LARGE_PAGE)
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{
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@ -59,274 +46,25 @@ KiInitMachineDependent(VOID)
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/* Check for global page support */
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if (KeFeatureBits & KF_GLOBAL_PAGE)
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{
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/* Do an IPI to enable it on all CPUs */
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CpuCount = KeNumberProcessors;
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KeIpiGenericCall(Ki386EnableGlobalPage, (ULONG_PTR)&CpuCount);
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/* FIXME: Support this */
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DPRINT1("Global Page support detected but not yet taken advantage of!\n");
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}
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/* Check if we have MTRR */
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if (KeFeatureBits & KF_MTRR)
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{
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/* FIXME: Support this */
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DPRINT1("MTRR support detected but not yet taken advantage of!\n");
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}
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/* Check for PAT and/or MTRR support */
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if (KeFeatureBits & (KF_PAT | KF_MTRR))
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if (KeFeatureBits & KF_PAT)
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{
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/* Query the HAL to make sure we can use it */
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Status = HalQuerySystemInformation(HalFrameBufferCachingInformation,
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sizeof(BOOLEAN),
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&FbCaching,
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&ReturnLength);
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if ((NT_SUCCESS(Status)) && (FbCaching))
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{
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/* We can't, disable it */
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KeFeatureBits &= ~(KF_PAT | KF_MTRR);
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}
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/* FIXME: Support this */
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DPRINT1("PAT support detected but not yet taken advantage of!\n");
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}
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/* Check for PAT support and enable it */
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if (KeFeatureBits & KF_PAT) KiInitializePAT();
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/* Assume no errata for now */
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SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = 0;
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/* Check if we have an NPX */
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if (KeI386NpxPresent)
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{
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/* Loop every CPU */
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i = KeActiveProcessors;
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for (Affinity = 1; i; Affinity <<= 1)
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{
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/* Check if this is part of the set */
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if (i & Affinity)
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{
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/* Run on this CPU */
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i &= ~Affinity;
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KeSetSystemAffinityThread(Affinity);
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/* Detect FPU errata */
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if (KiIsNpxErrataPresent())
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{
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/* Disable NPX support */
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KeI386NpxPresent = FALSE;
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SharedUserData->
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ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] =
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TRUE;
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break;
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}
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}
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}
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}
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/* If there's no NPX, then we're emulating the FPU */
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SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] =
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!KeI386NpxPresent;
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/* Check if there's no NPX, so that we can disable associated features */
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if (!KeI386NpxPresent)
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{
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/* Remove NPX-related bits */
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KeFeatureBits &= ~(KF_XMMI64 | KF_XMMI | KF_FXSR | KF_MMX);
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/* Disable kernel flags */
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KeI386FxsrPresent = KeI386XMMIPresent = FALSE;
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/* Disable processor features that might've been set until now */
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SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] =
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SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] =
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SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] =
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SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] =
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SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = 0;
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}
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/* Check for CR4 support */
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if (KeFeatureBits & KF_CR4)
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{
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/* Do an IPI call to enable the Debug Exceptions */
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CpuCount = KeNumberProcessors;
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KeIpiGenericCall(Ki386EnableDE, (ULONG_PTR)&CpuCount);
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}
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/* Check if FXSR was found */
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if (KeFeatureBits & KF_FXSR)
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{
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/* Do an IPI call to enable the FXSR */
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CpuCount = KeNumberProcessors;
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KeIpiGenericCall(Ki386EnableFxsr, (ULONG_PTR)&CpuCount);
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/* Check if XMM was found too */
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if (KeFeatureBits & KF_XMMI)
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{
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/* Do an IPI call to enable XMMI exceptions */
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CpuCount = KeNumberProcessors;
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KeIpiGenericCall(Ki386EnableXMMIExceptions, (ULONG_PTR)&CpuCount);
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/* FIXME: Implement and enable XMM Page Zeroing for Mm */
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/* Patch the RtlPrefetchMemoryNonTemporal routine to enable it */
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Protect = MmGetPageProtect(NULL, RtlPrefetchMemoryNonTemporal);
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MmSetPageProtect(NULL,
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RtlPrefetchMemoryNonTemporal,
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Protect | PAGE_IS_WRITABLE);
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*(PCHAR)RtlPrefetchMemoryNonTemporal = 0x90;
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MmSetPageProtect(NULL, RtlPrefetchMemoryNonTemporal, Protect);
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}
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}
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/* Check for, and enable SYSENTER support */
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KiRestoreFastSyscallReturnState();
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/* Loop every CPU */
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i = KeActiveProcessors;
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for (Affinity = 1; i; Affinity <<= 1)
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{
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/* Check if this is part of the set */
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if (i & Affinity)
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{
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/* Run on this CPU */
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i &= ~Affinity;
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KeSetSystemAffinityThread(Affinity);
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/* Reset MHz to 0 for this CPU */
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KeGetCurrentPrcb()->MHz = 0;
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/* Check if we can use RDTSC */
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if (KeFeatureBits & KF_RDTSC)
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{
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/* Start sampling loop */
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for (;;)
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{
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/* Do a dummy CPUID to start the sample */
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CPUID(Dummy, 0);
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/* Fill out the starting data */
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CurrentSample->PerfStart = KeQueryPerformanceCounter(NULL);
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CurrentSample->TSCStart = __rdtsc();
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CurrentSample->PerfFreq.QuadPart = -50000;
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/* Sleep for this sample */
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KeDelayExecutionThread(KernelMode,
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FALSE,
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&CurrentSample->PerfFreq);
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/* Do another dummy CPUID */
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CPUID(Dummy, 0);
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/* Fill out the ending data */
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CurrentSample->PerfEnd =
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KeQueryPerformanceCounter(&CurrentSample->PerfFreq);
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CurrentSample->TSCEnd = __rdtsc();
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/* Calculate the differences */
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CurrentSample->PerfDelta = CurrentSample->PerfEnd.QuadPart -
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CurrentSample->PerfStart.QuadPart;
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CurrentSample->TSCDelta = CurrentSample->TSCEnd -
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CurrentSample->TSCStart;
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/* Compute CPU Speed */
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CurrentSample->MHz = (ULONG)((CurrentSample->TSCDelta *
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CurrentSample->
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PerfFreq.QuadPart + 500000) /
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(CurrentSample->PerfDelta *
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1000000));
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/* Check if this isn't the first sample */
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if (Sample)
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{
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/* Check if we got a good precision within 1MHz */
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if ((CurrentSample->MHz == CurrentSample[-1].MHz) ||
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(CurrentSample->MHz == CurrentSample[-1].MHz + 1) ||
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(CurrentSample->MHz == CurrentSample[-1].MHz - 1))
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{
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/* We did, stop sampling */
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break;
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}
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}
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/* Move on */
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CurrentSample++;
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Sample++;
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if (Sample == sizeof(Samples) / sizeof(Samples[0]))
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{
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/* Restart */
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CurrentSample = Samples;
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Sample = 0;
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}
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}
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/* Save the CPU Speed */
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KeGetCurrentPrcb()->MHz = CurrentSample[-1].MHz;
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}
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/* Check if we have MTRR */
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if (KeFeatureBits & KF_MTRR)
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{
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/* Then manually initialize MTRR for the CPU */
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KiInitializeMTRR(i ? FALSE : TRUE);
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}
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/* Check if we have AMD MTRR and initialize it for the CPU */
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if (KeFeatureBits & KF_AMDK6MTRR) KiAmdK6InitializeMTRR();
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/* Check if this is a buggy Pentium and apply the fixup if so */
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if (KiI386PentiumLockErrataPresent) KiI386PentiumLockErrataFixup();
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/* Check if the CPU supports FXSR */
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if (KeFeatureBits & KF_FXSR)
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{
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/* Get the current thread NPX state */
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FxSaveArea = (PVOID)
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((ULONG_PTR)KeGetCurrentThread()->InitialStack -
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NPX_FRAME_LENGTH);
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/* Clear initial MXCsr mask */
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FxSaveArea->U.FxArea.MXCsrMask = 0;
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/* Save the current NPX State */
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#ifdef __GNUC__
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asm volatile("fxsave %0\n\t" : "=m" (*FxSaveArea));
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#else
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__asm fxsave [FxSaveArea]
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#endif
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/* Check if the current mask doesn't match the reserved bits */
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if (FxSaveArea->U.FxArea.MXCsrMask != 0)
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{
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/* Then use whatever it's holding */
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MXCsrMask = FxSaveArea->U.FxArea.MXCsrMask;
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}
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/* Check if nobody set the kernel-wide mask */
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if (!KiMXCsrMask)
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{
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/* Then use the one we calculated above */
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KiMXCsrMask = MXCsrMask;
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}
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else
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{
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/* Was it set to the same value we found now? */
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if (KiMXCsrMask != MXCsrMask)
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{
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/* No, something is definitely wrong */
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KEBUGCHECKEX(MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED,
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KF_FXSR,
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KiMXCsrMask,
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MXCsrMask,
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0);
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}
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}
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/* Now set the kernel mask */
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KiMXCsrMask &= MXCsrMask;
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}
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}
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}
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/* Return affinity back to where it was */
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KeRevertToUserAffinityThread();
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/* NT allows limiting the duration of an ISR with a registry key */
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if (KiTimeLimitIsrMicroseconds)
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{
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/* FIXME: TODO */
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DPRINT1("ISR Time Limit not yet supported\n");
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}
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#endif
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}
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VOID
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@ -405,6 +143,44 @@ KiInitializePcr(IN PKIPCR Pcr,
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}
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VOID
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NTAPI
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KiInitializeCpuFeatures(ULONG Cpu)
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{
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ULONG FeatureBits;
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/* Get the processor features for this CPU */
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FeatureBits = KiGetFeatureBits();
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/* Check if we support all needed features */
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if ((FeatureBits & REQUIRED_FEATURE_BITS) != REQUIRED_FEATURE_BITS)
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{
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/* If not, bugcheck system */
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FrLdrDbgPrint("CPU doesn't have needed features! Has: 0x%x, required: 0x%x\n",
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FeatureBits, REQUIRED_FEATURE_BITS);
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KeBugCheck(0);
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}
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/* Set DEP to always on */
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SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_ALWAYSON;
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FeatureBits |= KF_NX_ENABLED;
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/* Save feature bits */
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KeGetCurrentPrcb()->FeatureBits = FeatureBits;
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/* Enable fx save restore support */
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__writecr4(__readcr4() | CR4_FXSR);
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/* Enable XMMI exceptions */
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__writecr4(__readcr4() | CR4_XMMEXCPT);
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/* Enable Write-Protection */
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__writecr0(__readcr0() | CR0_WP);
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/* Disable fpu monitoring */
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__writecr0(__readcr0() & ~CR0_MP);
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}
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VOID
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NTAPI
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KiInitializeKernel(IN PKPROCESS InitProcess,
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@ -414,7 +190,6 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
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IN CCHAR Number,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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{
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ULONG FeatureBits;
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ULONG PageDirectory[2];
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PVOID DpcStack;
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@ -424,54 +199,6 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
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/* Initialize the Power Management Support for this PRCB */
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// PoInitializePrcb(Prcb);
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/* Get the processor features for the CPU */
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FeatureBits = KiGetFeatureBits();
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/* Check if we support all needed features */
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if ((FeatureBits & REQUIRED_FEATURE_BITS) != REQUIRED_FEATURE_BITS)
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{
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/* If not, bugcheck system */
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DPRINT1("CPU doesn't have needed features! Has: 0x%x, required: 0x%x\n",
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FeatureBits, REQUIRED_FEATURE_BITS);
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KeBugCheck(0);
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}
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/* Set the default NX policy (opt-in) */
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SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN;
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/* Check if NPX is always on */
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if (strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE=ALWAYSON"))
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{
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/* Set it always on */
|
||||
SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_ALWAYSON;
|
||||
FeatureBits |= KF_NX_ENABLED;
|
||||
}
|
||||
else if (strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE=OPTOUT"))
|
||||
{
|
||||
/* Set it in opt-out mode */
|
||||
SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTOUT;
|
||||
FeatureBits |= KF_NX_ENABLED;
|
||||
}
|
||||
else if ((strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE=OPTIN")) ||
|
||||
(strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE")))
|
||||
{
|
||||
/* Set the feature bits */
|
||||
FeatureBits |= KF_NX_ENABLED;
|
||||
}
|
||||
else if ((strstr(KeLoaderBlock->LoadOptions, "NOEXECUTE=ALWAYSOFF")) ||
|
||||
(strstr(KeLoaderBlock->LoadOptions, "EXECUTE")))
|
||||
{
|
||||
/* Set disabled mode */
|
||||
SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_ALWAYSOFF;
|
||||
FeatureBits |= KF_NX_DISABLED;
|
||||
}
|
||||
|
||||
/* Save feature bits */
|
||||
Prcb->FeatureBits = FeatureBits;
|
||||
|
||||
/* Initialize the CPU features */
|
||||
KiInitializeCpuFeatures();
|
||||
|
||||
/* Save CPU state */
|
||||
KiSaveProcessorControlState(&Prcb->ProcessorState);
|
||||
|
||||
|
@ -490,15 +217,9 @@ KiInitializeKernel(IN PKPROCESS InitProcess,
|
|||
KeNodeBlock[0]->ProcessorMask = Prcb->SetMember;
|
||||
|
||||
/* Set boot-level flags */
|
||||
KeI386NpxPresent = TRUE;
|
||||
KeI386CpuType = Prcb->CpuType;
|
||||
KeI386CpuStep = Prcb->CpuStep;
|
||||
KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_INTEL;
|
||||
KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_AMD64;
|
||||
KeProcessorLevel = (USHORT)Prcb->CpuType;
|
||||
if (Prcb->CpuID) KeProcessorRevision = Prcb->CpuStep;
|
||||
KeFeatureBits = FeatureBits;
|
||||
KeI386FxsrPresent = (KeFeatureBits & KF_FXSR) ? TRUE : FALSE;
|
||||
KeI386XMMIPresent = (KeFeatureBits & KF_XMMI) ? TRUE : FALSE;
|
||||
|
||||
/* Set the current MP Master KPRCB to the Boot PRCB */
|
||||
Prcb->MultiThreadSetMaster = Prcb;
|
||||
|
@ -646,10 +367,7 @@ KiSystemStartupReal(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
|||
KeLoaderBlock = LoaderBlock;
|
||||
|
||||
/* Get the current CPU number */
|
||||
Cpu = KeNumberProcessors++;
|
||||
|
||||
/* Set active processors */
|
||||
KeActiveProcessors |= 1 << Cpu;
|
||||
Cpu = KeNumberProcessors++; // FIXME
|
||||
|
||||
/* LoaderBlock initialization for Cpu 0 */
|
||||
if (Cpu == 0)
|
||||
|
@ -677,10 +395,7 @@ KiSystemStartupReal(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
|||
Ke386SetFs(KGDT_32_R3_TEB | RPL_MASK);
|
||||
|
||||
/* LDT is unused */
|
||||
// __lldt(0);
|
||||
|
||||
/* Enable fx save restore support */
|
||||
__writecr4(__readcr4() | CR4_FXSR);
|
||||
__lldt(0);
|
||||
|
||||
/* Align stack to 16 bytes */
|
||||
LoaderBlock->KernelStack &= ~(16 - 1);
|
||||
|
@ -698,6 +413,9 @@ KiSystemStartupReal(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
|||
/* Initialize the PCR */
|
||||
KiInitializePcr(Pcr, Cpu, InitialThread, KiDoubleFaultStack);
|
||||
|
||||
/* Initialize the CPU features */
|
||||
KiInitializeCpuFeatures(Cpu);
|
||||
|
||||
/* Initial setup for the boot CPU */
|
||||
if (Cpu == 0)
|
||||
{
|
||||
|
@ -721,21 +439,26 @@ KiSystemStartupReal(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
|||
while (!KdPollBreakIn());
|
||||
DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
DPRINT("Pcr = %p, Gdt = %p, Idt = %p, Tss = %p\n",
|
||||
Pcr, Pcr->GdtBase, Pcr->IdtBase, Pcr->TssBase);
|
||||
|
||||
/* Acquire lock */
|
||||
while (InterlockedBitTestAndSet64((PLONG64)&KiFreezeExecutionLock, 0))
|
||||
{
|
||||
/* Loop until lock is free */
|
||||
while ((*(volatile KSPIN_LOCK*)&KiFreezeExecutionLock) & 1);
|
||||
}
|
||||
|
||||
/* Initialize the Processor with HAL */
|
||||
HalInitializeProcessor(Cpu, KeLoaderBlock);
|
||||
|
||||
/* Loop until we can release the freeze lock */
|
||||
do
|
||||
{
|
||||
/* Loop until execution can continue */
|
||||
while (*(volatile PKSPIN_LOCK*)&KiFreezeExecutionLock == (PVOID)1);
|
||||
} while(InterlockedBitTestAndSet64((PLONG64)&KiFreezeExecutionLock, 0));
|
||||
/* Set processor as active */
|
||||
KeActiveProcessors |= 1 << Cpu;
|
||||
|
||||
/* Release lock */
|
||||
InterlockedAnd64((PLONG64)&KiFreezeExecutionLock, 0);
|
||||
|
||||
/* Raise to HIGH_LEVEL */
|
||||
KfRaiseIrql(HIGH_LEVEL);
|
||||
|
|
|
@ -81,9 +81,6 @@ KiInitializeContextThread(IN PKTHREAD Thread,
|
|||
/* Setup the Fx Area */
|
||||
//FxSaveArea = &InitFrame->FxSaveArea;
|
||||
|
||||
/* Check if we support FXsr */
|
||||
// if (KeI386FxsrPresent)
|
||||
// {
|
||||
// /* Get the FX Save Format Area */
|
||||
// FxSaveFormat = (PFXSAVE_FORMAT)Context->ExtendedRegisters;
|
||||
//
|
||||
|
@ -96,41 +93,19 @@ KiInitializeContextThread(IN PKTHREAD Thread,
|
|||
// FxSaveFormat->DataOffset = 0;
|
||||
// FxSaveFormat->DataSelector = 0;
|
||||
// FxSaveFormat->MXCsr = 0x1F80;
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// /* Setup the regular save area */
|
||||
// Context->FloatSave.ControlWord = 0x27F;
|
||||
// Context->FloatSave.StatusWord = 0;
|
||||
// Context->FloatSave.TagWord = -1;
|
||||
// Context->FloatSave.ErrorOffset = 0;
|
||||
// Context->FloatSave.ErrorSelector = 0;
|
||||
// Context->FloatSave.DataOffset =0;
|
||||
// Context->FloatSave.DataSelector = 0;
|
||||
// }
|
||||
|
||||
/* Check if the CPU has NPX */
|
||||
if (KeI386NpxPresent)
|
||||
{
|
||||
/* Set an intial NPX State */
|
||||
//Context->FloatSave.Cr0NpxState = 0;
|
||||
//FxSaveArea->Cr0NpxState = 0;
|
||||
//FxSaveArea->NpxSavedCpu = 0;
|
||||
/* Set an intial NPX State */
|
||||
//Context->FloatSave.Cr0NpxState = 0;
|
||||
//FxSaveArea->Cr0NpxState = 0;
|
||||
//FxSaveArea->NpxSavedCpu = 0;
|
||||
|
||||
/* Now set the context flags depending on XMM support */
|
||||
//ContextFlags |= (KeI386FxsrPresent) ? CONTEXT_EXTENDED_REGISTERS :
|
||||
// CONTEXT_FLOATING_POINT;
|
||||
/* Now set the context flags depending on XMM support */
|
||||
//ContextFlags |= (KeI386FxsrPresent) ? CONTEXT_EXTENDED_REGISTERS :
|
||||
// CONTEXT_FLOATING_POINT;
|
||||
|
||||
/* Set the Thread's NPX State */
|
||||
Thread->NpxState = 0xA;
|
||||
Thread->DispatcherHeader.NpxIrql = PASSIVE_LEVEL;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We'll use emulation */
|
||||
//FxSaveArea->Cr0NpxState = CR0_EM;
|
||||
Thread->NpxState = 0xA &~ CR0_MP;
|
||||
}
|
||||
/* Set the Thread's NPX State */
|
||||
Thread->NpxState = 0xA;
|
||||
Thread->DispatcherHeader.NpxIrql = PASSIVE_LEVEL;
|
||||
|
||||
/* Disable any debug regiseters */
|
||||
Context->ContextFlags &= ~CONTEXT_DEBUG_REGISTERS;
|
||||
|
@ -179,19 +154,10 @@ KiInitializeContextThread(IN PKTHREAD Thread,
|
|||
//RtlZeroMemory(FxSaveArea, sizeof(FX_SAVE_AREA));
|
||||
|
||||
/* Check if we have Fxsr support */
|
||||
if (KeI386FxsrPresent)
|
||||
{
|
||||
DPRINT1("FxsrPresent but did nothing\n");
|
||||
// /* Set the stub FX area */
|
||||
// FxSaveArea->U.FxArea.ControlWord = 0x27F;
|
||||
// FxSaveArea->U.FxArea.MXCsr = 0x1F80;
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// /* Set the stub FN area */
|
||||
// FxSaveArea->U.FnArea.ControlWord = 0x27F;
|
||||
// FxSaveArea->U.FnArea.TagWord = -1;
|
||||
}
|
||||
DPRINT1("FxsrPresent but did nothing\n");
|
||||
// /* Set the stub FX area */
|
||||
// FxSaveArea->U.FxArea.ControlWord = 0x27F;
|
||||
// FxSaveArea->U.FxArea.MXCsr = 0x1F80;
|
||||
|
||||
/* No NPX State */
|
||||
Thread->NpxState = 0xA;
|
||||
|
|
Loading…
Reference in a new issue