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compatability fixes, so some hal code can be shared
svn path=/branches/ros-amd64-bringup/; revision=35902
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@ -48,7 +48,7 @@ HalpInitializeClock(VOID)
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PKPRCB Prcb = KeGetCurrentPrcb();
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PKPRCB Prcb = KeGetCurrentPrcb();
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ULONG Increment;
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ULONG Increment;
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USHORT RollOver;
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USHORT RollOver;
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ULONG Flags = 0;
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ULONG_PTR Flags = 0;
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/* Check the CPU Type */
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/* Check the CPU Type */
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if (Prcb->CpuType <= 4)
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if (Prcb->CpuType <= 4)
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@ -92,7 +92,7 @@ NTAPI
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HalCalibratePerformanceCounter(IN volatile PLONG Count,
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HalCalibratePerformanceCounter(IN volatile PLONG Count,
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IN ULONGLONG NewCount)
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IN ULONGLONG NewCount)
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{
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{
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ULONG Flags = 0;
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ULONG_PTR Flags = 0;
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/* Disable interrupts */
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/* Disable interrupts */
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Ke386SaveFlags(Flags);
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Ke386SaveFlags(Flags);
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@ -43,7 +43,7 @@
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#define TYPE1_READ(x, y) \
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#define TYPE1_READ(x, y) \
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TYPE1_START(x, y) \
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TYPE1_START(x, y) \
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*((POINTER_TO_(y))Buffer) = \
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*((POINTER_TO_(y))Buffer) = \
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READ_FROM(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i)); \
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READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \
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TYPE1_END(y)
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TYPE1_END(y)
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//
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//
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@ -51,7 +51,7 @@
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//
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//
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#define TYPE1_WRITE(x, y) \
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#define TYPE1_WRITE(x, y) \
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TYPE1_START(x, y) \
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TYPE1_START(x, y) \
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WRITE_TO(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i), \
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WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \
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*((POINTER_TO_(y))Buffer)); \
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*((POINTER_TO_(y))Buffer)); \
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TYPE1_END(y)
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TYPE1_END(y)
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@ -69,7 +69,7 @@
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#define TYPE2_READ(x, y) \
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#define TYPE2_READ(x, y) \
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TYPE2_START(x, y) \
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TYPE2_START(x, y) \
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*((POINTER_TO_(y))Buffer) = \
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*((POINTER_TO_(y))Buffer) = \
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READ_FROM(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT); \
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READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \
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TYPE2_END(y)
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TYPE2_END(y)
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//
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//
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@ -77,7 +77,7 @@
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//
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//
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#define TYPE2_WRITE(x, y) \
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#define TYPE2_WRITE(x, y) \
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TYPE2_START(x, y) \
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TYPE2_START(x, y) \
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WRITE_TO(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT, \
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WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \
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*((POINTER_TO_(y))Buffer)); \
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*((POINTER_TO_(y))Buffer)); \
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TYPE2_END(y)
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TYPE2_END(y)
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@ -35,7 +35,11 @@
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/* Internal kernel headers */
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/* Internal kernel headers */
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#include "internal/pci.h"
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#include "internal/pci.h"
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#ifdef _M_AMD64
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#include "internal/amd64/intrin_i.h"
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#else
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#include "internal/i386/intrin_i.h"
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#include "internal/i386/intrin_i.h"
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#endif
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/* Internal HAL Headers */
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/* Internal HAL Headers */
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#include "apic.h"
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#include "apic.h"
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@ -154,6 +154,17 @@ HalpTrap06(
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VOID
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VOID
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);
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);
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#ifdef _M_AMD64
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#define KfLowerIrql KeLowerIrql
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#ifndef CONFIG_SMP
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/* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
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#define KiAcquireSpinLock(SpinLock)
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#define KiReleaseSpinLock(SpinLock)
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#define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
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#define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
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#endif // !CONFIG_SMP
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#endif // _M_AMD64
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extern PVOID HalpRealModeStart;
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extern PVOID HalpRealModeStart;
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extern PVOID HalpRealModeEnd;
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extern PVOID HalpRealModeEnd;
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