From 84e3ee3768f6f2fdfdd00018fa3be05552dcac9e Mon Sep 17 00:00:00 2001 From: Timo Kreuzer Date: Wed, 24 Mar 2010 20:26:54 +0000 Subject: [PATCH] [NTOS] - fix ExInterlockedPopEntryList and ExInterlockedPushEntryList - Update amd64/mm.h and mm/amd64/init.c to reflect latest trunk changes - make freelist.c compile again svn path=/branches/ros-amd64-bringup/; revision=46403 --- reactos/ntoskrnl/ex/amd64/fastinterlck.c | 9 +- reactos/ntoskrnl/include/internal/amd64/mm.h | 94 ++++++++++++-------- reactos/ntoskrnl/mm/amd64/init.c | 64 ++++++------- reactos/ntoskrnl/mm/amd64/page.c | 5 +- reactos/ntoskrnl/mm/freelist.c | 43 +++++---- 5 files changed, 117 insertions(+), 98 deletions(-) diff --git a/reactos/ntoskrnl/ex/amd64/fastinterlck.c b/reactos/ntoskrnl/ex/amd64/fastinterlck.c index dbd9564327e..b9ca32aab1b 100644 --- a/reactos/ntoskrnl/ex/amd64/fastinterlck.c +++ b/reactos/ntoskrnl/ex/amd64/fastinterlck.c @@ -79,11 +79,11 @@ ExInterlockedPopEntryList(IN PSINGLE_LIST_ENTRY ListHead, IN PKSPIN_LOCK Lock) { KIRQL OldIrql; - PSINGLE_LIST_ENTRY OldHead = NULL; + PSINGLE_LIST_ENTRY FirstEntry; KeAcquireSpinLock(Lock, &OldIrql); - if (!ListHead->Next) OldHead = PopEntryList(ListHead); + FirstEntry = PopEntryList(ListHead); KeReleaseSpinLock(Lock, OldIrql); - return OldHead; + return FirstEntry; } PSINGLE_LIST_ENTRY @@ -94,7 +94,8 @@ ExInterlockedPushEntryList(IN PSINGLE_LIST_ENTRY ListHead, KIRQL OldIrql; PSINGLE_LIST_ENTRY OldHead = NULL; KeAcquireSpinLock(Lock, &OldIrql); - if (!ListHead->Next) OldHead = PushEntryList(ListHead, ListEntry); + OldHead = ListHead->Next; + PushEntryList(ListHead, ListEntry); KeReleaseSpinLock(Lock, OldIrql); return OldHead; } diff --git a/reactos/ntoskrnl/include/internal/amd64/mm.h b/reactos/ntoskrnl/include/internal/amd64/mm.h index eb1ef0f6ff9..a1952915416 100644 --- a/reactos/ntoskrnl/include/internal/amd64/mm.h +++ b/reactos/ntoskrnl/include/internal/amd64/mm.h @@ -2,8 +2,7 @@ * Lowlevel memory managment definitions */ -#ifndef __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H -#define __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H +#pragma once /* Helper macros */ #define PAGE_MASK(x) ((x)&(~0xfff)) @@ -22,8 +21,25 @@ #define MI_NONPAGED_POOL_END (PVOID)0xFFFFFAE000000000ULL #define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL +#define MI_SYSTEM_CACHE_WS_START (PVOID)0xFFFFF78000001000ULL // CHECKME - +/* Memory sizes */ +#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT) +#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT) +#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT) +#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) +#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) +#define MI_MAX_FREE_PAGE_LISTS 4 +#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024) +#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024) +#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024) +#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024) +#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024) +#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \ + MI_SESSION_POOL_SIZE + \ + MI_SESSION_IMAGE_SIZE + \ + MI_SESSION_WORKING_SET_SIZE) +#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024) #define MI_NUMBER_SYSTEM_PTES 22000 PULONG64 @@ -53,21 +69,23 @@ MiAddressToPpe(PVOID Address) PMMPTE FORCEINLINE -MiAddressToPde(PVOID Address) +_MiAddressToPde(PVOID Address) { ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3); Offset &= 0x7FFFFFF << 3; return (PMMPTE)(PDE_BASE + Offset); } +#define MiAddressToPde(x) _MiAddressToPde((PVOID)(x)) PMMPTE FORCEINLINE -MiAddressToPte(PVOID Address) +_MiAddressToPte(PVOID Address) { ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3); Offset &= 0xFFFFFFFFFULL << 3; return (PMMPTE)(PTE_BASE + Offset); } +#define MiAddressToPte(x) _MiAddressToPte((PVOID)(x)) /* Convert a PTE into a corresponding address */ PVOID @@ -90,9 +108,9 @@ MiIsPdeForAddressValid(PVOID Address) (MiAddressToPde(Address)->u.Hard.Valid)); } -//#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE)) -//#define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE))) -//#define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE) +#define ADDR_TO_PAGE_TABLE(v) (((ULONG_PTR)(v)) / (512 * PAGE_SIZE)) +#define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))) +#define ADDR_TO_PTE_OFFSET(v) ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE) #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF) #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF) @@ -117,8 +135,6 @@ MmInitGlobalKernelPageDirectory(VOID) #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0) #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE) -/// MIARM.H - /* Easy accessing PFN in PTE */ #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber) @@ -128,43 +144,47 @@ MmInitGlobalKernelPageDirectory(VOID) #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1) #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1) #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0) +#if !defined(CONFIG_SMP) #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1) +#else +#define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1) +#endif #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1) #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1) #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1) +#if !defined(CONFIG_SMP) #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1) +#else +#define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1) +#endif +#if 0 // FIXME +#define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \ + ((x) / (4*1024*1024)) -#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT) -#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT) -#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT) -#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) -#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) -#define MI_MAX_FREE_PAGE_LISTS 4 +#define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \ + ((((x)) % (4*1024*1024)) / (4*1024)) +#endif -#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024) +#define NR_SECTION_PAGE_TABLES 1024 +#define NR_SECTION_PAGE_ENTRIES 1024 -#define MI_SESSION_VIEW_SIZE (20 * 1024 * 1024) -#define MI_SESSION_POOL_SIZE (16 * 1024 * 1024) -#define MI_SESSION_IMAGE_SIZE (8 * 1024 * 1024) -#define MI_SESSION_WORKING_SET_SIZE (4 * 1024 * 1024) -#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \ - MI_SESSION_POOL_SIZE + \ - MI_SESSION_IMAGE_SIZE + \ - MI_SESSION_WORKING_SET_SIZE) +//#define TEB_BASE 0x7FFDE000 -#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024) +#define MI_HYPERSPACE_PTES (256 - 1) +#define MI_ZERO_PTES (32) +#define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE +#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \ + MI_HYPERSPACE_PTES * PAGE_SIZE) +#define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ + PAGE_SIZE) - -#define MM_HIGHEST_VAD_ADDRESS \ - (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE)) +/* On x86, these two are the same */ +#define MMPDE MMPTE +#define PMMPDE PMMPTE +/* +* FIXME - different architectures have different cache line sizes... +*/ +#define MM_CACHE_LINE_SIZE 32 -// -// FIXFIX: These should go in ex.h after the pool merge -// -#define POOL_LISTS_PER_PAGE (PAGE_SIZE / sizeof(LIST_ENTRY)) -#define BASE_POOL_TYPE_MASK 1 -#define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + sizeof(LIST_ENTRY))) - -#endif /* __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H */ diff --git a/reactos/ntoskrnl/mm/amd64/init.c b/reactos/ntoskrnl/mm/amd64/init.c index 4555478b39c..e740ef78bb4 100644 --- a/reactos/ntoskrnl/mm/amd64/init.c +++ b/reactos/ntoskrnl/mm/amd64/init.c @@ -27,21 +27,21 @@ HalInitializeBios(ULONG Unknown, PLOADER_PARAMETER_BLOCK LoaderBlock); /* GLOBALS *****************************************************************/ /* Sizes */ -ULONG64 MmBootImageSize; -ULONG64 MmMinimumNonPagedPoolSize = 256 * 1024; -ULONG64 MmSizeOfNonPagedPoolInBytes; -ULONG64 MmMaximumNonPagedPoolInBytes; -ULONG64 MmMaximumNonPagedPoolPercent; -ULONG64 MmMinAdditionNonPagedPoolPerMb = 32 * 1024; -ULONG64 MmMaxAdditionNonPagedPoolPerMb = 400 * 1024; -ULONG64 MmDefaultMaximumNonPagedPool = 1024 * 1024; -ULONG64 MmSessionSize = MI_SESSION_SIZE; -ULONG64 MmSessionViewSize = MI_SESSION_VIEW_SIZE; -ULONG64 MmSessionPoolSize = MI_SESSION_POOL_SIZE; -ULONG64 MmSessionImageSize = MI_SESSION_IMAGE_SIZE; -ULONG64 MmSystemViewSize = MI_SYSTEM_VIEW_SIZE; -ULONG64 MmSizeOfPagedPoolInBytes = MI_MIN_INIT_PAGED_POOLSIZE; -ULONG64 MiNonPagedSystemSize; +//SIZE_T MmBootImageSize; +//SIZE_T MmMinimumNonPagedPoolSize = 256 * 1024; +//SIZE_T MmSizeOfNonPagedPoolInBytes; +//SIZE_T MmMaximumNonPagedPoolInBytes; +//ULONG MmMaximumNonPagedPoolPercent; +//ULONG MmMinAdditionNonPagedPoolPerMb = 32 * 1024; +//ULONG MmMaxAdditionNonPagedPoolPerMb = 400 * 1024; +//SIZE_T MmDefaultMaximumNonPagedPool = 1024 * 1024; +//SIZE_T MmSessionSize = MI_SESSION_SIZE; +SIZE_T MmSessionViewSize = MI_SESSION_VIEW_SIZE; +SIZE_T MmSessionPoolSize = MI_SESSION_POOL_SIZE; +SIZE_T MmSessionImageSize = MI_SESSION_IMAGE_SIZE; +SIZE_T MmSystemViewSize = MI_SYSTEM_VIEW_SIZE; +//SIZE_T MmSizeOfPagedPoolInBytes = MI_MIN_INIT_PAGED_POOLSIZE; +SIZE_T MiNonPagedSystemSize; /* Address ranges */ ULONG64 MmUserProbeAddress = 0x7FFFFFF0000ULL; @@ -57,24 +57,24 @@ PVOID MiSessionImageEnd; // FFFFF98000000000 = MiSessionS PVOID MiSessionSpaceEnd = MI_SESSION_SPACE_END; // FFFFF98000000000 PVOID MmSystemCacheStart; // FFFFF98000000000 PVOID MmSystemCacheEnd; // FFFFFA8000000000 -PVOID MmPagedPoolStart = MI_PAGED_POOL_START; // FFFFFA8000000000 +/// PVOID MmPagedPoolStart = MI_PAGED_POOL_START; // FFFFFA8000000000 PVOID MmPagedPoolEnd; // FFFFFAA000000000 PVOID MiSystemViewStart; PVOID MmNonPagedSystemStart; // FFFFFAA000000000 PVOID MmNonPagedPoolStart; PVOID MmNonPagedPoolExpansionStart; -PVOID MmNonPagedPoolEnd = MI_NONPAGED_POOL_END; // 0xFFFFFAE000000000 +///PVOID MmNonPagedPoolEnd = MI_NONPAGED_POOL_END; // 0xFFFFFAE000000000 PVOID MmHyperSpaceEnd = (PVOID)HYPER_SPACE_END; -PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock; -ULONG MmNumberOfPhysicalPages, MmHighestPhysicalPage, MmLowestPhysicalPage = -1; // FIXME: ULONG64 +//PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock; +//ULONG MmNumberOfPhysicalPages, MmHighestPhysicalPage, MmLowestPhysicalPage = -1; // FIXME: ULONG64 -ULONG MmNumberOfSystemPtes; -PMMPTE MmSystemPagePtes; +//ULONG MmNumberOfSystemPtes; +//PMMPTE MmSystemPagePtes; MMSUPPORT MmSystemCacheWs; -RTL_BITMAP MiPfnBitMap; -ULONG64 MxPfnAllocation; +//RTL_BITMAP MiPfnBitMap; +//ULONG64 MxPfnAllocation; ULONG64 MxPfnSizeInBytes; PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor; @@ -86,8 +86,8 @@ BOOLEAN MiIncludeType[LoaderMaximum]; PFN_NUMBER MxFreePageBase; ULONG64 MxFreePageCount = 0; -PFN_NUMBER MmSystemPageDirectory; -PFN_NUMBER MmSizeOfPagedPoolInPages = MI_MIN_INIT_PAGED_POOLSIZE / PAGE_SIZE; +extern PFN_NUMBER MmSystemPageDirectory; +//PFN_NUMBER MmSizeOfPagedPoolInPages = MI_MIN_INIT_PAGED_POOLSIZE / PAGE_SIZE; BOOLEAN MiPfnsInitialized = FALSE; @@ -187,7 +187,7 @@ MiEarlyAllocPage() if (MiPfnsInitialized) { - return MmAllocPage(MC_SYSTEM, 0); + return MmAllocPage(MC_SYSTEM); } /* Make sure we have enough pages */ @@ -308,7 +308,7 @@ MiPreparePfnDatabse(IN PLOADER_PARAMETER_BLOCK LoaderBlock) MxPfnAllocation = MxPfnSizeInBytes >> PAGE_SHIFT; /* Simply start at hardcoded address */ - MmPfnDatabase = MI_PFN_DATABASE; + MmPfnDatabase[1] = MI_PFN_DATABASE; /* Loop the memory descriptors */ for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink; @@ -552,7 +552,7 @@ MiBuildNonPagedPool(VOID) } /* Initialize the ARM3 nonpaged pool */ - MiInitializeArmPool(); + MiInitializeNonPagedPool(); /* Initialize the nonpaged pool */ InitializePool(NonPagedPool, 0); @@ -693,7 +693,7 @@ MiBuildPhysicalMemoryBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock) VOID NTAPI -MiBuildPagedPool(VOID) +MiBuildPagedPool_x(VOID) { PMMPTE Pte; MMPTE TmplPte; @@ -737,7 +737,7 @@ MiBuildPagedPool(VOID) if (!Pte->u.Flush.Valid) { /* Map it! */ - TmplPte.u.Flush.PageFrameNumber = MmAllocPage(MC_SYSTEM, 0); + TmplPte.u.Flush.PageFrameNumber = MmAllocPage(MC_SYSTEM); *Pte = TmplPte; } @@ -817,7 +817,7 @@ MiBuildPagedPool(VOID) NTSTATUS NTAPI -MmArmInitSystem(IN ULONG Phase, +MmArmInitSystem_x(IN ULONG Phase, IN PLOADER_PARAMETER_BLOCK LoaderBlock) { if (Phase == 0) @@ -829,7 +829,7 @@ MmArmInitSystem(IN ULONG Phase, MiEvaluateMemoryDescriptors(LoaderBlock); /* Start PFN database at hardcoded address */ - MmPfnDatabase = MI_PFN_DATABASE; + MmPfnDatabase[1] = MI_PFN_DATABASE; /* Prepare PFN database mappings */ MiPreparePfnDatabse(LoaderBlock); diff --git a/reactos/ntoskrnl/mm/amd64/page.c b/reactos/ntoskrnl/mm/amd64/page.c index a96e519140a..bc15126eff6 100644 --- a/reactos/ntoskrnl/mm/amd64/page.c +++ b/reactos/ntoskrnl/mm/amd64/page.c @@ -15,7 +15,7 @@ #undef InterlockedExchangePte #define InterlockedExchangePte(pte1, pte2) \ - InterlockedExchange64(&pte1->u.Long, pte2.u.Long) + InterlockedExchange64((LONG64*)&pte1->u.Long, pte2.u.Long) #define PAGE_EXECUTE_ANY (PAGE_EXECUTE|PAGE_EXECUTE_READ|PAGE_EXECUTE_READWRITE|PAGE_EXECUTE_WRITECOPY) #define PAGE_WRITE_ANY (PAGE_EXECUTE_READWRITE|PAGE_READWRITE|PAGE_EXECUTE_WRITECOPY|PAGE_WRITECOPY) @@ -251,7 +251,6 @@ NTAPI MmGetPageProtect(PEPROCESS Process, PVOID Address) { MMPTE Pte; - ULONG Protect; Pte.u.Long = MiGetPteValueForProcess(Process, Address); @@ -362,7 +361,7 @@ MmDeleteVirtualMapping( if (Pte) { /* Atomically set the entry to zero and get the old value. */ - OldPte.u.Long = InterlockedExchange64(&Pte->u.Long, 0); + OldPte.u.Long = InterlockedExchange64((LONG64*)&Pte->u.Long, 0); if (OldPte.u.Hard.Valid) { diff --git a/reactos/ntoskrnl/mm/freelist.c b/reactos/ntoskrnl/mm/freelist.c index 0221fc77721..8eaecc46c6e 100644 --- a/reactos/ntoskrnl/mm/freelist.c +++ b/reactos/ntoskrnl/mm/freelist.c @@ -27,14 +27,9 @@ // // ReactOS to NT Physical Page Descriptor Entry Legacy Mapping Definitions // -// REACTOS NT -// -#define RmapListHead AweReferenceCount -#define PHYSICAL_PAGE MMPFN -#define PPHYSICAL_PAGE PMMPFN - -/* The first array contains ReactOS PFNs, the second contains ARM3 PFNs */ -PPHYSICAL_PAGE MmPfnDatabase[2]; +typedef union +{ + MMPFN;// Pfn; struct { @@ -61,18 +56,22 @@ PPHYSICAL_PAGE MmPfnDatabase[2]; C_ASSERT(sizeof(PHYSICAL_PAGE) == sizeof(MMPFN)); -#define MiGetPfnEntry(Pfn) ((PPHYSICAL_PAGE)MiGetPfnEntry(Pfn)) +//#define MiGetPfnEntry(Pfn) ((PPHYSICAL_PAGE)MiGetPfnEntry(Pfn)) #define MiGetPfnEntryIndex(x) MiGetPfnEntryIndex((struct _MMPFN*)x) #define LockCount Flags.LockCount -PMMPFN MmPfnDatabase; -#define MmPfnDatabase ((PPHYSICAL_PAGE)MmPfnDatabase) +/* The first array contains ReactOS PFNs, the second contains ARM3 PFNs */ +PMMPFN MmPfnDatabase[2]; +#define MmPfnDatabase ((PPHYSICAL_PAGE*)MmPfnDatabase) -#define MMPFN PHYSICAL_PAGE -#define PMMPFN PPHYSICAL_PAGE +//#define MMPFN PHYSICAL_PAGE +//#define PMMPFN PPHYSICAL_PAGE -ULONG MmAvailablePages; -ULONG MmResidentAvailablePages; +/* The first array contains ReactOS PFNs, the second contains ARM3 PFNs */ +//PPHYSICAL_PAGE MmPfnDatabase[2]; + +PFN_NUMBER MmAvailablePages; +PFN_NUMBER MmResidentAvailablePages; SIZE_T MmTotalCommitLimit; SIZE_T MmTotalCommittedPages; @@ -108,7 +107,7 @@ MiInitializeUserPfnBitmap(VOID) RtlClearAllBits(&MiUserPfnBitMap); } -PFN_TYPE +PFN_NUMBER NTAPI MmGetLRUFirstUserPage(VOID) { @@ -371,7 +370,7 @@ MiAllocatePagesForMdl(IN PHYSICAL_ADDRESS LowAddress, PFN_NUMBER PageCount, LowPage, HighPage, SkipPages, PagesFound = 0, Page; PPFN_NUMBER MdlPage, LastMdlPage; KIRQL OldIrql; - PPHYSICAL_PAGE Pfn1; + PMMPFN Pfn1; INT LookForZeroedPages; ASSERT (KeGetCurrentIrql() <= APC_LEVEL); @@ -608,7 +607,7 @@ NTAPI MmDumpPfnDatabase(VOID) { ULONG i; - PPHYSICAL_PAGE Pfn1; + PMMPFN Pfn1; PCHAR State = "????", Type = "Unknown"; KIRQL OldIrql; ULONG Totals[5] = {0}, FreePages = 0; @@ -646,7 +645,7 @@ MmDumpPfnDatabase(VOID) State, Type, Pfn1->u3.e2.ReferenceCount, - Pfn1->RmapListHead); + ((PPHYSICAL_PAGE)Pfn1)->RmapListHead); } DbgPrint("Nonpaged Pool: %d pages\t[%d KB]\n", Totals[MC_NPPOOL], (Totals[MC_NPPOOL] << PAGE_SHIFT) / 1024); @@ -742,7 +741,7 @@ MmSetRmapListHeadPage(PFN_NUMBER Pfn, struct _MM_RMAP_ENTRY* ListHead) KIRQL oldIrql; oldIrql = KeAcquireQueuedSpinLock(LockQueuePfnLock); - MiGetPfnEntry(Pfn)->RmapListHead = (LONG_PTR)ListHead; + ((PPHYSICAL_PAGE)MiGetPfnEntry(Pfn))->RmapListHead = (LONG_PTR)ListHead; KeReleaseQueuedSpinLock(LockQueuePfnLock, oldIrql); } @@ -754,7 +753,7 @@ MmGetRmapListHeadPage(PFN_NUMBER Pfn) struct _MM_RMAP_ENTRY* ListHead; oldIrql = KeAcquireQueuedSpinLock(LockQueuePfnLock); - ListHead = (struct _MM_RMAP_ENTRY*)MiGetPfnEntry(Pfn)->RmapListHead; + ListHead = (struct _MM_RMAP_ENTRY*)((PPHYSICAL_PAGE)MiGetPfnEntry(Pfn))->RmapListHead; KeReleaseQueuedSpinLock(LockQueuePfnLock, oldIrql); return(ListHead); @@ -833,7 +832,7 @@ MmIsPageInUse(PFN_NUMBER Pfn) VOID NTAPI -MiSetConsumer(IN PFN_TYPE Pfn, +MiSetConsumer(IN PFN_NUMBER Pfn, IN ULONG Type) { MiGetPfnEntry(Pfn)->u3.e1.PageLocation = ActiveAndValid;