[NTOSKRNL]

- Add MM_HAL_VA_END and use it in MiAddHalIoMappings instead of making assumptions about the page tables
- Add MM_SHARED_USER_DATA_VA for x86
- use MM_SHARED_USER_DATA_VA in Mm to avoid ambiguities
- fix or comment out USER_SHARED_DATA in asm headers, as it should be the kernel mode address here
- set Teb->ExceptionList to NULL on amd64, it is used as a link to the Wow64 TEB, if any

svn path=/trunk/; revision=55445

reactos/hal/halx86/apic/rtctimer.c

@@ -19,10 +19,10 @@
 const UCHAR HalpClockVector = 0xD1;
 BOOLEAN HalpClockSetMSRate;
 UCHAR HalpNextMSRate;
-UCHAR HalpCurrentRate = 9;  /* Initial rate  9: 128 Hz / 7,8 ms */
+UCHAR HalpCurrentRate = 9;  /* Initial rate  9: 128 Hz / 7.8 ms */
 ULONG HalpCurrentTimeIncrement;
-static UCHAR RtcMinimumClockRate = 6;  /* Minimum rate  6:  16 Hz / 62,5 ms */
+static UCHAR RtcMinimumClockRate = 6;  /* Minimum rate  6:  16 Hz / 62.5 ms */
-static UCHAR RtcMaximumClockRate = 10; /* Maximum rate 10: 256 Hz / 3,9 ms */
+static UCHAR RtcMaximumClockRate = 10; /* Maximum rate 10: 256 Hz / 3.9 ms */
 
 
 ULONG
@@ -131,7 +131,7 @@ HalpClockInterruptHandler(IN PKTRAP_FRAME TrapFrame)
     if (HalpClockSetMSRate)
     {
         /* Set new clock rate */
-        RtcSetClockRate(HalpCurrentRate);
+        RtcSetClockRate(HalpNextMSRate);
 
         /* We're done */
         HalpClockSetMSRate = FALSE;

reactos/include/asm/ksx.template.h

@@ -240,7 +240,7 @@ CONSTANT(Executive),
 CONSTANT(FALSE),
 CONSTANT(TRUE),
 CONSTANT(DBG_STATUS_CONTROL_C),
-CONSTANTPTR(USER_SHARED_DATA),
+//CONSTANTPTR(USER_SHARED_DATA), // FIXME: we need the kernel mode address here!
 //CONSTANT(MM_SHARED_USER_DATA_VA),
 CONSTANT(PAGE_SIZE),
 //CONSTANT(KERNEL_STACK_CONTROL_LARGE_STACK),

reactos/include/ndk/amd64/ketypes.h

@@ -164,6 +164,7 @@ Author:
 #define INITIAL_STALL_COUNT     100
 #define HYPERSPACE_BASE         0xfffff70000000000ULL
 #define MM_HAL_VA_START         0xFFFFFFFFFFC00000ULL /* This is Vista+ */
+#define MM_HAL_VA_END           0xFFFFFFFFFFFFFFFFULL
 #define APIC_BASE               0xFFFFFFFFFFFE0000ULL
 
 //

reactos/include/ndk/i386/ketypes.h

@@ -142,6 +142,7 @@ Author:
 #define HYPERSPACE_BASE         0xc0800000
 #endif
 #define MM_HAL_VA_START         0xFFC00000
+#define MM_HAL_VA_END           0xFFFFFFFF
 #define APIC_BASE               0xFFFE0000
 
 //

reactos/include/ndk/i386/mmtypes.h

@@ -31,6 +31,11 @@ Author:
 #define MM_ALLOCATION_GRANULARITY         0x10000
 #define MM_ALLOCATION_GRANULARITY_SHIFT   16L
 
+//
+// Address of the shared user page
+//
+#define MM_SHARED_USER_DATA_VA 0x7FFE0000
+
 //
 // Sanity checks for Paging Macros
 //

reactos/include/reactos/ks386.inc

@@ -182,7 +182,7 @@ Executive = 0x0
 FALSE = 0x0
 TRUE = 0x1
 DBG_STATUS_CONTROL_C = 0x1
-USER_SHARED_DATA = 0x7ffe0000
+USER_SHARED_DATA = 0xffdf0000
 PAGE_SIZE = 0x1000
 MAXIMUM_IDTVECTOR = 0xff
 PRIMARY_VECTOR_BASE = 0x30

reactos/include/reactos/ksamd64.inc

@@ -182,7 +182,7 @@ Executive = 0x0
 FALSE = 0x0
 TRUE = 0x1
 DBG_STATUS_CONTROL_C = 0x1
-USER_SHARED_DATA = 0x7ffe0000
+USER_SHARED_DATA = 0xffdf0000
 PAGE_SIZE = 0x1000
 MAXIMUM_IDTVECTOR = 0xff
 PRIMARY_VECTOR_BASE = 0x30

reactos/ntoskrnl/mm/ARM3/mminit.c

@@ -1284,9 +1284,9 @@ INIT_FUNCTION
 MiAddHalIoMappings(VOID)
 {
     PVOID BaseAddress;
-    PMMPDE PointerPde;
+    PMMPDE PointerPde, LastPde;
     PMMPTE PointerPte;
-    ULONG i, j, PdeCount;
+    ULONG j;
     PFN_NUMBER PageFrameIndex;
 
     /* HAL Heap address -- should be on a PDE boundary */
@@ -1295,8 +1295,9 @@ MiAddHalIoMappings(VOID)
 
     /* Check how many PDEs the heap has */
     PointerPde = MiAddressToPde(BaseAddress);
-    PdeCount = PDE_COUNT - MiGetPdeOffset(BaseAddress);
+    LastPde = MiAddressToPde((PVOID)MM_HAL_VA_END);
-    for (i = 0; i < PdeCount; i++)
+
+    while (PointerPde <= LastPde)
     {
         /* Does the HAL own this mapping? */
         if ((PointerPde->u.Hard.Valid == 1) &&

reactos/ntoskrnl/mm/ARM3/pagfault.c

@@ -56,7 +56,7 @@ MiCheckVirtualAddress(IN PVOID VirtualAddress,
     ASSERT(MI_IS_SESSION_ADDRESS(VirtualAddress) == FALSE);
 
     /* Special case for shared data */
-    if (PAGE_ALIGN(VirtualAddress) == (PVOID)USER_SHARED_DATA)
+    if (PAGE_ALIGN(VirtualAddress) == (PVOID)MM_SHARED_USER_DATA_VA)
     {
         /* It's a read-only page */
         *ProtectCode = MM_READONLY;

reactos/ntoskrnl/mm/ARM3/procsup.c

@@ -29,7 +29,7 @@ MiRosTakeOverSharedUserPage(IN PEPROCESS Process)
     NTSTATUS Status;
     PMEMORY_AREA MemoryArea;
     PHYSICAL_ADDRESS BoundaryAddressMultiple;
-    PVOID AllocatedBase = (PVOID)USER_SHARED_DATA;
+    PVOID AllocatedBase = (PVOID)MM_SHARED_USER_DATA_VA;
     BoundaryAddressMultiple.QuadPart = 0;
 
     Status = MmCreateMemoryArea(&Process->Vm,
@@ -830,7 +830,11 @@ MmCreateTeb(IN PEPROCESS Process,
         //
         // Set TIB Data
         //
+#ifdef _M_AMD64
+        Teb->NtTib.ExceptionList = NULL;
+#else
         Teb->NtTib.ExceptionList = EXCEPTION_CHAIN_END;
+#endif
         Teb->NtTib.Self = (PNT_TIB)Teb;
 
         //

reactos/ntoskrnl/mm/ARM3/virtual.c

@@ -2360,7 +2360,7 @@ MiQueryMemoryBasicInformation(IN HANDLE ProcessHandle,
 
     /* Check for illegal addresses in user-space, or the shared memory area */
     if ((BaseAddress > MM_HIGHEST_VAD_ADDRESS) ||
-        (PAGE_ALIGN(BaseAddress) == (PVOID)USER_SHARED_DATA))
+        (PAGE_ALIGN(BaseAddress) == (PVOID)MM_SHARED_USER_DATA_VA))
     {
         Address = PAGE_ALIGN(BaseAddress);
 
@@ -2370,9 +2370,9 @@ MiQueryMemoryBasicInformation(IN HANDLE ProcessHandle,
         MemoryInfo.Type = MEM_PRIVATE;
 
         /* Special case for shared data */
-        if (Address == (PVOID)USER_SHARED_DATA)
+        if (Address == (PVOID)MM_SHARED_USER_DATA_VA)
         {
-            MemoryInfo.AllocationBase = (PVOID)USER_SHARED_DATA;
+            MemoryInfo.AllocationBase = (PVOID)MM_SHARED_USER_DATA_VA;
             MemoryInfo.State = MEM_COMMIT;
             MemoryInfo.Protect = PAGE_READONLY;
             MemoryInfo.RegionSize = PAGE_SIZE;