mirror of
https://github.com/reactos/reactos.git
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[NTVDM]
- Add stubs for VDDReserve/ReleaseIrqLine; - Add stub implementation for Direct Memory Access; - Add corresponding exports. svn path=/trunk/; revision=65437
This commit is contained in:
Hermès Bélusca-Maïto
parent
fc11139981
commit
83303b29d9
6 changed files with 570 additions and 12 deletions
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@ -19,6 +19,7 @@ list(APPEND SOURCE
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cpu/cpu.c
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cpu/registers.c
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hardware/cmos.c
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hardware/dma.c
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hardware/keyboard.c
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hardware/mouse.c
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hardware/pic.c
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@ -22,6 +22,7 @@
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#include "clock.h"
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#include "bios/rom.h"
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#include "hardware/cmos.h"
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#include "hardware/dma.h"
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#include "hardware/keyboard.h"
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#include "hardware/mouse.h"
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#include "hardware/pic.h"
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@ -626,6 +627,7 @@ BOOLEAN EmulatorInitialize(HANDLE ConsoleInput, HANDLE ConsoleOutput)
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CpuInitialize();
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/* Initialize DMA */
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DmaInitialize();
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/* Initialize the PIC, the PIT, the CMOS and the PC Speaker */
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PicInitialize();
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@ -706,6 +708,8 @@ VOID EmulatorCleanup(VOID)
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// PitCleanup();
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// PicCleanup();
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// DmaCleanup();
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CpuCleanup();
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#ifdef STANDALONE
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462
reactos/subsystems/ntvdm/hardware/dma.c
Normal file
462
reactos/subsystems/ntvdm/hardware/dma.c
Normal file
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@ -0,0 +1,462 @@
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/*
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* COPYRIGHT: GPL - See COPYING in the top level directory
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* PROJECT: ReactOS Virtual DOS Machine
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* FILE: dma.c
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* PURPOSE: Direct Memory Access Controller emulation -
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* i8237A compatible with 74LS612 Memory Mapper extension
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* PROGRAMMERS: Hermes Belusca-Maito (hermes.belusca@sfr.fr)
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*/
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/* INCLUDES *******************************************************************/
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#define NDEBUG
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#include "emulator.h"
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#include "io.h"
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#include "dma.h"
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/* PRIVATE VARIABLES **********************************************************/
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/*
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* DMA Controller 0 (Channels 0..3): Slave controller
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* DMA Controller 1 (Channels 4..7): Master controller
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*/
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static DMA_CONTROLLER DmaControllers[DMA_CONTROLLERS];
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/* External page registers for each channel of the two DMA controllers */
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static DMA_PAGE_REGISTER DmaPageRegisters[DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS];
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/* PRIVATE FUNCTIONS **********************************************************/
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#define READ_ADDR(CtrlIndex, ChanIndex, Data) \
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do { \
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(Data) = \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].CurrAddress + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)); \
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DmaControllers[(CtrlIndex)].FlipFlop ^= 1; \
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} while(0)
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#define READ_CNT(CtrlIndex, ChanIndex, Data) \
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do { \
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(Data) = \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].CurrWordCnt + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)); \
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DmaControllers[(CtrlIndex)].FlipFlop ^= 1; \
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} while(0)
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static BYTE WINAPI DmaReadPort(USHORT Port)
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{
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BYTE ReadValue = 0xFF;
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switch (Port)
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{
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/* Start Address Registers */
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{
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case 0x00:
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READ_ADDR(0, 0, ReadValue);
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return ReadValue;
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case 0x02:
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READ_ADDR(0, 1, ReadValue);
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return ReadValue;
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case 0x04:
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READ_ADDR(0, 2, ReadValue);
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return ReadValue;
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case 0x06:
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READ_ADDR(0, 3, ReadValue);
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return ReadValue;
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case 0xC0:
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READ_ADDR(1, 0, ReadValue);
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return ReadValue;
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case 0xC4:
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READ_ADDR(1, 1, ReadValue);
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return ReadValue;
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case 0xC8:
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READ_ADDR(1, 2, ReadValue);
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return ReadValue;
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case 0xCC:
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READ_ADDR(1, 3, ReadValue);
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return ReadValue;
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}
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/* Count Address Registers */
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{
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case 0x01:
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READ_CNT(0, 0, ReadValue);
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return ReadValue;
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case 0x03:
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READ_CNT(0, 1, ReadValue);
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return ReadValue;
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case 0x05:
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READ_CNT(0, 2, ReadValue);
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return ReadValue;
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case 0x07:
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READ_CNT(0, 3, ReadValue);
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return ReadValue;
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case 0xC2:
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READ_CNT(1, 0, ReadValue);
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return ReadValue;
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case 0xC6:
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READ_CNT(1, 1, ReadValue);
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return ReadValue;
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case 0xCA:
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READ_CNT(1, 2, ReadValue);
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return ReadValue;
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case 0xCE:
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READ_CNT(1, 3, ReadValue);
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return ReadValue;
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}
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/* Status Registers */
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{
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case 0x08:
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return DmaControllers[0].Status;
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case 0xD0:
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return DmaControllers[1].Status;
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}
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/* DMA Intermediate (Temporary) Registers */
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{
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case 0x0D:
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return DmaControllers[0].TempReg;
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case 0xDA:
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return DmaControllers[1].TempReg;
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}
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}
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return 0x00;
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}
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#define WRITE_ADDR(CtrlIndex, ChanIndex, Data) \
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do { \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].BaseAddress + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)) = (Data); \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].CurrAddress + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)) = (Data); \
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DmaControllers[(CtrlIndex)].FlipFlop ^= 1; \
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} while(0)
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#define WRITE_CNT(CtrlIndex, ChanIndex, Data) \
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do { \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].BaseWordCnt + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)) = (Data); \
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*((PBYTE)&DmaControllers[(CtrlIndex)].DmaChannel[(ChanIndex)].CurrWordCnt + \
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(DmaControllers[(CtrlIndex)].FlipFlop & 0x01)) = (Data); \
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DmaControllers[(CtrlIndex)].FlipFlop ^= 1; \
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} while(0)
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static VOID WINAPI DmaWritePort(USHORT Port, BYTE Data)
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{
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switch (Port)
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{
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/* Start Address Registers */
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{
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case 0x00:
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WRITE_ADDR(0, 0, Data);
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break;
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case 0x02:
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WRITE_ADDR(0, 1, Data);
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break;
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case 0x04:
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WRITE_ADDR(0, 2, Data);
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break;
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case 0x06:
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WRITE_ADDR(0, 3, Data);
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break;
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case 0xC0:
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WRITE_ADDR(1, 0, Data);
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break;
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case 0xC4:
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WRITE_ADDR(1, 1, Data);
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break;
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case 0xC8:
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WRITE_ADDR(1, 2, Data);
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break;
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case 0xCC:
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WRITE_ADDR(1, 3, Data);
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break;
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}
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/* Count Address Registers */
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{
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case 0x01:
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WRITE_CNT(0, 0, Data);
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break;
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case 0x03:
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WRITE_CNT(0, 1, Data);
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break;
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case 0x05:
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WRITE_CNT(0, 2, Data);
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break;
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case 0x07:
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WRITE_CNT(0, 3, Data);
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break;
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case 0xC2:
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WRITE_CNT(1, 0, Data);
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break;
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case 0xC6:
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WRITE_CNT(1, 1, Data);
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break;
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case 0xCA:
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WRITE_CNT(1, 2, Data);
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break;
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case 0xCE:
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WRITE_CNT(1, 3, Data);
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break;
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}
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/* Command Registers */
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{
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case 0x08:
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DmaControllers[0].Command = Data;
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break;
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case 0xD0:
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DmaControllers[1].Command = Data;
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break;
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}
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/* Request Registers */
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{
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case 0x09:
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DmaControllers[0].Request = Data;
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break;
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case 0xD2:
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DmaControllers[1].Request = Data;
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break;
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}
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/* Flip-Flop Reset */
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{
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case 0x0C:
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DmaControllers[0].FlipFlop = 0;
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break;
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case 0xD8:
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DmaControllers[1].FlipFlop = 0;
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break;
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}
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/* DMA Master Reset */
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{
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case 0x0D:
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DmaControllers[0].Command = 0x00;
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DmaControllers[0].Status = 0x00;
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DmaControllers[0].Request = 0x00;
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DmaControllers[0].TempReg = 0x00;
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DmaControllers[0].FlipFlop = 0;
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DmaControllers[0].Mask = 0x0F;
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break;
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case 0xDA:
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DmaControllers[1].Command = 0x00;
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DmaControllers[1].Status = 0x00;
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DmaControllers[1].Request = 0x00;
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DmaControllers[1].TempReg = 0x00;
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DmaControllers[1].FlipFlop = 0;
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DmaControllers[1].Mask = 0x0F;
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break;
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}
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}
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}
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/* Page Address Registers */
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static BYTE WINAPI DmaPageReadPort(USHORT Port)
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{
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switch (Port)
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{
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case 0x87:
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return DmaPageRegisters[0].Page;
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case 0x83:
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return DmaPageRegisters[1].Page;
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case 0x81:
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return DmaPageRegisters[2].Page;
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case 0x82:
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return DmaPageRegisters[3].Page;
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case 0x8F:
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return DmaPageRegisters[4].Page;
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case 0x8B:
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return DmaPageRegisters[5].Page;
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case 0x89:
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return DmaPageRegisters[6].Page;
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case 0x8A:
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return DmaPageRegisters[7].Page;
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}
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return 0x00;
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}
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static VOID WINAPI DmaPageWritePort(USHORT Port, BYTE Data)
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{
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switch (Port)
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{
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case 0x87:
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DmaPageRegisters[0].Page = Data;
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break;
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case 0x83:
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DmaPageRegisters[1].Page = Data;
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break;
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case 0x81:
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DmaPageRegisters[2].Page = Data;
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break;
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case 0x82:
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DmaPageRegisters[3].Page = Data;
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break;
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case 0x8F:
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DmaPageRegisters[4].Page = Data;
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break;
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case 0x8B:
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DmaPageRegisters[5].Page = Data;
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break;
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case 0x89:
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DmaPageRegisters[6].Page = Data;
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break;
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case 0x8A:
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DmaPageRegisters[7].Page = Data;
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break;
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}
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}
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/* PUBLIC FUNCTIONS ***********************************************************/
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VOID DmaInitialize(VOID)
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{
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/* Register the I/O Ports */
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/* Channels 0(Reserved)..3 */
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RegisterIoPort(0x00, NULL, DmaWritePort); /* Start Address Register 0 (Reserved) */
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RegisterIoPort(0x01, NULL, DmaWritePort); /* Count Address Register 0 (Reserved) */
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RegisterIoPort(0x02, NULL, DmaWritePort); /* Start Address Register 1 */
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RegisterIoPort(0x03, NULL, DmaWritePort); /* Count Address Register 1 */
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RegisterIoPort(0x04, NULL, DmaWritePort); /* Start Address Register 2 */
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RegisterIoPort(0x05, NULL, DmaWritePort); /* Count Address Register 2 */
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RegisterIoPort(0x06, NULL, DmaWritePort); /* Start Address Register 3 */
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RegisterIoPort(0x07, NULL, DmaWritePort); /* Count Address Register 3 */
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RegisterIoPort(0x08, DmaReadPort, DmaWritePort); /* Status (Read) / Command (Write) Registers */
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RegisterIoPort(0x09, NULL, DmaWritePort); /* Request Register */
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RegisterIoPort(0x0A, NULL, DmaWritePort); /* Single Channel Mask Register */
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RegisterIoPort(0x0B, NULL, DmaWritePort); /* Mode Register */
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RegisterIoPort(0x0C, NULL, DmaWritePort); /* Flip-Flop Reset Register */
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RegisterIoPort(0x0D, DmaReadPort, DmaWritePort); /* Intermediate (Read) / Master Reset (Write) Registers */
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RegisterIoPort(0x0E, NULL, DmaWritePort); /* Mask Reset Register */
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RegisterIoPort(0x0F, DmaReadPort, DmaWritePort); /* Multi-Channel Mask Reset Register */
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/* Channels 4(Reserved)..7 */
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RegisterIoPort(0xC0, NULL, DmaWritePort); /* Start Address Register 4 (Reserved) */
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RegisterIoPort(0xC2, NULL, DmaWritePort); /* Count Address Register 4 (Reserved) */
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RegisterIoPort(0xC4, NULL, DmaWritePort); /* Start Address Register 5 */
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RegisterIoPort(0xC6, NULL, DmaWritePort); /* Count Address Register 5 */
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RegisterIoPort(0xC8, NULL, DmaWritePort); /* Start Address Register 6 */
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RegisterIoPort(0xCA, NULL, DmaWritePort); /* Count Address Register 6 */
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RegisterIoPort(0xCC, NULL, DmaWritePort); /* Start Address Register 7 */
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RegisterIoPort(0xCE, NULL, DmaWritePort); /* Count Address Register 7 */
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RegisterIoPort(0xD0, DmaReadPort, DmaWritePort); /* Status (Read) / Command (Write) Registers */
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RegisterIoPort(0xD2, NULL, DmaWritePort); /* Request Register */
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RegisterIoPort(0xD4, NULL, DmaWritePort); /* Single Channel Mask Register */
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RegisterIoPort(0xD6, NULL, DmaWritePort); /* Mode Register */
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RegisterIoPort(0xD8, NULL, DmaWritePort); /* Flip-Flop Reset Register */
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RegisterIoPort(0xDA, DmaReadPort, DmaWritePort); /* Intermediate (Read) / Master Reset (Write) Registers */
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RegisterIoPort(0xDC, NULL, DmaWritePort); /* Mask Reset Register */
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RegisterIoPort(0xDE, DmaReadPort, DmaWritePort); /* Multi-Channel Mask Reset Register */
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/* Channels Page Address Registers */
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RegisterIoPort(0x87, DmaPageReadPort, DmaPageWritePort); /* Channel 0 (Reserved) */
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RegisterIoPort(0x83, DmaPageReadPort, DmaPageWritePort); /* Channel 1 */
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RegisterIoPort(0x81, DmaPageReadPort, DmaPageWritePort); /* Channel 2 */
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RegisterIoPort(0x82, DmaPageReadPort, DmaPageWritePort); /* Channel 3 */
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RegisterIoPort(0x8F, DmaPageReadPort, DmaPageWritePort); /* Channel 4 (Reserved) */
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RegisterIoPort(0x8B, DmaPageReadPort, DmaPageWritePort); /* Channel 5 */
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RegisterIoPort(0x89, DmaPageReadPort, DmaPageWritePort); /* Channel 6 */
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RegisterIoPort(0x8A, DmaPageReadPort, DmaPageWritePort); /* Channel 7 */
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}
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DWORD
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WINAPI
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VDDRequestDMA(IN HANDLE hVdd,
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IN WORD iChannel,
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IN OUT PVOID Buffer,
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IN DWORD length)
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{
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UNREFERENCED_PARAMETER(hVdd);
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if (iChannel >= DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS)
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{
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SetLastError(ERROR_INVALID_ADDRESS);
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return FALSE;
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}
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UNIMPLEMENTED;
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return 0;
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}
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BOOL
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WINAPI
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VDDQueryDMA(IN HANDLE hVdd,
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IN WORD iChannel,
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IN PVDD_DMA_INFO pDmaInfo)
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{
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PDMA_CONTROLLER pDcp;
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WORD Channel;
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UNREFERENCED_PARAMETER(hVdd);
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if (iChannel >= DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS)
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{
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SetLastError(ERROR_INVALID_ADDRESS);
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return FALSE;
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}
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pDcp = &DmaControllers[iChannel / DMA_CONTROLLER_CHANNELS];
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Channel = iChannel % DMA_CONTROLLER_CHANNELS;
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pDmaInfo->addr = pDcp->DmaChannel[Channel].CurrAddress;
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pDmaInfo->count = pDcp->DmaChannel[Channel].CurrWordCnt;
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// pDmaInfo->page = DmaPageRegisters[iChannel].Page;
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pDmaInfo->status = pDcp->Status;
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pDmaInfo->mode = pDcp->DmaChannel[Channel].Mode;
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pDmaInfo->mask = pDcp->Mask;
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return TRUE;
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}
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BOOL
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WINAPI
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VDDSetDMA(IN HANDLE hVdd,
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IN WORD iChannel,
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IN WORD fDMA,
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IN PVDD_DMA_INFO pDmaInfo)
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{
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PDMA_CONTROLLER pDcp;
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WORD Channel;
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|
||||
UNREFERENCED_PARAMETER(hVdd);
|
||||
|
||||
if (iChannel >= DMA_CONTROLLERS * DMA_CONTROLLER_CHANNELS)
|
||||
{
|
||||
SetLastError(ERROR_INVALID_ADDRESS);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
pDcp = &DmaControllers[iChannel / DMA_CONTROLLER_CHANNELS];
|
||||
Channel = iChannel % DMA_CONTROLLER_CHANNELS;
|
||||
|
||||
if (fDMA & VDD_DMA_ADDR)
|
||||
pDcp->DmaChannel[Channel].CurrAddress = pDmaInfo->addr;
|
||||
|
||||
if (fDMA & VDD_DMA_COUNT)
|
||||
pDcp->DmaChannel[Channel].CurrWordCnt = pDmaInfo->count;
|
||||
|
||||
// if (fDMA & VDD_DMA_PAGE)
|
||||
// DmaPageRegisters[iChannel].Page = pDmaInfo->page;
|
||||
|
||||
if (fDMA & VDD_DMA_STATUS)
|
||||
pDcp->Status = pDmaInfo->status;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
64
reactos/subsystems/ntvdm/hardware/dma.h
Normal file
64
reactos/subsystems/ntvdm/hardware/dma.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* COPYRIGHT: GPL - See COPYING in the top level directory
|
||||
* PROJECT: ReactOS Virtual DOS Machine
|
||||
* FILE: dma.h
|
||||
* PURPOSE: Direct Memory Access Controller emulation -
|
||||
* i8237A compatible with 74LS612 Memory Mapper extension
|
||||
* PROGRAMMERS: Hermes Belusca-Maito (hermes.belusca@sfr.fr)
|
||||
*/
|
||||
|
||||
#ifndef _DMA_H_
|
||||
#define _DMA_H_
|
||||
|
||||
/* INCLUDES *******************************************************************/
|
||||
|
||||
#include "ntvdm.h"
|
||||
|
||||
/* DEFINES ********************************************************************/
|
||||
|
||||
#define DMA_CONTROLLERS 2
|
||||
#define DMA_CONTROLLER_CHANNELS 4 // Each DMA controller has 4 channels
|
||||
|
||||
typedef struct _DMA_CHANNEL
|
||||
{
|
||||
WORD BaseAddress;
|
||||
WORD BaseWordCnt;
|
||||
WORD CurrAddress;
|
||||
WORD CurrWordCnt;
|
||||
BYTE Mode;
|
||||
} DMA_CHANNEL, *PDMA_CHANNEL;
|
||||
|
||||
typedef struct _DMA_CONTROLLER
|
||||
{
|
||||
DMA_CHANNEL DmaChannel[DMA_CONTROLLER_CHANNELS];
|
||||
|
||||
WORD TempAddress;
|
||||
WORD TempWordCnt;
|
||||
|
||||
BYTE TempReg;
|
||||
|
||||
BYTE Command;
|
||||
BYTE Request;
|
||||
BYTE Mask;
|
||||
BYTE Status;
|
||||
|
||||
BOOLEAN FlipFlop; // 0: LSB ; 1: MSB
|
||||
|
||||
} DMA_CONTROLLER, *PDMA_CONTROLLER;
|
||||
|
||||
/* 74LS612 Memory Mapper extension */
|
||||
typedef struct _DMA_PAGE_REGISTER
|
||||
{
|
||||
BYTE Page;
|
||||
} DMA_PAGE_REGISTER, *PDMA_PAGE_REGISTER;
|
||||
|
||||
// The 74LS612 contains 16 bytes, each of them being a page register.
|
||||
// They are accessible via ports 0x80 through 0x8F .
|
||||
|
||||
/* FUNCTIONS ******************************************************************/
|
||||
|
||||
VOID DmaInitialize(VOID);
|
||||
|
||||
#endif // _DMA_H_
|
||||
|
||||
/* EOF */
|
||||
|
|
@ -349,4 +349,24 @@ call_ica_hw_interrupt(INT ms,
|
|||
}
|
||||
}
|
||||
|
||||
WORD
|
||||
WINAPI
|
||||
VDDReserveIrqLine(IN HANDLE hVdd,
|
||||
IN WORD IrqLine)
|
||||
{
|
||||
UNIMPLEMENTED;
|
||||
SetLastError(ERROR_INVALID_PARAMETER);
|
||||
return 0xFFFF;
|
||||
}
|
||||
|
||||
BOOL
|
||||
WINAPI
|
||||
VDDReleaseIrqLine(IN HANDLE hVdd,
|
||||
IN WORD IrqLine)
|
||||
{
|
||||
UNIMPLEMENTED;
|
||||
SetLastError(ERROR_INVALID_PARAMETER);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* EOF */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; NTVDM Registers exports ;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;;;;;;;;;;;;;;;;;;;;
|
||||
;; NTVDM Registers ;;
|
||||
;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
@ stdcall getAF()
|
||||
@ stdcall getAH()
|
||||
|
|
@ -90,9 +90,9 @@
|
|||
@ stdcall setZF(long)
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; NTVDM CCPU MIPS exports ;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; NTVDM CCPU MIPS Compatibility ;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
@ stdcall c_getAF() getAF
|
||||
@ stdcall c_getAH() getAH
|
||||
|
|
@ -179,9 +179,9 @@
|
|||
@ stdcall c_setZF(long) setZF
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; NTVDM DOS-32 Emulation exports ;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; NTVDM DOS-32 Emulation ;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
@ stdcall demClientErrorEx(long long long)
|
||||
@ stdcall demFileDelete(ptr)
|
||||
|
|
@ -200,9 +200,9 @@
|
|||
;@ stdcall demWOWLFNInit
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; NTVDM Miscellaneous exports ;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; NTVDM Miscellaneous ;;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
@ stdcall MGetVdmPointer(long long long)
|
||||
@ stdcall Sim32pGetVDMPointer(long long)
|
||||
|
|
@ -212,9 +212,16 @@
|
|||
;@ stdcall VdmUnmapFlat(long long ptr long) ; Not exported on x86
|
||||
|
||||
@ stdcall call_ica_hw_interrupt(long long long)
|
||||
@ stdcall VDDReserveIrqLine(long long)
|
||||
@ stdcall VDDReleaseIrqLine(long long)
|
||||
|
||||
@ stdcall VDDInstallIOHook(long long ptr ptr)
|
||||
@ stdcall VDDDeInstallIOHook(long long ptr)
|
||||
|
||||
@ stdcall VDDRequestDMA(long long ptr long)
|
||||
@ stdcall VDDQueryDMA(long long ptr)
|
||||
@ stdcall VDDSetDMA(long long long ptr)
|
||||
|
||||
@ stdcall VDDSimulate16()
|
||||
@ stdcall host_simulate() VDDSimulate16
|
||||
@ stdcall VDDTerminateVDM()
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue