diff --git a/reactos/hal/halx86/mp/halinit_mp.c b/reactos/hal/halx86/mp/halinit_mp.c
index 89f023f2122..d3e1faf89d5 100644
--- a/reactos/hal/halx86/mp/halinit_mp.c
+++ b/reactos/hal/halx86/mp/halinit_mp.c
@@ -22,7 +22,7 @@ ULONG_PTR KernelBase;
 
 /***************************************************************************/
 
-VOID NTAPI HalpInitPICs(VOID)
+VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts)
 {
     UNIMPLEMENTED;
 }
diff --git a/reactos/hal/halx86/mp/ioapic.c b/reactos/hal/halx86/mp/ioapic.c
index 1e2702a22fb..414147816aa 100644
--- a/reactos/hal/halx86/mp/ioapic.c
+++ b/reactos/hal/halx86/mp/ioapic.c
@@ -32,7 +32,7 @@ ULONG IRQVectorMap[MAX_IRQ_SOURCE];             /* IRQ to vector map */
  * EISA conforming in the MP table, that means its trigger type must
  * be read in from the ELCR */
 
-#define default_EISA_trigger(idx)	(EISA_ELCR(IRQMap[idx].SrcBusIrq))
+#define default_EISA_trigger(idx)	(EISA_ELCR_Read(IRQMap[idx].SrcBusIrq))
 #define default_EISA_polarity(idx)	(0)
 
 /* ISA interrupts are always polarity zero edge triggered,
@@ -64,7 +64,7 @@ VOID IOAPICWrite(ULONG Apic, ULONG Offset, ULONG Value);
 /*
  * EISA Edge/Level control register, ELCR
  */
-static ULONG EISA_ELCR(ULONG irq)
+static ULONG EISA_ELCR_Read(ULONG irq)
 {
    if (irq < 16) 
    {