mirror of
https://github.com/reactos/reactos.git
synced 2025-02-22 16:36:33 +00:00
[NTOS]: Context switch in C instead of ASM. Can be made more portable, but it's a good start. Unless Timo rewrites it.
svn path=/trunk/; revision=49520
This commit is contained in:
Sir Richard
parent
58e3fc91d5
commit
77d20c89bf
2 changed files with 159 additions and 277 deletions
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@ -40,284 +40,16 @@
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.globl @KiSwapContextInternal@0
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.func @KiSwapContextInternal@0, @KiSwapContextInternal@0
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@KiSwapContextInternal@0:
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/* Set APC Bypass Disable and old thread pointer */
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mov edx, edi
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or dl, cl
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/* Save the IRQL */
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push ecx
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#ifdef CONFIG_SMP
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GetSwapLock:
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/* Acquire the swap lock */
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cmp byte ptr [esi+KTHREAD_SWAP_BUSY], 0
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jz NotBusy
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pause
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jmp GetSwapLock
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NotBusy:
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#endif
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/* Increase context switches (use ES for lazy load) */
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inc dword ptr es:[ebx+KPCR_CONTEXT_SWITCHES]
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/* Save the Exception list */
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push [ebx+KPCR_EXCEPTION_LIST]
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/* Check for WMI */
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cmp dword ptr [ebx+KPCR_PERF_GLOBAL_GROUP_MASK], 0
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jnz WmiTrace
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AfterTrace:
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#ifdef CONFIG_SMP
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#if DBG
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/* Assert that we're on the right CPU */
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mov cl, [esi+KTHREAD_NEXT_PROCESSOR]
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cmp cl, [ebx+KPCR_PROCESSOR_NUMBER]
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jnz WrongCpu
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#endif
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#endif
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/* Get CR0 and save it */
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mov ebp, cr0
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mov edx, ebp
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#ifdef CONFIG_SMP
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/* Check NPX State */
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cmp byte ptr [edi+KTHREAD_NPX_STATE], NPX_STATE_LOADED
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jz NpxLoaded
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SetStack:
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#endif
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/* Set new stack */
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mov [edi+KTHREAD_KERNEL_STACK], esp
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/* Checking NPX, disable interrupts now */
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mov eax, [esi+KTHREAD_INITIAL_STACK]
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cli
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/* Get the NPX State */
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movzx ecx, byte ptr [esi+KTHREAD_NPX_STATE]
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/* Clear the other bits, merge in CR0, merge in FPU CR0 bits and compare */
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and edx, ~(CR0_MP + CR0_EM + CR0_TS)
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or ecx, edx
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or ecx, [eax - (NPX_FRAME_LENGTH - FN_CR0_NPX_STATE)]
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cmp ebp, ecx
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jnz NewCr0
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StackOk:
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/* Enable interrupts and set the current stack */
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sti
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mov esp, [esi+KTHREAD_KERNEL_STACK]
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/* Check if address space switch is needed */
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mov ebp, [esi+KTHREAD_APCSTATE_PROCESS]
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mov eax, [edi+KTHREAD_APCSTATE_PROCESS]
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cmp ebp, eax
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jz SameProcess
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#ifdef CONFIG_SMP
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/* Get the active processors and XOR with the process' */
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mov ecx, [ebx+KPCR_SET_MEMBER_COPY]
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lock xor [ebp+KPROCESS_ACTIVE_PROCESSORS], ecx
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lock xor [eax+KPROCESS_ACTIVE_PROCESSORS], ecx
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/* Assert change went ok */
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#if DBG
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test [ebp+KPROCESS_ACTIVE_PROCESSORS], ecx
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jz WrongActiveCpu
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test [eax+KPROCESS_ACTIVE_PROCESSORS], ecx
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jnz WrongActiveCpu
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#endif
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#endif
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/* Check if we need an LDT */
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mov ecx, [ebp+KPROCESS_LDT_DESCRIPTOR0]
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or ecx, [eax+KPROCESS_LDT_DESCRIPTOR0]
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jnz LdtReload
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UpdateCr3:
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/* Switch address space */
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mov eax, [ebp+KPROCESS_DIRECTORY_TABLE_BASE]
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mov cr3, eax
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SameProcess:
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#ifdef CONFIG_SMP
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/* Release swap lock */
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and byte ptr [edi+KTHREAD_SWAP_BUSY], 0
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#endif
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/* Clear gs */
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xor eax, eax
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mov gs, ax
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/* Set the TEB */
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mov eax, [esi+KTHREAD_TEB]
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mov [ebx+KPCR_TEB], eax
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mov ecx, [ebx+KPCR_GDT]
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mov [ecx+0x3A], ax
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shr eax, 16
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mov [ecx+0x3C], al
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mov [ecx+0x3F], ah
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/* Get stack pointer */
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mov eax, [esi+KTHREAD_INITIAL_STACK]
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/* Make space for the NPX Frame */
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sub eax, NPX_FRAME_LENGTH
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/* Check if this isn't V86 Mode, so we can bias the Esp0 */
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test dword ptr [eax - KTRAP_FRAME_SIZE + KTRAP_FRAME_EFLAGS], EFLAGS_V86_MASK
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jnz NoAdjust
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/* Bias esp */
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sub eax, KTRAP_FRAME_V86_GS - KTRAP_FRAME_SS
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NoAdjust:
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/* Set new ESP0 */
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mov ecx, [ebx+KPCR_TSS]
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mov [ecx+KTSS_ESP0], eax
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/* Set current IOPM offset in the TSS */
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mov ax, [ebp+KPROCESS_IOPM_OFFSET]
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mov [ecx+KTSS_IOMAPBASE], ax
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/* Increase context switches */
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inc dword ptr [esi+KTHREAD_CONTEXT_SWITCHES]
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/* Restore exception list */
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pop [ebx+KPCR_EXCEPTION_LIST]
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/* Restore IRQL */
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pop ecx
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/* DPC shouldn't be active */
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cmp byte ptr [ebx+KPCR_PRCB_DPC_ROUTINE_ACTIVE], 0
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jnz BugCheckDpc
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/* Check if kernel APCs are pending */
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cmp byte ptr [esi+KTHREAD_PENDING_KERNEL_APC], 0
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jnz CheckApc
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/* No APCs, return */
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xor eax, eax
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ret
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CheckApc:
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/* Check if they're disabled */
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cmp word ptr [esi+KTHREAD_SPECIAL_APC_DISABLE], 0
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jnz ApcReturn
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test cl, cl
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jz ApcReturn
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/* Request APC Delivery */
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mov cl, APC_LEVEL
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call @HalRequestSoftwareInterrupt@4
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or eax, esp
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ApcReturn:
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/* Return with APC pending */
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setz al
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ret
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LdtReload:
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/* Check if it's empty */
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mov eax, [ebp+KPROCESS_LDT_DESCRIPTOR0]
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test eax, eax
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jz LoadLdt
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/* Write the LDT Selector */
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mov ecx, [ebx+KPCR_GDT]
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mov [ecx+KGDT_LDT], eax
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mov eax, [ebp+KPROCESS_LDT_DESCRIPTOR1]
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mov [ecx+KGDT_LDT+4], eax
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/* Write the INT21 handler */
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mov ecx, [ebx+KPCR_IDT]
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mov eax, [ebp+KPROCESS_INT21_DESCRIPTOR0]
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mov [ecx+0x108], eax
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mov eax, [ebp+KPROCESS_INT21_DESCRIPTOR1]
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mov [ecx+0x10C], eax
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/* Save LDT Selector */
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mov eax, KGDT_LDT
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LoadLdt:
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lldt ax
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jmp UpdateCr3
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NewCr0:
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#if DBG
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/* Assert NPX State */
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test byte ptr [esi+KTHREAD_NPX_STATE], ~(NPX_STATE_NOT_LOADED)
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jnz InvalidNpx
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test dword ptr [eax - (NPX_FRAME_LENGTH - FN_CR0_NPX_STATE)], ~(CR0_PE + CR0_MP + CR0_EM + CR0_TS)
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jnz InvalidNpx
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#endif
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/* Update CR0 */
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mov cr0, ecx
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jmp StackOk
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#ifdef CONFIG_SMP
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NpxLoaded:
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/* Mask out FPU flags */
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and edx, ~(CR0_MP + CR0_EM + CR0_TS)
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/* Get the NPX Frame */
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mov ecx, [edi+KTHREAD_INITIAL_STACK]
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sub ecx, NPX_FRAME_LENGTH
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/* Check if we have a new CR0 */
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cmp ebp, edx
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jz Cr0Equal
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/* We do, update it */
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mov cr0, edx
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mov ebp, edx
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Cr0Equal:
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/* Save the NPX State */
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fxsave [ecx]
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mov byte ptr [edi+KTHREAD_NPX_STATE], NPX_STATE_NOT_LOADED
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/* Clear the NPX Thread */
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mov dword ptr [ebx+KPCR_NPX_THREAD], 0
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/* Jump back */
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jmp SetStack
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#endif
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WmiTrace:
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/* No WMI support yet */
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int 3
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/* Jump back */
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jmp AfterTrace
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BugCheckDpc:
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/* Bugcheck the machine, printing out the threads being switched */
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mov eax, [edi+KTHREAD_INITIAL_STACK]
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push 0
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push eax
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push esi
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push edi
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push ATTEMPTED_SWITCH_FROM_DPC
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call _KeBugCheckEx@20
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#if DBG
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InvalidNpx:
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int 3
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WrongActiveCpu:
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int 3
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WrongCpu:
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int 3
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#endif
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/* Build switch frame */
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sub esp, 2 * 4
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mov ecx, esp
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call @KiSwapContextEntry@8
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mov ecx, 0xB00BFACA
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jmp $
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.endfunc
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/*++
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@ -511,6 +243,20 @@ _Ki386SetupAndExitToV86Mode@4:
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jmp $
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.endfunc
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.globl @KiSwitchThreads@8
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.func @KiSwitchThreads@8, @KiSwitchThreads@8
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@KiSwitchThreads@8:
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/* Load the new kernel stack and switch OS to new thread */
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mov esp, [edx+KTHREAD_KERNEL_STACK]
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mov edx, esp
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call @KiSwapContextExit@8
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/* Now we're on the new thread. Return to the caller to restore registers */
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add esp, 2 * 4
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ret
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.endfunc
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.globl @Ki386BiosCallReturnAddress@4
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@Ki386BiosCallReturnAddress@4:
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@ -42,6 +42,13 @@ typedef struct _KKINIT_FRAME
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FX_SAVE_AREA FxSaveArea;
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} KKINIT_FRAME, *PKKINIT_FRAME;
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VOID
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FASTCALL
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KiSwitchThreads(
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IN PKTHREAD OldThread,
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IN PKTHREAD NewThread
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);
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/* FUNCTIONS *****************************************************************/
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VOID
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@ -311,4 +318,133 @@ KiIdleLoop(VOID)
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}
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}
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BOOLEAN
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FASTCALL
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KiSwapContextExit(IN PKTHREAD OldThread,
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IN PKSWITCHFRAME SwitchFrame)
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{
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PKIPCR Pcr = (PKIPCR)KeGetPcr();
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PKPROCESS OldProcess, NewProcess;
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PKGDTENTRY GdtEntry;
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PKTHREAD NewThread;
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PKUINIT_FRAME InitFrame;
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/* We are on the new thread stack now */
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NewThread = Pcr->PrcbData.CurrentThread;
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/* Now we are the new thread. Check if it's in a new process */
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OldProcess = OldThread->ApcState.Process;
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NewProcess = NewThread->ApcState.Process;
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if (OldProcess != NewProcess)
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{
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/* Check if there is a different LDT */
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if (*(PULONGLONG)&OldProcess->LdtDescriptor != *(PULONGLONG)&NewProcess->LdtDescriptor)
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{
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DPRINT1("LDT switch not implemented\n");
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ASSERT(FALSE);
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}
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/* Switch address space and flush TLB */
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__writecr3(NewProcess->DirectoryTableBase[0]);
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}
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/* Clear GS */
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Ke386SetGs(0);
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/* Set the TEB */
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Pcr->NtTib.Self = (PVOID)NewThread->Teb;
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GdtEntry = &Pcr->GDT[KGDT_R3_TEB / sizeof(KGDTENTRY)];
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GdtEntry->BaseLow = (USHORT)((ULONG_PTR)NewThread->Teb & 0xFFFF);
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GdtEntry->HighWord.Bytes.BaseMid = (UCHAR)((ULONG_PTR)NewThread->Teb >> 16);
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GdtEntry->HighWord.Bytes.BaseHi = (UCHAR)((ULONG_PTR)NewThread->Teb >> 24);
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/* Set new TSS fields */
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InitFrame = (PKUINIT_FRAME)NewThread->InitialStack - 1;
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Pcr->TSS->Esp0 = (ULONG_PTR)&InitFrame->TrapFrame;
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if (!(InitFrame->TrapFrame.EFlags & EFLAGS_V86_MASK))
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{
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Pcr->TSS->Esp0 -= (FIELD_OFFSET(KTRAP_FRAME, V86Gs) - FIELD_OFFSET(KTRAP_FRAME, HardwareSegSs));
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}
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Pcr->TSS->IoMapBase = NewProcess->IopmOffset;
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/* Increase thread context switches */
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NewThread->ContextSwitches++;
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/* Load data from switch frame */
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Pcr->NtTib.ExceptionList = SwitchFrame->ExceptionList;
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/* DPCs shouldn't be active */
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if (Pcr->PrcbData.DpcRoutineActive)
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{
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/* Crash the machine */
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KeBugCheckEx(ATTEMPTED_SWITCH_FROM_DPC,
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(ULONG_PTR)OldThread,
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(ULONG_PTR)NewThread,
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(ULONG_PTR)OldThread->InitialStack,
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0);
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}
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/* Kernel APCs may be pending */
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if (NewThread->ApcState.KernelApcPending)
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{
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/* Are APCs enabled? */
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if (!NewThread->SpecialApcDisable)
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{
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/* Request APC delivery */
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if (!SwitchFrame->ApcBypassDisable) HalRequestSoftwareInterrupt(APC_LEVEL);
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return TRUE;
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}
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}
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/* Return */
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return FALSE;
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}
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VOID
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FASTCALL
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KiSwapContextEntry(IN PKSWITCHFRAME SwitchFrame,
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IN ULONG_PTR OldThreadAndApcFlag)
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{
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PKIPCR Pcr = (PKIPCR)KeGetPcr();
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PKTHREAD OldThread, NewThread;
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ULONG Cr0, NewCr0;
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/* Switch threads, check for APC disable */
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ASSERT(OldThreadAndApcFlag &~ 1);
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/* Save APC bypass disable */
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SwitchFrame->ApcBypassDisable = OldThreadAndApcFlag & 3;
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SwitchFrame->ExceptionList = Pcr->NtTib.ExceptionList;
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/* Increase context switch count and check if tracing is enabled */
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Pcr->ContextSwitches++;
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if (Pcr->PerfGlobalGroupMask)
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{
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/* We don't support this yet on x86 either */
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DPRINT1("WMI Tracing not supported\n");
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ASSERT(FALSE);
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}
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/* Get thread pointers */
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OldThread = (PKTHREAD)(OldThreadAndApcFlag & ~3);
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NewThread = Pcr->PrcbData.CurrentThread;
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/* Get the old thread and set its kernel stack */
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OldThread->KernelStack = SwitchFrame;
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/* ISRs can change FPU state, so disable interrupts while checking */
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_disable();
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/* Get current and new CR0 and check if they've changed */
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Cr0 = __readcr0();
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NewCr0 = NewThread->NpxState |
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(Cr0 & ~(CR0_MP | CR0_EM | CR0_TS)) |
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((PKUINIT_FRAME)NewThread->InitialStack - 1)->FxSaveArea.Cr0NpxState;
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if (Cr0 != NewCr0) __writecr0(NewCr0);
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/* Now enable interrupts and do the switch */
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_enable();
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KiSwitchThreads(OldThread, NewThread);
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}
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/* EOF */
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