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[NTOS:MM] Use MI_ZERO_PTES as the number of usable zeroing PTEs, not the total allocated. CORE-11856

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We'll now have 32 usable zeroing PTEs instead of 31.
MP kernels will (some day) zero up to 32 pages at a time.
This commit is contained in:
Thomas Faber 2017-11-04 14:08:56 +01:00
parent 61c8d3432c
commit 754e175d12
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GPG key ID: 076E7C3D44720826
3 changed files with 10 additions and 9 deletions
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6
ntoskrnl/mm/ARM3/hypermap.c
View file

@ -122,7 +122,7 @@ MiMapPagesInZeroSpace(IN PMMPFN Pfn1,
// //
ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL); ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);
ASSERT(NumberOfPages != 0); ASSERT(NumberOfPages != 0);
ASSERT(NumberOfPages <= (MI_ZERO_PTES - 1)); ASSERT(NumberOfPages <= MI_ZERO_PTES);
// //
// Pick the first zeroing PTE // Pick the first zeroing PTE
@ -138,7 +138,7 @@ MiMapPagesInZeroSpace(IN PMMPFN Pfn1,
// //
// Reset the PTEs // Reset the PTEs
// //
Offset = MI_ZERO_PTES - 1; Offset = MI_ZERO_PTES;
PointerPte->u.Hard.PageFrameNumber = Offset; PointerPte->u.Hard.PageFrameNumber = Offset;
KeFlushProcessTb(); KeFlushProcessTb();
} }
@ -192,7 +192,7 @@ MiUnmapPagesInZeroSpace(IN PVOID VirtualAddress,
// //
ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL); ASSERT(KeGetCurrentIrql() == PASSIVE_LEVEL);
ASSERT (NumberOfPages != 0); ASSERT (NumberOfPages != 0);
ASSERT (NumberOfPages <= (MI_ZERO_PTES - 1)); ASSERT(NumberOfPages <= MI_ZERO_PTES);
// //
// Get the first PTE for the mapped zero VA // Get the first PTE for the mapped zero VA

6
ntoskrnl/mm/ARM3/i386/init.c
View file

@ -522,14 +522,14 @@ MiInitMachineDependent(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
// //
// Reserve system PTEs for zeroing PTEs and clear them // Reserve system PTEs for zeroing PTEs and clear them
// //
MiFirstReservedZeroingPte = MiReserveSystemPtes(MI_ZERO_PTES, MiFirstReservedZeroingPte = MiReserveSystemPtes(MI_ZERO_PTES + 1,
SystemPteSpace); SystemPteSpace);
RtlZeroMemory(MiFirstReservedZeroingPte, MI_ZERO_PTES * sizeof(MMPTE)); RtlZeroMemory(MiFirstReservedZeroingPte, (MI_ZERO_PTES + 1) * sizeof(MMPTE));
// //
// Set the counter to maximum to boot with // Set the counter to maximum to boot with
// //
MiFirstReservedZeroingPte->u.Hard.PageFrameNumber = MI_ZERO_PTES - 1; MiFirstReservedZeroingPte->u.Hard.PageFrameNumber = MI_ZERO_PTES;
/* Lock PFN database */ /* Lock PFN database */
OldIrql = MiAcquirePfnLock(); OldIrql = MiAcquirePfnLock();

7
ntoskrnl/mm/amd64/init.c
View file

@ -382,11 +382,12 @@ MiBuildSystemPteSpace(VOID)
MiInitializeSystemPtes(PointerPte, MmNumberOfSystemPtes, SystemPteSpace); MiInitializeSystemPtes(PointerPte, MmNumberOfSystemPtes, SystemPteSpace);
/* Reserve system PTEs for zeroing PTEs and clear them */ /* Reserve system PTEs for zeroing PTEs and clear them */
MiFirstReservedZeroingPte = MiReserveSystemPtes(MI_ZERO_PTES, SystemPteSpace); MiFirstReservedZeroingPte = MiReserveSystemPtes(MI_ZERO_PTES + 1,
RtlZeroMemory(MiFirstReservedZeroingPte, MI_ZERO_PTES * sizeof(MMPTE)); SystemPteSpace);
RtlZeroMemory(MiFirstReservedZeroingPte, (MI_ZERO_PTES + 1) * sizeof(MMPTE));
/* Set the counter to maximum */ /* Set the counter to maximum */
MiFirstReservedZeroingPte->u.Hard.PageFrameNumber = MI_ZERO_PTES - 1; MiFirstReservedZeroingPte->u.Hard.PageFrameNumber = MI_ZERO_PTES;
} }
static static