mirror of
https://github.com/reactos/reactos.git
synced 2024-12-27 09:34:43 +00:00
[PCI][HALX86] Support PCI debugging devices
Also optimize the PCI bus scanning CORE-17360
This commit is contained in:
Dmitry Borisov
Victor Perevertkin
parent
216d69c59e
commit
734cd5e842
9 changed files with 880 additions and 84 deletions
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@ -49,6 +49,30 @@ FdoLocateChildDevice(
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return STATUS_UNSUCCESSFUL;
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}
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static
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BOOLEAN
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PciIsDebuggingDevice(
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_In_ ULONG Bus,
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_In_ PCI_SLOT_NUMBER SlotNumber)
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{
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ULONG i;
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if (!HasDebuggingDevice)
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return FALSE;
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for (i = 0; i < RTL_NUMBER_OF(PciDebuggingDevice); ++i)
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{
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if (PciDebuggingDevice[i].InUse &&
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PciDebuggingDevice[i].BusNumber == Bus &&
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PciDebuggingDevice[i].DeviceNumber == SlotNumber.u.bits.DeviceNumber &&
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PciDebuggingDevice[i].FunctionNumber == SlotNumber.u.bits.FunctionNumber)
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{
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return TRUE;
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}
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}
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return FALSE;
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}
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static NTSTATUS
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FdoEnumerateDevices(
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@ -92,7 +116,9 @@ FdoEnumerateDevices(
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&PciConfig,
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PCI_COMMON_HDR_LENGTH);
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DPRINT("Size %lu\n", Size);
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if (Size < PCI_COMMON_HDR_LENGTH)
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if (Size != PCI_COMMON_HDR_LENGTH ||
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PciConfig.VendorID == PCI_INVALID_VENDORID ||
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PciConfig.VendorID == 0)
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{
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if (FunctionNumber == 0)
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{
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@ -111,12 +137,6 @@ FdoEnumerateDevices(
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PciConfig.VendorID,
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PciConfig.DeviceID);
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if (PciConfig.VendorID == 0 && PciConfig.DeviceID == 0)
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{
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DPRINT("Filter out devices with null vendor and device ID\n");
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continue;
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}
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Status = FdoLocateChildDevice(&Device, DeviceExtension, SlotNumber, &PciConfig);
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if (!NT_SUCCESS(Status))
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{
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@ -132,6 +152,27 @@ FdoEnumerateDevices(
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Device->BusNumber = DeviceExtension->BusNumber;
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if (PciIsDebuggingDevice(DeviceExtension->BusNumber, SlotNumber))
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{
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Device->IsDebuggingDevice = TRUE;
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/*
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* ReactOS-specific: apply a hack
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* to prevent driver installation for the debugging device.
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* NOTE: Nothing to do for IEEE 1394 devices; NT5.1 and NT5.2
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* support IEEE 1394 debugging.
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*
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* FIXME: We should set the device problem code
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* CM_PROB_USED_BY_DEBUGGER instead.
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*/
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if (PciConfig.BaseClass != PCI_CLASS_SERIAL_BUS_CTLR ||
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PciConfig.SubClass != PCI_SUBCLASS_SB_IEEE1394)
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{
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PciConfig.VendorID = 0xDEAD;
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PciConfig.DeviceID = 0xBEEF;
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}
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}
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RtlCopyMemory(&Device->SlotNumber,
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&SlotNumber,
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sizeof(PCI_SLOT_NUMBER));
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@ -29,6 +29,8 @@ static NTSTATUS NTAPI PciPnpControl(IN PDEVICE_OBJECT DeviceObject, IN PIRP Irp)
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/*** PUBLIC ******************************************************************/
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PPCI_DRIVER_EXTENSION DriverExtension = NULL;
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BOOLEAN HasDebuggingDevice = FALSE;
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PCI_TYPE1_CFG_CYCLE_BITS PciDebuggingDevice[2] = {0};
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/*** PRIVATE *****************************************************************/
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@ -194,6 +196,54 @@ PciUnload(
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UNREFERENCED_PARAMETER(DriverObject);
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}
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static
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CODE_SEG("INIT")
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VOID
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PciLocateKdDevices(VOID)
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{
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ULONG i;
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NTSTATUS Status;
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WCHAR KeyNameBuffer[16];
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ULONG BusNumber, SlotNumber;
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RTL_QUERY_REGISTRY_TABLE QueryTable[3];
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RtlZeroMemory(QueryTable, sizeof(QueryTable));
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QueryTable[0].Flags = RTL_QUERY_REGISTRY_DIRECT | RTL_QUERY_REGISTRY_REQUIRED;
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QueryTable[0].Name = L"Bus";
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QueryTable[0].EntryContext = &BusNumber;
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QueryTable[1].Flags = RTL_QUERY_REGISTRY_DIRECT | RTL_QUERY_REGISTRY_REQUIRED;
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QueryTable[1].Name = L"Slot";
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QueryTable[1].EntryContext = &SlotNumber;
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for (i = 0; i < RTL_NUMBER_OF(PciDebuggingDevice); ++i)
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{
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PCI_SLOT_NUMBER PciSlot;
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RtlStringCbPrintfW(KeyNameBuffer, sizeof(KeyNameBuffer), L"PCI\\Debug\\%d", i);
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Status = RtlQueryRegistryValues(RTL_REGISTRY_SERVICES,
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KeyNameBuffer,
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QueryTable,
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NULL,
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NULL);
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if (!NT_SUCCESS(Status))
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return;
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HasDebuggingDevice = TRUE;
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PciSlot.u.AsULONG = SlotNumber;
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PciDebuggingDevice[i].DeviceNumber = PciSlot.u.bits.DeviceNumber;
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PciDebuggingDevice[i].FunctionNumber = PciSlot.u.bits.FunctionNumber;
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PciDebuggingDevice[i].BusNumber = BusNumber;
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PciDebuggingDevice[i].InUse = TRUE;
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DPRINT1("PCI debugging device %02x:%02x.%x\n",
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BusNumber,
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PciSlot.u.bits.DeviceNumber,
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PciSlot.u.bits.FunctionNumber);
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}
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}
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CODE_SEG("INIT")
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NTSTATUS
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NTAPI
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@ -224,6 +274,8 @@ DriverEntry(
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InitializeListHead(&DriverExtension->BusListHead);
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KeInitializeSpinLock(&DriverExtension->BusListLock);
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PciLocateKdDevices();
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return STATUS_SUCCESS;
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}
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@ -3,6 +3,7 @@
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#include <ntifs.h>
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#include <cmreslist.h>
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#include <ntstrsafe.h>
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#define TAG_PCI '0ICP'
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@ -24,6 +25,8 @@ typedef struct _PCI_DEVICE
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BOOLEAN EnableIoSpace;
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// Enable bus master
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BOOLEAN EnableBusMaster;
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// Whether the device is owned by the KD
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BOOLEAN IsDebuggingDevice;
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} PCI_DEVICE, *PPCI_DEVICE;
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@ -105,12 +108,28 @@ typedef struct _PCI_DRIVER_EXTENSION
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KSPIN_LOCK BusListLock;
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} PCI_DRIVER_EXTENSION, *PPCI_DRIVER_EXTENSION;
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typedef union _PCI_TYPE1_CFG_CYCLE_BITS
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{
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struct
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{
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ULONG InUse:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG DeviceNumber:5;
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ULONG BusNumber:8;
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ULONG Reserved2:8;
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};
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ULONG AsULONG;
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} PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
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/* We need a global variable to get the driver extension,
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* because at least InterfacePciDevicePresent has no
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* other way to get it... */
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extern PPCI_DRIVER_EXTENSION DriverExtension;
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extern BOOLEAN HasDebuggingDevice;
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extern PCI_TYPE1_CFG_CYCLE_BITS PciDebuggingDevice[2];
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/* fdo.c */
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NTSTATUS
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@ -6,6 +6,7 @@ list(APPEND HAL_GENERIC_SOURCE
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generic/dma.c
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generic/drive.c
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generic/halinit.c
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generic/kdpci.c
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generic/memory.c
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generic/misc.c
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generic/nmi.c
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578
hal/halx86/generic/kdpci.c
Normal file
578
hal/halx86/generic/kdpci.c
Normal file
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@ -0,0 +1,578 @@
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/*
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* PROJECT: ReactOS Hardware Abstraction Layer
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* LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
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* PURPOSE: Kernel debugger PCI configurator
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* COPYRIGHT: Copyright 2022 Dmitry Borisov <di.sean@protonmail.com>
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*/
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/*
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* FIXME: We don't use a PCI resource allocator and rely on firmware to
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* have configured PCI devices properly. The KD PCI configurator should
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* allocate and assign PCI resources for all PCI buses
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* before the debugging device can be enabled.
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*/
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/* INCLUDES *******************************************************************/
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#include <hal.h>
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/* GLOBALS ********************************************************************/
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#if defined(EARLY_DEBUG)
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ULONG (*DPRINT0)(_In_ _Printf_format_string_ PCSTR Format, ...);
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#else
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#if defined(_MSC_VER)
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#define DPRINT0 __noop
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#else
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#define DPRINT0
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#endif
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#endif
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PCI_TYPE1_CFG_CYCLE_BITS HalpPciDebuggingDevice[2] = {0};
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/* FUNCTIONS ******************************************************************/
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static
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CODE_SEG("INIT")
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ULONG
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HalpPciBarLength(
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_In_ ULONG CurrentBar,
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_In_ ULONG NextBar)
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{
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ULONG64 Bar;
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ULONG Length;
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Bar = CurrentBar;
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if (CurrentBar & PCI_ADDRESS_IO_SPACE)
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{
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Length = 1 << 2;
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}
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else
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{
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if ((CurrentBar & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT)
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{
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Bar = ((ULONG64)NextBar << 32) | CurrentBar;
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}
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Length = 1 << 4;
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}
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while (!(Bar & Length) && Length)
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{
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Length <<= 1;
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}
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return Length;
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}
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static
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CODE_SEG("INIT")
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BOOLEAN
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HalpConfigureDebuggingDevice(
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_In_ PDEBUG_DEVICE_DESCRIPTOR PciDevice,
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_In_ ULONG PciBus,
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_In_ PCI_SLOT_NUMBER PciSlot,
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_Inout_ PPCI_COMMON_HEADER PciConfig)
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{
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ULONG i, Register;
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Register = PciConfig->Command & ~(PCI_ENABLE_MEMORY_SPACE |
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PCI_ENABLE_IO_SPACE);
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HalpPhase0SetPciDataByOffset(PciBus,
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PciSlot,
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&Register,
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FIELD_OFFSET(PCI_COMMON_HEADER, Command),
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sizeof(USHORT));
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/* Fill out the device descriptor */
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for (i = 0; i < MAXIMUM_DEBUG_BARS; ++i)
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{
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ULONG Length, NextBar;
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PDEBUG_DEVICE_ADDRESS DeviceAddress;
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DeviceAddress = &PciDevice->BaseAddress[i];
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DeviceAddress->Valid = FALSE;
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Register = 0xFFFFFFFF;
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HalpPhase0SetPciDataByOffset(PciBus,
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PciSlot,
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&Register,
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FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[i]),
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sizeof(ULONG));
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HalpPhase0GetPciDataByOffset(PciBus,
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PciSlot,
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&Register,
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FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[i]),
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sizeof(ULONG));
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HalpPhase0SetPciDataByOffset(PciBus,
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PciSlot,
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&PciConfig->u.type0.BaseAddresses[i],
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FIELD_OFFSET(PCI_COMMON_HEADER, u.type0.BaseAddresses[i]),
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sizeof(ULONG));
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if (i < MAXIMUM_DEBUG_BARS - 1)
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NextBar = PciConfig->u.type0.BaseAddresses[i + 1];
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else
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NextBar = 0;
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Length = HalpPciBarLength(Register, NextBar);
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if (Register == 0 || Length == 0)
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continue;
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/* I/O space */
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if (Register & PCI_ADDRESS_IO_SPACE)
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{
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DeviceAddress->Type = CmResourceTypePort;
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DeviceAddress->Length = Length;
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DeviceAddress->Valid = TRUE;
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DeviceAddress->TranslatedAddress =
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UlongToPtr(PciConfig->u.type0.BaseAddresses[i] & PCI_ADDRESS_IO_ADDRESS_MASK);
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DPRINT0("BAR[%u] IO %lx, length 0x%lx, 0x%lx\n",
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i,
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DeviceAddress->TranslatedAddress,
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Length,
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Register);
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}
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else
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{
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PHYSICAL_ADDRESS PhysicalAddress;
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BOOLEAN SkipBar = FALSE;
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DeviceAddress->Type = CmResourceTypeMemory;
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DeviceAddress->Length = Length;
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DeviceAddress->Valid = TRUE;
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/* 32-bit memory space */
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PhysicalAddress.HighPart = 0;
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PhysicalAddress.LowPart =
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PciConfig->u.type0.BaseAddresses[i] & PCI_ADDRESS_MEMORY_ADDRESS_MASK;
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/* 64-bit memory space */
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if (((Register & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT))
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{
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PhysicalAddress.HighPart = NextBar;
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SkipBar = TRUE;
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}
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DPRINT0("BAR[%u] MEM %I64x, length 0x%lx, 0x%lx\n",
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i,
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PhysicalAddress.QuadPart,
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Length,
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Register);
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if (SkipBar)
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{
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++i;
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}
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DeviceAddress->TranslatedAddress =
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HalpMapPhysicalMemory64(PhysicalAddress, BYTES_TO_PAGES(Length));
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}
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}
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PciDevice->Bus = PciBus;
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PciDevice->Slot = PciSlot.u.AsULONG;
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PciDevice->VendorID = PciConfig->VendorID;
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PciDevice->DeviceID = PciConfig->DeviceID;
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PciDevice->BaseClass = PciConfig->BaseClass;
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PciDevice->SubClass = PciConfig->SubClass;
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PciDevice->ProgIf = PciConfig->ProgIf;
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/* Enable decodes */
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PciConfig->Command |= (PCI_ENABLE_MEMORY_SPACE |
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PCI_ENABLE_IO_SPACE |
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PCI_ENABLE_BUS_MASTER);
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HalpPhase0SetPciDataByOffset(PciBus,
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PciSlot,
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&PciConfig->Command,
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FIELD_OFFSET(PCI_COMMON_HEADER, Command),
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sizeof(USHORT));
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return TRUE;
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}
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static
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CODE_SEG("INIT")
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BOOLEAN
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HalpMatchDebuggingDevice(
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_In_ PDEBUG_DEVICE_DESCRIPTOR PciDevice,
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_In_ ULONG PciBus,
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_In_ PCI_SLOT_NUMBER PciSlot,
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_In_ PPCI_COMMON_HEADER PciConfig)
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{
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/* Check if we weren't given a specific device location */
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if (PciDevice->Bus == 0xFFFFFFFF && PciDevice->Slot == 0xFFFFFFFF)
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{
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if (PciDevice->DeviceID == 0xFFFF && PciDevice->VendorID == 0xFFFF)
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{
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if (PciDevice->BaseClass == PciConfig->BaseClass &&
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PciDevice->SubClass == PciConfig->SubClass)
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{
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if (PciDevice->ProgIf == 0xFF ||
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PciDevice->ProgIf == PciConfig->ProgIf)
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{
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return TRUE;
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}
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}
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}
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else if (PciDevice->DeviceID == PciConfig->DeviceID &&
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PciDevice->VendorID == PciConfig->VendorID)
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{
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return TRUE;
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}
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}
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else if (PciDevice->Bus == PciBus &&
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PciDevice->Slot == PciSlot.u.AsULONG)
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{
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return TRUE;
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}
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return FALSE;
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}
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static
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CODE_SEG("INIT")
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BOOLEAN
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HalpFindMatchingDebuggingDevice(
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_In_ PDEBUG_DEVICE_DESCRIPTOR PciDevice)
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{
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ULONG BusNumber, DeviceNumber, FunctionNumber;
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for (BusNumber = 0; BusNumber < 0xFF; ++BusNumber)
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{
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for (DeviceNumber = 0; DeviceNumber < PCI_MAX_DEVICES; ++DeviceNumber)
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{
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for (FunctionNumber = 0; FunctionNumber < PCI_MAX_FUNCTION; ++FunctionNumber)
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{
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ULONG Bytes;
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PCI_SLOT_NUMBER PciSlot;
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PCI_COMMON_HEADER PciConfig;
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PciSlot.u.bits.DeviceNumber = DeviceNumber;
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PciSlot.u.bits.FunctionNumber = FunctionNumber;
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PciSlot.u.bits.Reserved = 0;
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Bytes = HalpPhase0GetPciDataByOffset(BusNumber,
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PciSlot,
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&PciConfig,
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0,
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PCI_COMMON_HDR_LENGTH);
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if (Bytes != PCI_COMMON_HDR_LENGTH ||
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PciConfig.VendorID == PCI_INVALID_VENDORID ||
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PciConfig.VendorID == 0)
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{
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if (FunctionNumber == 0)
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{
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/* This slot has no single- or a multi-function device */
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break;
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}
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else
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{
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/* Continue scanning the functions */
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continue;
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}
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}
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DPRINT0("Check %02x:%02x.%x [%04x:%04x]\n",
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BusNumber, DeviceNumber, FunctionNumber,
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PciConfig.VendorID, PciConfig.DeviceID);
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|
||||
switch (PCI_CONFIGURATION_TYPE(&PciConfig))
|
||||
{
|
||||
case PCI_DEVICE_TYPE:
|
||||
{
|
||||
if (HalpMatchDebuggingDevice(PciDevice, BusNumber, PciSlot, &PciConfig))
|
||||
{
|
||||
DPRINT0("Found device\n");
|
||||
|
||||
if (HalpConfigureDebuggingDevice(PciDevice,
|
||||
BusNumber,
|
||||
PciSlot,
|
||||
&PciConfig))
|
||||
{
|
||||
DPRINT0("Device is ready\n");
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case PCI_BRIDGE_TYPE:
|
||||
{
|
||||
/* FIXME: Implement PCI resource allocator */
|
||||
break;
|
||||
}
|
||||
|
||||
case PCI_CARDBUS_BRIDGE_TYPE:
|
||||
{
|
||||
/* FIXME: Implement PCI resource allocator */
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (!PCI_MULTIFUNCTION_DEVICE(&PciConfig))
|
||||
{
|
||||
/* The device is a single function device */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
CODE_SEG("INIT")
|
||||
VOID
|
||||
NTAPI
|
||||
HalpRegisterPciDebuggingDeviceInfo(VOID)
|
||||
{
|
||||
ULONG i;
|
||||
NTSTATUS Status;
|
||||
WCHAR StringBuffer[16];
|
||||
BOOLEAN HasDebuggingDevice = FALSE;
|
||||
UNICODE_STRING KeyName = RTL_CONSTANT_STRING(L"\\Registry\\Machine\\System\\"
|
||||
L"CurrentControlSet\\Services\\PCI\\Debug");
|
||||
HANDLE Handle, KeyHandle;
|
||||
|
||||
PAGED_CODE();
|
||||
|
||||
for (i = 0; i < RTL_NUMBER_OF(HalpPciDebuggingDevice); ++i)
|
||||
{
|
||||
if (HalpPciDebuggingDevice[i].InUse)
|
||||
{
|
||||
HasDebuggingDevice = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!HasDebuggingDevice)
|
||||
{
|
||||
/* Nothing to register */
|
||||
return;
|
||||
}
|
||||
|
||||
Status = HalpOpenRegistryKey(&Handle, 0, &KeyName, KEY_ALL_ACCESS, TRUE);
|
||||
if (!NT_SUCCESS(Status))
|
||||
return;
|
||||
|
||||
for (i = 0; i < RTL_NUMBER_OF(HalpPciDebuggingDevice); ++i)
|
||||
{
|
||||
ULONG Value;
|
||||
PCI_SLOT_NUMBER PciSlot;
|
||||
|
||||
if (!HalpPciDebuggingDevice[i].InUse)
|
||||
continue;
|
||||
|
||||
RtlInitEmptyUnicodeString(&KeyName, StringBuffer, sizeof(StringBuffer));
|
||||
RtlIntegerToUnicodeString(i, 10, &KeyName);
|
||||
Status = HalpOpenRegistryKey(&KeyHandle,
|
||||
Handle,
|
||||
&KeyName,
|
||||
KEY_ALL_ACCESS,
|
||||
TRUE);
|
||||
if (!NT_SUCCESS(Status))
|
||||
continue;
|
||||
|
||||
Value = HalpPciDebuggingDevice[i].BusNumber;
|
||||
RtlInitUnicodeString(&KeyName, L"Bus");
|
||||
ZwSetValueKey(KeyHandle,
|
||||
&KeyName,
|
||||
0,
|
||||
REG_DWORD,
|
||||
&Value,
|
||||
sizeof(Value));
|
||||
|
||||
PciSlot.u.AsULONG = 0;
|
||||
PciSlot.u.bits.DeviceNumber = HalpPciDebuggingDevice[i].DeviceNumber;
|
||||
PciSlot.u.bits.FunctionNumber = HalpPciDebuggingDevice[i].FunctionNumber;
|
||||
Value = PciSlot.u.AsULONG;
|
||||
RtlInitUnicodeString(&KeyName, L"Slot");
|
||||
ZwSetValueKey(KeyHandle,
|
||||
&KeyName,
|
||||
0,
|
||||
REG_DWORD,
|
||||
&Value,
|
||||
sizeof(Value));
|
||||
|
||||
ZwClose(KeyHandle);
|
||||
}
|
||||
|
||||
ZwClose(Handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief
|
||||
* Releases the PCI device MMIO mappings
|
||||
* previously allocated with HalpSetupPciDeviceForDebugging().
|
||||
*
|
||||
* This is used to release resources when a device specific initialization fails.
|
||||
*
|
||||
* @param[in,out] PciDevice
|
||||
* Pointer to the debug device descriptor, whose mappings are to be released.
|
||||
*
|
||||
* @return STATUS_SUCCESS.
|
||||
*/
|
||||
CODE_SEG("INIT")
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
HalpReleasePciDeviceForDebugging(
|
||||
_Inout_ PDEBUG_DEVICE_DESCRIPTOR PciDevice)
|
||||
{
|
||||
ULONG i;
|
||||
|
||||
DPRINT0("%s(%p) called\n", __FUNCTION__, PciDevice);
|
||||
|
||||
for (i = 0; i < MAXIMUM_DEBUG_BARS; ++i)
|
||||
{
|
||||
PDEBUG_DEVICE_ADDRESS DeviceAddress = &PciDevice->BaseAddress[i];
|
||||
|
||||
if (DeviceAddress->Type == CmResourceTypeMemory && DeviceAddress->Valid)
|
||||
{
|
||||
HalpUnmapVirtualAddress(DeviceAddress->TranslatedAddress,
|
||||
BYTES_TO_PAGES(DeviceAddress->Length));
|
||||
|
||||
DeviceAddress->Valid = FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
return STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief
|
||||
* Finds and fully initializes the PCI device
|
||||
* associated with the supplied debug device descriptor.
|
||||
*
|
||||
* @param[in] LoaderBlock
|
||||
* Pointer to the Loader parameter block. Can be NULL.
|
||||
*
|
||||
* @param[in,out] PciDevice
|
||||
* Pointer to the debug device descriptor.
|
||||
*
|
||||
* @return Status.
|
||||
*
|
||||
* This routine is used to match devices to debug device descriptors during
|
||||
* boot phase of the system. This function will search the first device that
|
||||
* matches the criteria given by the fields of the debug device descriptor.
|
||||
* A value of all 1's for the field will indicate that the function
|
||||
* should ignore that field in the search criteria.
|
||||
* The @c Length field of the debug memory requirements optionally specifies
|
||||
* library-determined number of bytes to be allocated for the device context.
|
||||
*
|
||||
* Example:
|
||||
* @code
|
||||
* RtlZeroMemory(&PciDevice, sizeof(DEBUG_DEVICE_DESCRIPTOR));
|
||||
* PciDevice.VendorID = 0xFFFF;
|
||||
* PciDevice.DeviceID = 0xFFFF;
|
||||
* PciDevice.Bus = 0xFFFFFFFF;
|
||||
* PciDevice.Slot = 0xFFFFFFFF;
|
||||
* PciDevice.BaseClass = PCI_CLASS_SERIAL_BUS_CTLR;
|
||||
* PciDevice.SubClass = PCI_SUBCLASS_SB_USB;
|
||||
* PciDevice.ProgIf = 0x30;
|
||||
* PciDevice.Memory.Length = sizeof(HW_EXTENSION);
|
||||
* @endcode
|
||||
*
|
||||
* @sa HalpReleasePciDeviceForDebugging
|
||||
*/
|
||||
CODE_SEG("INIT")
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
HalpSetupPciDeviceForDebugging(
|
||||
_In_opt_ PVOID LoaderBlock,
|
||||
_Inout_ PDEBUG_DEVICE_DESCRIPTOR PciDevice)
|
||||
{
|
||||
ULONG i;
|
||||
ULONG64 MaxAddress;
|
||||
PFN_NUMBER PageCount;
|
||||
PCI_SLOT_NUMBER PciSlot;
|
||||
PHYSICAL_ADDRESS PhysicalAddress;
|
||||
PPCI_TYPE1_CFG_CYCLE_BITS DebuggingDevice;
|
||||
|
||||
#if defined(EARLY_DEBUG)
|
||||
if (LoaderBlock)
|
||||
{
|
||||
/* Define your own function or use the trick with FreeLoader */
|
||||
DPRINT0 = ((PLOADER_PARAMETER_BLOCK)LoaderBlock)->u.I386.CommonDataArea;
|
||||
}
|
||||
#endif
|
||||
|
||||
DPRINT0("%s(%p, %p) called\n", __FUNCTION__, LoaderBlock, PciDevice);
|
||||
|
||||
if (!HalpFindMatchingDebuggingDevice(PciDevice))
|
||||
{
|
||||
DPRINT0("No device found matching given device descriptor!\n");
|
||||
return STATUS_DEVICE_DOES_NOT_EXIST;
|
||||
}
|
||||
|
||||
if (PciDevice->Initialized)
|
||||
return STATUS_SUCCESS;
|
||||
|
||||
PciSlot.u.AsULONG = PciDevice->Slot;
|
||||
|
||||
/* Check if the device is already present */
|
||||
for (i = 0; i < RTL_NUMBER_OF(HalpPciDebuggingDevice); ++i)
|
||||
{
|
||||
DebuggingDevice = &HalpPciDebuggingDevice[i];
|
||||
|
||||
if (DebuggingDevice->InUse &&
|
||||
DebuggingDevice->DeviceNumber == PciSlot.u.bits.DeviceNumber &&
|
||||
DebuggingDevice->FunctionNumber == PciSlot.u.bits.FunctionNumber &&
|
||||
DebuggingDevice->BusNumber == PciDevice->Bus)
|
||||
{
|
||||
DPRINT0("Device %p(0x%lx) is already in use!\n", PciDevice, PciDevice->Slot);
|
||||
return STATUS_UNSUCCESSFUL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Save the device location */
|
||||
for (i = 0; i < RTL_NUMBER_OF(HalpPciDebuggingDevice); ++i)
|
||||
{
|
||||
DebuggingDevice = &HalpPciDebuggingDevice[i];
|
||||
|
||||
if (!DebuggingDevice->InUse)
|
||||
{
|
||||
DebuggingDevice->DeviceNumber = PciSlot.u.bits.DeviceNumber;
|
||||
DebuggingDevice->FunctionNumber = PciSlot.u.bits.FunctionNumber;
|
||||
DebuggingDevice->BusNumber = PciDevice->Bus;
|
||||
DebuggingDevice->InUse = TRUE;
|
||||
|
||||
PciDevice->Initialized = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i == RTL_NUMBER_OF(HalpPciDebuggingDevice))
|
||||
{
|
||||
DPRINT0("Maximum device count reached!\n");
|
||||
return STATUS_UNSUCCESSFUL;
|
||||
}
|
||||
|
||||
if (!PciDevice->Memory.Length)
|
||||
return STATUS_SUCCESS;
|
||||
|
||||
if (!LoaderBlock)
|
||||
return STATUS_INVALID_PARAMETER_1;
|
||||
|
||||
if (!PciDevice->Memory.MaxEnd.QuadPart)
|
||||
{
|
||||
PciDevice->Memory.MaxEnd.QuadPart = (ULONG64)-1;
|
||||
}
|
||||
MaxAddress = min(PciDevice->Memory.MaxEnd.QuadPart, 0xFFFFFFFF);
|
||||
PageCount = BYTES_TO_PAGES(PciDevice->Memory.Length);
|
||||
|
||||
/* Allocate the device context */
|
||||
PhysicalAddress.QuadPart = HalpAllocPhysicalMemory(LoaderBlock,
|
||||
MaxAddress,
|
||||
PageCount,
|
||||
FALSE);
|
||||
PciDevice->Memory.Start = PhysicalAddress;
|
||||
if (!PhysicalAddress.QuadPart)
|
||||
{
|
||||
return STATUS_INSUFFICIENT_RESOURCES;
|
||||
}
|
||||
PciDevice->Memory.VirtualAddress = HalpMapPhysicalMemory64(PhysicalAddress, PageCount);
|
||||
|
||||
return STATUS_SUCCESS;
|
||||
}
|
||||
|
|
@ -244,21 +244,18 @@ typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
|
|||
} u;
|
||||
} PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
|
||||
|
||||
typedef struct _PCI_TYPE1_CFG_CYCLE_BITS
|
||||
typedef union _PCI_TYPE1_CFG_CYCLE_BITS
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
ULONG Reserved1:2;
|
||||
ULONG InUse:2;
|
||||
ULONG RegisterNumber:6;
|
||||
ULONG FunctionNumber:3;
|
||||
ULONG DeviceNumber:5;
|
||||
ULONG BusNumber:8;
|
||||
ULONG Reserved2:8;
|
||||
} bits;
|
||||
};
|
||||
ULONG AsULONG;
|
||||
} u;
|
||||
} PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
|
||||
|
||||
typedef struct _ARRAY
|
||||
|
|
@ -396,6 +393,24 @@ HalpAssignPCISlotResources(
|
|||
IN OUT PCM_RESOURCE_LIST *pAllocatedResources
|
||||
);
|
||||
|
||||
CODE_SEG("INIT")
|
||||
ULONG
|
||||
HalpPhase0GetPciDataByOffset(
|
||||
_In_ ULONG Bus,
|
||||
_In_ PCI_SLOT_NUMBER PciSlot,
|
||||
_Out_writes_bytes_all_(Length) PVOID Buffer,
|
||||
_In_ ULONG Offset,
|
||||
_In_ ULONG Length);
|
||||
|
||||
CODE_SEG("INIT")
|
||||
ULONG
|
||||
HalpPhase0SetPciDataByOffset(
|
||||
_In_ ULONG Bus,
|
||||
_In_ PCI_SLOT_NUMBER PciSlot,
|
||||
_In_reads_bytes_(Length) PVOID Buffer,
|
||||
_In_ ULONG Offset,
|
||||
_In_ ULONG Length);
|
||||
|
||||
/* NON-LEGACY */
|
||||
|
||||
ULONG
|
||||
|
|
|
|||
|
|
@ -17,8 +17,6 @@
|
|||
extern BOOLEAN HalpPciLockSettings;
|
||||
ULONG HalpBusType;
|
||||
|
||||
PCI_TYPE1_CFG_CYCLE_BITS HalpPciDebuggingDevice[2] = {{{{0}}}};
|
||||
|
||||
BOOLEAN HalpPCIConfigInitialized;
|
||||
ULONG HalpMinPciBus, HalpMaxPciBus;
|
||||
KSPIN_LOCK HalpPCIConfigLock;
|
||||
|
|
@ -302,21 +300,23 @@ HalpWritePCIConfig(IN PBUS_HANDLER BusHandler,
|
|||
}
|
||||
|
||||
#ifdef SARCH_XBOX
|
||||
static
|
||||
BOOLEAN
|
||||
NTAPI
|
||||
HalpXboxBlacklistedPCISlot(IN PBUS_HANDLER BusHandler,
|
||||
IN PCI_SLOT_NUMBER Slot)
|
||||
HalpXboxBlacklistedPCISlot(
|
||||
_In_ ULONG BusNumber,
|
||||
_In_ PCI_SLOT_NUMBER Slot)
|
||||
{
|
||||
/* Trying to get PCI config data from devices 0:0:1 and 0:0:2 will completely
|
||||
* hang the Xbox. Also, the device number doesn't seem to be decoded for the
|
||||
* video card, so it appears to be present on 1:0:0 - 1:31:0.
|
||||
* We hack around these problems by indicating "device not present" for devices
|
||||
* 0:0:1, 0:0:2, 1:1:0, 1:2:0, 1:3:0, ...., 1:31:0 */
|
||||
if ((BusHandler->BusNumber == 0 && Slot.u.bits.DeviceNumber == 0 &&
|
||||
if ((BusNumber == 0 && Slot.u.bits.DeviceNumber == 0 &&
|
||||
(Slot.u.bits.FunctionNumber == 1 || Slot.u.bits.FunctionNumber == 2)) ||
|
||||
(BusHandler->BusNumber == 1 && Slot.u.bits.DeviceNumber != 0))
|
||||
(BusNumber == 1 && Slot.u.bits.DeviceNumber != 0))
|
||||
{
|
||||
DPRINT("Blacklisted PCI slot (%d:%d:%d)\n", BusHandler->BusNumber, Slot.u.bits.DeviceNumber, Slot.u.bits.FunctionNumber);
|
||||
DPRINT("Blacklisted PCI slot (%d:%d:%d)\n",
|
||||
BusNumber, Slot.u.bits.DeviceNumber, Slot.u.bits.FunctionNumber);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
|
@ -339,7 +339,8 @@ HalpValidPCISlot(IN PBUS_HANDLER BusHandler,
|
|||
if (Slot.u.bits.DeviceNumber >= BusData->MaxDevice) return FALSE;
|
||||
|
||||
#ifdef SARCH_XBOX
|
||||
if (HalpXboxBlacklistedPCISlot(BusHandler, Slot)) return FALSE;
|
||||
if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
|
||||
return FALSE;
|
||||
#endif
|
||||
|
||||
/* Function 0 doesn't need checking */
|
||||
|
|
@ -362,6 +363,143 @@ HalpValidPCISlot(IN PBUS_HANDLER BusHandler,
|
|||
return TRUE;
|
||||
}
|
||||
|
||||
CODE_SEG("INIT")
|
||||
ULONG
|
||||
HalpPhase0GetPciDataByOffset(
|
||||
_In_ ULONG Bus,
|
||||
_In_ PCI_SLOT_NUMBER PciSlot,
|
||||
_Out_writes_bytes_all_(Length) PVOID Buffer,
|
||||
_In_ ULONG Offset,
|
||||
_In_ ULONG Length)
|
||||
{
|
||||
ULONG BytesLeft = Length;
|
||||
PUCHAR BufferPtr = Buffer;
|
||||
PCI_TYPE1_CFG_BITS PciCfg;
|
||||
|
||||
#ifdef SARCH_XBOX
|
||||
if (HalpXboxBlacklistedPCISlot(Bus, PciSlot))
|
||||
{
|
||||
RtlFillMemory(Buffer, Length, 0xFF);
|
||||
return Length;
|
||||
}
|
||||
#endif
|
||||
|
||||
PciCfg.u.AsULONG = 0;
|
||||
PciCfg.u.bits.BusNumber = Bus;
|
||||
PciCfg.u.bits.DeviceNumber = PciSlot.u.bits.DeviceNumber;
|
||||
PciCfg.u.bits.FunctionNumber = PciSlot.u.bits.FunctionNumber;
|
||||
PciCfg.u.bits.Enable = TRUE;
|
||||
|
||||
while (BytesLeft)
|
||||
{
|
||||
ULONG i;
|
||||
|
||||
PciCfg.u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
||||
WRITE_PORT_ULONG((PULONG)PCI_TYPE1_ADDRESS_PORT, PciCfg.u.AsULONG);
|
||||
|
||||
i = PCIDeref[Offset % sizeof(ULONG)][BytesLeft % sizeof(ULONG)];
|
||||
switch (i)
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
*(PULONG)BufferPtr = READ_PORT_ULONG((PULONG)PCI_TYPE1_DATA_PORT);
|
||||
|
||||
/* Number of bytes read */
|
||||
i = sizeof(ULONG);
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
{
|
||||
*BufferPtr = READ_PORT_UCHAR((PUCHAR)(PCI_TYPE1_DATA_PORT +
|
||||
Offset % sizeof(ULONG)));
|
||||
break;
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
*(PUSHORT)BufferPtr = READ_PORT_USHORT((PUSHORT)(PCI_TYPE1_DATA_PORT +
|
||||
Offset % sizeof(ULONG)));
|
||||
break;
|
||||
}
|
||||
|
||||
DEFAULT_UNREACHABLE;
|
||||
}
|
||||
|
||||
Offset += i;
|
||||
BufferPtr += i;
|
||||
BytesLeft -= i;
|
||||
}
|
||||
|
||||
return Length;
|
||||
}
|
||||
|
||||
CODE_SEG("INIT")
|
||||
ULONG
|
||||
HalpPhase0SetPciDataByOffset(
|
||||
_In_ ULONG Bus,
|
||||
_In_ PCI_SLOT_NUMBER PciSlot,
|
||||
_In_reads_bytes_(Length) PVOID Buffer,
|
||||
_In_ ULONG Offset,
|
||||
_In_ ULONG Length)
|
||||
{
|
||||
ULONG BytesLeft = Length;
|
||||
PUCHAR BufferPtr = Buffer;
|
||||
PCI_TYPE1_CFG_BITS PciCfg;
|
||||
|
||||
#ifdef SARCH_XBOX
|
||||
if (HalpXboxBlacklistedPCISlot(Bus, PciSlot))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
PciCfg.u.AsULONG = 0;
|
||||
PciCfg.u.bits.BusNumber = Bus;
|
||||
PciCfg.u.bits.DeviceNumber = PciSlot.u.bits.DeviceNumber;
|
||||
PciCfg.u.bits.FunctionNumber = PciSlot.u.bits.FunctionNumber;
|
||||
PciCfg.u.bits.Enable = TRUE;
|
||||
|
||||
while (BytesLeft)
|
||||
{
|
||||
ULONG i;
|
||||
|
||||
PciCfg.u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
||||
WRITE_PORT_ULONG((PULONG)PCI_TYPE1_ADDRESS_PORT, PciCfg.u.AsULONG);
|
||||
|
||||
i = PCIDeref[Offset % sizeof(ULONG)][BytesLeft % sizeof(ULONG)];
|
||||
switch (i)
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
WRITE_PORT_ULONG((PULONG)PCI_TYPE1_DATA_PORT, *(PULONG)BufferPtr);
|
||||
|
||||
/* Number of bytes written */
|
||||
i = sizeof(ULONG);
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
{
|
||||
WRITE_PORT_UCHAR((PUCHAR)(PCI_TYPE1_DATA_PORT + Offset % sizeof(ULONG)),
|
||||
*BufferPtr);
|
||||
break;
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
WRITE_PORT_USHORT((PUSHORT)(PCI_TYPE1_DATA_PORT + Offset % sizeof(ULONG)),
|
||||
*(PUSHORT)BufferPtr);
|
||||
break;
|
||||
}
|
||||
|
||||
DEFAULT_UNREACHABLE;
|
||||
}
|
||||
|
||||
Offset += i;
|
||||
BufferPtr += i;
|
||||
BytesLeft -= i;
|
||||
}
|
||||
|
||||
return Length;
|
||||
}
|
||||
|
||||
/* HAL PCI CALLBACKS *********************************************************/
|
||||
|
||||
ULONG
|
||||
|
|
@ -380,14 +518,10 @@ HalpGetPCIData(IN PBUS_HANDLER BusHandler,
|
|||
|
||||
Slot.u.AsULONG = SlotNumber;
|
||||
#ifdef SARCH_XBOX
|
||||
if (HalpXboxBlacklistedPCISlot(BusHandler, Slot))
|
||||
if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
|
||||
{
|
||||
if (Offset == 0 && Length >= sizeof(USHORT))
|
||||
{
|
||||
*(PUSHORT)Buffer = PCI_INVALID_VENDORID;
|
||||
return sizeof(USHORT);
|
||||
}
|
||||
return 0;
|
||||
RtlFillMemory(Buffer, Length, 0xFF);
|
||||
return Length;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -464,7 +598,8 @@ HalpSetPCIData(IN PBUS_HANDLER BusHandler,
|
|||
|
||||
Slot.u.AsULONG = SlotNumber;
|
||||
#ifdef SARCH_XBOX
|
||||
if (HalpXboxBlacklistedPCISlot(BusHandler, Slot)) return 0;
|
||||
if (HalpXboxBlacklistedPCISlot(BusHandler->BusNumber, Slot))
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
/* Normalize the length */
|
||||
|
|
@ -607,53 +742,6 @@ HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler,
|
|||
(*Range)->Limit = PciData.u.type0.InterruptLine;
|
||||
return STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
CODE_SEG("INIT")
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
HalpSetupPciDeviceForDebugging(IN PVOID LoaderBlock,
|
||||
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
|
||||
{
|
||||
DPRINT1("Unimplemented!\n");
|
||||
return STATUS_NOT_IMPLEMENTED;
|
||||
}
|
||||
|
||||
CODE_SEG("INIT")
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
HalpReleasePciDeviceForDebugging(IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
|
||||
{
|
||||
DPRINT1("Unimplemented!\n");
|
||||
return STATUS_NOT_IMPLEMENTED;
|
||||
}
|
||||
|
||||
CODE_SEG("INIT")
|
||||
VOID
|
||||
NTAPI
|
||||
HalpRegisterPciDebuggingDeviceInfo(VOID)
|
||||
{
|
||||
BOOLEAN Found = FALSE;
|
||||
ULONG i;
|
||||
PAGED_CODE();
|
||||
|
||||
/* Loop PCI debugging devices */
|
||||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
/* Reserved bit is set if we found one */
|
||||
if (HalpPciDebuggingDevice[i].u.bits.Reserved1)
|
||||
{
|
||||
Found = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Bail out if there aren't any */
|
||||
if (!Found) return;
|
||||
|
||||
/* FIXME: TODO */
|
||||
UNIMPLEMENTED_DBGBREAK("You have implemented the KD routines for searching PCI debugger"
|
||||
"devices, but you have forgotten to implement this routine\n");
|
||||
}
|
||||
#endif // _MINIHAL_
|
||||
|
||||
static ULONG NTAPI
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ list(APPEND HAL_PC98_SOURCE
|
|||
generic/dma.c
|
||||
generic/drive.c
|
||||
generic/halinit.c
|
||||
generic/kdpci.c
|
||||
generic/memory.c
|
||||
generic/misc.c
|
||||
generic/nmi.c
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ list(APPEND HAL_XBOX_SOURCE
|
|||
generic/dma.c
|
||||
generic/drive.c
|
||||
generic/halinit.c
|
||||
generic/kdpci.c
|
||||
generic/memory.c
|
||||
generic/misc.c
|
||||
generic/nmi.c
|
||||
|
|
|
|||
Loading…
Reference in a new issue