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[NTVDM:SVGA]

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Halfplement (or perhaps hackplement) SVGA packed pixel addressing.


svn path=/trunk/; revision=72518
This commit is contained in:
Aleksandar Andrejevic 2016-08-31 05:38:56 +00:00
parent 17a315285a
commit 724065020c
2 changed files with 163 additions and 108 deletions
Download patch file Download diff file Expand all files Collapse all files

72
reactos/subsystems/mvdm/ntvdm/hardware/video/svga.c
View file

@ -317,7 +317,12 @@ static inline DWORD VgaGetVideoBaseAddress(VOID)
static inline DWORD VgaGetAddressSize(VOID)
{
if (VgaCrtcRegisters[VGA_CRTC_UNDERLINE_REG] & VGA_CRTC_UNDERLINE_DWORD)
if (VgaSeqRegisters[SVGA_SEQ_EXT_MODE_REG] & SVGA_SEQ_EXT_MODE_HIGH_RES)
{
/* Packed pixel addressing */
return 1;
}
else if (VgaCrtcRegisters[VGA_CRTC_UNDERLINE_REG] & VGA_CRTC_UNDERLINE_DWORD)
{
/* Double-word addressing */
return 4; // sizeof(DWORD)
@ -735,7 +740,8 @@ static VOID VgaUpdateFramebuffer(VOID)
DWORD Address = StartAddressLatch;
BYTE BytePanning = (VgaCrtcRegisters[VGA_CRTC_PRESET_ROW_SCAN_REG] >> 5) & 3;
WORD LineCompare = VgaCrtcRegisters[VGA_CRTC_LINE_COMPARE_REG]
| ((VgaCrtcRegisters[VGA_CRTC_OVERFLOW_REG] & VGA_CRTC_OVERFLOW_LC8) << 4);
| ((VgaCrtcRegisters[VGA_CRTC_OVERFLOW_REG] & VGA_CRTC_OVERFLOW_LC8) << 4)
| ((VgaCrtcRegisters[VGA_CRTC_MAX_SCAN_LINE_REG] & VGA_CRTC_MAXSCANLINE_LC9) << 3);
BYTE PixelShift = VgaAcRegisters[VGA_AC_HORZ_PANNING_REG] & 0x0F;
/*
@ -815,6 +821,15 @@ static VOID VgaUpdateFramebuffer(VOID)
X = j + ((PixelShift < 8) ? PixelShift : -1);
}
if (VgaSeqRegisters[SVGA_SEQ_EXT_MODE_REG] & SVGA_SEQ_EXT_MODE_HIGH_RES)
{
// TODO: Check for high color modes
/* 256 color mode */
PixelData = VgaMemory[Address + X];
}
else
{
/* Check the shifting mode */
if (VgaGcRegisters[VGA_GC_MODE_REG] & VGA_GC_MODE_SHIFT256)
{
@ -911,6 +926,7 @@ static VOID VgaUpdateFramebuffer(VOID)
}
}
}
}
if (!(VgaAcRegisters[VGA_AC_CONTROL_REG] & VGA_AC_CONTROL_8BIT))
{
@ -1687,6 +1703,7 @@ static VOID FASTCALL VgaHorizontalRetrace(ULONGLONG ElapsedTime)
/* Save the scanline size */
ScanlineSizeLatch = ((DWORD)VgaCrtcRegisters[VGA_CRTC_OFFSET_REG]
+ (((DWORD)VgaCrtcRegisters[SVGA_CRTC_EXT_DISPLAY_REG] & SVGA_CRTC_EXT_OFFSET_BIT8) << 4)) * 2;
if (VgaSeqRegisters[SVGA_SEQ_EXT_MODE_REG] & SVGA_SEQ_EXT_MODE_HIGH_RES) ScanlineSizeLatch <<= 2;
/* Save the starting address */
StartAddressLatch = MAKEWORD(VgaCrtcRegisters[VGA_CRTC_START_ADDR_LOW_REG],
@ -1768,6 +1785,7 @@ VOID VgaRefreshDisplay(VOID)
/* Save the scanline size */
ScanlineSizeLatch = ((DWORD)VgaCrtcRegisters[VGA_CRTC_OFFSET_REG]
+ (((DWORD)VgaCrtcRegisters[SVGA_CRTC_EXT_DISPLAY_REG] & SVGA_CRTC_EXT_OFFSET_BIT8) << 4)) * 2;
if (VgaSeqRegisters[SVGA_SEQ_EXT_MODE_REG] & SVGA_SEQ_EXT_MODE_HIGH_RES) ScanlineSizeLatch <<= 2;
/* Save the starting address */
StartAddressLatch = MAKEWORD(VgaCrtcRegisters[VGA_CRTC_START_ADDR_LOW_REG],
@ -1797,12 +1815,11 @@ VOID FASTCALL VgaReadMemory(ULONG Address, PVOID Buffer, ULONG Size)
{
VideoAddress = VgaTranslateAddress(Address);
#if 0
/* Packed pixel mode - not used yet */
/* Check for packed pixel, chain-4, and odd-even mode */
if (VgaSeqRegisters[SVGA_SEQ_EXT_MODE_REG] & SVGA_SEQ_EXT_MODE_HIGH_RES)
{
/* Just copy from the video memory */
PVOID VideoMemory = &VgaMemory[VideoAddress * VGA_NUM_BANKS + (Address & 3)];
PVOID VideoMemory = &VgaMemory[VideoAddress + (Address & 3)];
switch (Size)
{
@ -1830,10 +1847,7 @@ VOID FASTCALL VgaReadMemory(ULONG Address, PVOID Buffer, ULONG Size)
#endif
}
}
#endif
/* Check for chain-4 and odd-even mode */
if (VgaSeqRegisters[VGA_SEQ_MEM_REG] & VGA_SEQ_MEM_C4)
else if (VgaSeqRegisters[VGA_SEQ_MEM_REG] & VGA_SEQ_MEM_C4)
{
i = 0;
@ -1979,6 +1993,8 @@ BOOLEAN FASTCALL VgaWriteMemory(ULONG Address, PVOID Buffer, ULONG Size)
/* Also ignore if write access to all planes is disabled */
if ((VgaSeqRegisters[VGA_SEQ_MASK_REG] & 0x0F) == 0x00) return TRUE;
if (!(VgaSeqRegisters[SVGA_SEQ_EXT_MODE_REG] & SVGA_SEQ_EXT_MODE_HIGH_RES))
{
/* Loop through each byte */
for (i = 0; i < Size; i++)
{
@ -2013,6 +2029,44 @@ BOOLEAN FASTCALL VgaWriteMemory(ULONG Address, PVOID Buffer, ULONG Size)
VgaMemory[VideoAddress * VGA_NUM_BANKS + j] = VgaTranslateByteForWriting(BufPtr[i], j);
}
}
}
else
{
PVOID VideoMemory;
// TODO: Apply the page write mask!
// TODO: Check whether the write mode stuff applies to packed-pixel modes
/* Just copy to the video memory */
VideoAddress = VgaTranslateAddress(Address);
VideoMemory = &VgaMemory[VideoAddress + (Address & 3)];
switch (Size)
{
case sizeof(UCHAR):
*(PUCHAR)VideoMemory = *(PUCHAR)Buffer;
return TRUE;
case sizeof(USHORT):
*(PUSHORT)VideoMemory = *(PUSHORT)Buffer;
return TRUE;
case sizeof(ULONG):
*(PULONG)VideoMemory = *(PULONG)Buffer;
return TRUE;
case sizeof(ULONGLONG):
*(PULONGLONG)VideoMemory = *(PULONGLONG)Buffer;
return TRUE;
default:
#if defined(__GNUC__)
__builtin_memcpy(VideoMemory, Buffer, Size);
#else
RtlCopyMemory(VideoMemory, Buffer, Size);
#endif
}
}
return TRUE;
}

1
reactos/subsystems/mvdm/ntvdm/hardware/video/svga.h
View file

@ -182,6 +182,7 @@ enum
/* CRTC max scanline register bits */
#define VGA_CRTC_MAXSCANLINE_DOUBLE (1 << 7)
#define VGA_CRTC_MAXSCANLINE_LC9 (1 << 6)
/* CRTC mode control register bits */
#define VGA_CRTC_MODE_CONTROL_WRAP (1 << 5)