mirror of
https://github.com/reactos/reactos.git
synced 2024-07-06 20:55:16 +00:00
Say hello to 4KB pages! Removed bring-up 1MB page hacks all over FreeLDR, and setup the kernel pages the same way the x86 build does it -- 6MB from 0x80800000 to 0x80DFFFFF for kernel and drivers.
We still identity map the bottom 0MB of memory with a 1MB page, since this makes the most sense. We now map the low 8MB of memory to 0x80000000-0x807FFFFF, also with 4KB pages. This area will be discardable after early-init, and contains the early boot structures allocated by FreeLDR. The Loader Parameter Block and its Extension are now dynamically allocated, instead of being static inside FreeLDR. Fixed some bugs in the ARM_PTE structure. svn path=/trunk/; revision=32350
This commit is contained in:
ReactOS Portable Systems Group
parent
3f38f62b4c
commit
70fbfefbe5
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@ -69,4 +69,24 @@ BootStackEnd:
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.section pagedata
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.global ArmTranslationTable
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ArmTranslationTable:
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.space 0x4000
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.space 0x4000 // 0x00000000->0xFFFFFFFF
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.global BootTranslationTable
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BootTranslationTable:
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.space 0x0400 // 0x00000000->0x800FFFFF
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.space 0x0400 // 0x00100000->0x801FFFFF
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.space 0x0400 // 0x00200000->0x802FFFFF
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.space 0x0400 // 0x00300000->0x803FFFFF
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.space 0x0400 // 0x00400000->0x804FFFFF
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.space 0x0400 // 0x00500000->0x805FFFFF
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.space 0x0400 // 0x00600000->0x806FFFFF
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.space 0x0400 // 0x00700000->0x807FFFFF
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.global KernelTranslationTable
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KernelTranslationTable:
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.space 0x0400 // 0x00800000->0x808FFFFF
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.space 0x0400 // 0x00900000->0x809FFFFF
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.space 0x0400 // 0x00A00000->0x80AFFFFF
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.space 0x0400 // 0x00B00000->0x80BFFFFF
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.space 0x0400 // 0x00C00000->0x80CFFFFF
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.space 0x0400 // 0x00D00000->0x80DFFFFF
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@ -16,15 +16,17 @@
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/* GLOBALS ********************************************************************/
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ULONG PageDirectoryStart, PageDirectoryEnd;
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LOADER_PARAMETER_BLOCK ArmLoaderBlock;
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PLOADER_PARAMETER_BLOCK ArmLoaderBlock;
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CHAR ArmCommandLine[256];
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CHAR ArmArcBootPath[64];
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CHAR ArmArcHalPath[64];
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CHAR ArmNtHalPath[64];
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CHAR ArmNtBootPath[64];
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LOADER_PARAMETER_EXTENSION ArmExtension;
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PLOADER_PARAMETER_EXTENSION ArmExtension;
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extern ARM_TRANSLATION_TABLE ArmTranslationTable;
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extern ARM_COARSE_PAGE_TABLE BootTranslationTable, KernelTranslationTable;
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extern ROS_KERNEL_ENTRY_POINT KernelEntryPoint;
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extern ULONG_PTR KernelBase;
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ULONG SizeBits[] =
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{
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@ -65,21 +67,21 @@ ArmSetupPageDirectory(VOID)
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ARM_TTB_REGISTER TtbRegister;
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ARM_DOMAIN_REGISTER DomainRegister;
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ARM_PTE Pte;
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ULONG i;
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PARM_TRANSLATION_TABLE TranslationTable;
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ULONG i, j;
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PARM_TRANSLATION_TABLE MasterTable;
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PARM_COARSE_PAGE_TABLE BootTable, KernelTable;
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//
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// Allocate translation table buffer.
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// During bootstrap, this will be a simple L1 (Master) Page Table with
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// Section entries for KSEG0 and the first MB of RAM.
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// Get the PDEs that we will use
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//
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TranslationTable = &ArmTranslationTable;
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if (!TranslationTable) return;
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MasterTable = &ArmTranslationTable;
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BootTable = &BootTranslationTable;
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KernelTable = &KernelTranslationTable;
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//
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// Set it as the TTB
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// Set the master L1 PDE as the TTB
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//
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TtbRegister.AsUlong = (ULONG)TranslationTable;
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TtbRegister.AsUlong = (ULONG)MasterTable;
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ASSERT(TtbRegister.Reserved == 0);
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KeArmTranslationTableRegisterSet(TtbRegister);
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@ -93,10 +95,10 @@ ArmSetupPageDirectory(VOID)
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//
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// Set Fault PTEs everywhere
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//
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RtlZeroMemory(TranslationTable, 4096 * sizeof(ARM_PTE));
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RtlZeroMemory(MasterTable, sizeof(ARM_TRANSLATION_TABLE));
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//
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// Build the template PTE
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// Identity map the first MB of memory
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//
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Pte.L1.Section.Type = SectionPte;
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Pte.L1.Section.Buffered = FALSE;
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@ -106,32 +108,125 @@ ArmSetupPageDirectory(VOID)
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Pte.L1.Section.Access = SupervisorAccess;
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Pte.L1.Section.BaseAddress = 0;
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Pte.L1.Section.Ignored = Pte.L1.Section.Ignored1 = 0;
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//
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// Map KSEG0 (0x80000000 - 0xA0000000) to 0x00000000 - 0x20000000
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// In this way, the KERNEL_PHYS_ADDR (0x800000) becomes 0x80800000
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// which is the entrypoint, just like on x86.
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//
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for (i = (KSEG0_BASE >> TTB_SHIFT); i < ((KSEG0_BASE + 0x20000000) >> TTB_SHIFT); i++)
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{
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//
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// Write PTE and update the base address (next MB) for the next one
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//
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TranslationTable->Pte[i] = Pte;
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Pte.L1.Section.BaseAddress++;
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}
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//
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// Identity map the first MB of memory as well
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//
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Pte.L1.Section.BaseAddress = 0;
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TranslationTable->Pte[0] = Pte;
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MasterTable->Pte[0] = Pte;
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//
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// Map the page in MMIO space that contains the serial port into virtual memory
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//
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Pte.L1.Section.BaseAddress = ArmBoardBlock->UartRegisterBase >> TTB_SHIFT;
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TranslationTable->Pte[UART_VIRTUAL >> TTB_SHIFT] = Pte;
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Pte.L1.Section.BaseAddress = ArmBoardBlock->UartRegisterBase >> PDE_SHIFT;
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MasterTable->Pte[UART_VIRTUAL >> PDE_SHIFT] = Pte;
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//
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// Create template PTE for the coarse page tables which map the first 8MB
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//
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Pte.L1.Coarse.Type = CoarsePte;
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Pte.L1.Coarse.Domain = Domain0;
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Pte.L1.Coarse.Reserved = 1; // ARM926EJ-S manual recommends setting to 1
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Pte.L1.Coarse.BaseAddress = (ULONG)BootTable >> CPT_SHIFT;
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Pte.L1.Coarse.Ignored = Pte.L1.Coarse.Ignored1 = 0;
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//
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// Map 0x00000000 - 0x007FFFFF to 0x80000000 - 0x807FFFFF.
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// This is where the freeldr boot structures are located, and we need them.
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//
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for (i = (KSEG0_BASE >> PDE_SHIFT); i < ((KSEG0_BASE + 0x800000) >> PDE_SHIFT); i++)
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{
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//
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// Write PTE and update the base address (next MB) for the next one
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//
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MasterTable->Pte[i] = Pte;
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Pte.L1.Coarse.BaseAddress++;
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}
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//
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// Now create the template PTE for the coarse page tables for the next 6MB
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//
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Pte.L1.Coarse.BaseAddress = (ULONG)KernelTable >> CPT_SHIFT;
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TuiPrintf("Coarse Table at: %x\n", KernelTable);
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TuiPrintf("Coarse Table at: %x\n", Pte.L1.Coarse.BaseAddress);
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//
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// Map 0x00800000 - 0x00DFFFFF to 0x80800000 - 0x80DFFFFF
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// In this way, the KERNEL_PHYS_ADDR (0x800000) becomes 0x80800000
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// which is the kernel virtual base address, just like on x86.
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//
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ASSERT(KernelBase == 0x80800000);
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for (i = (KernelBase >> PDE_SHIFT); i < ((KernelBase + 0x600000) >> PDE_SHIFT); i++)
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{
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//
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// Write PTE and update the base address (next MB) for the next one
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//
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MasterTable->Pte[i] = Pte;
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Pte.L1.Coarse.BaseAddress++;
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}
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//
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// Now build the template PTE for the pages mapping the first 8MB
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//
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Pte.L2.Small.Type = SmallPte;
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Pte.L2.Small.Buffered = Pte.L2.Small.Cached = 0;
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Pte.L2.Small.Access0 =
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Pte.L2.Small.Access1 =
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Pte.L2.Small.Access2 =
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Pte.L2.Small.Access3 = SupervisorAccess;
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Pte.L2.Small.BaseAddress = 0;
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//
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// Loop each boot coarse page table (i).
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// Each PDE describes 1MB. We're mapping an area of 8MB, so 8 times.
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//
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for (i = 0; i < 8; i++)
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{
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//
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// Loop and set each the PTE (j).
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// Each PTE describes 4KB. We're mapping an area of 1MB, so 256 times.
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//
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for (j = 0; j < (PDE_SIZE / PAGE_SIZE); j++)
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{
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//
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// Write PTE and update the base address (next MB) for the next one
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//
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BootTable->Pte[j] = Pte;
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Pte.L2.Small.BaseAddress++;
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}
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//
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// Next iteration
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//
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BootTable++;
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}
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//
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// Now create the template PTE for the pages mapping the next 6MB
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//
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Pte.L2.Small.BaseAddress = (ULONG)KERNEL_BASE_PHYS >> PTE_SHIFT;
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TuiPrintf("First Kernel PFN at: %x\n", Pte.L2.Small.BaseAddress);
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//
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// Loop each kernel coarse page table (i).
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// Each PDE describes 1MB. We're mapping an area of 6MB, so 6 times.
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//
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for (i = 0; i < 6; i++)
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{
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//
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// Loop and set each the PTE (j).
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// Each PTE describes 4KB. We're mapping an area of 1MB, so 256 times.
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//
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for (j = 0; j < (PDE_SIZE / PAGE_SIZE); j++)
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{
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//
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// Write PTE and update the base address (next MB) for the next one
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//
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KernelTable->Pte[j] = Pte;
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Pte.L2.Small.BaseAddress++;
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}
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//
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// Next iteration
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//
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KernelTable++;
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TuiPrintf("Coarse Table at: %x\n", KernelTable);
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}
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}
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VOID
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@ -153,13 +248,13 @@ ArmSetupPagingAndJump(IN ULONG Magic)
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//
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ArmBoardBlock->UartRegisterBase = UART_VIRTUAL |
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(ArmBoardBlock->UartRegisterBase &
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((1 << TTB_SHIFT) - 1));
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((1 << PDE_SHIFT) - 1));
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TuiPrintf("Mapped serial port to 0x%x\n", ArmBoardBlock->UartRegisterBase);
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//
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// Jump to Kernel
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//
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(*KernelEntryPoint)(Magic, (PVOID)&ArmLoaderBlock);
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(*KernelEntryPoint)(Magic, (PVOID)ArmLoaderBlock);
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}
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VOID
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@ -169,18 +264,28 @@ ArmPrepareForReactOS(IN BOOLEAN Setup)
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PVOID Base;
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PCHAR BootPath, HalPath;
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//
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// Allocate the loader block and extension
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//
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ArmLoaderBlock = MmAllocateMemoryWithType(sizeof(LOADER_PARAMETER_BLOCK),
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LoaderOsloaderHeap);
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if (!ArmLoaderBlock) return;
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ArmExtension = MmAllocateMemoryWithType(sizeof(LOADER_PARAMETER_EXTENSION),
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LoaderOsloaderHeap);
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if (!ArmExtension) return;
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//
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// Initialize the loader block
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//
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InitializeListHead(&ArmLoaderBlock.BootDriverListHead);
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InitializeListHead(&ArmLoaderBlock.LoadOrderListHead);
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InitializeListHead(&ArmLoaderBlock.MemoryDescriptorListHead);
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InitializeListHead(&ArmLoaderBlock->BootDriverListHead);
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InitializeListHead(&ArmLoaderBlock->LoadOrderListHead);
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InitializeListHead(&ArmLoaderBlock->MemoryDescriptorListHead);
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//
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// Setup the extension and setup block
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//
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ArmLoaderBlock.Extension = &ArmExtension;
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ArmLoaderBlock.SetupLdrBlock = NULL;
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ArmLoaderBlock->Extension = ArmExtension;
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ArmLoaderBlock->SetupLdrBlock = NULL;
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//
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// TODO: Setup memory descriptors
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@ -209,7 +314,7 @@ ArmPrepareForReactOS(IN BOOLEAN Setup)
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//
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// Make a copy of the command line
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//
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ArmLoaderBlock.LoadOptions = ArmCommandLine;
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ArmLoaderBlock->LoadOptions = ArmCommandLine;
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strcpy(ArmCommandLine, reactos_kernel_cmdline);
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//
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@ -222,7 +327,7 @@ ArmPrepareForReactOS(IN BOOLEAN Setup)
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// Set the ARC Boot Path
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//
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strncpy(ArmArcBootPath, ArmCommandLine, 63);
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ArmLoaderBlock.ArcBootDeviceName = ArmArcBootPath;
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ArmLoaderBlock->ArcBootDeviceName = ArmArcBootPath;
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//
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// The rest of the string is the NT path
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@ -232,77 +337,77 @@ ArmPrepareForReactOS(IN BOOLEAN Setup)
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ArmNtBootPath[0] = '\\';
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strncat(ArmNtBootPath, BootPath + 1, 63);
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strcat(ArmNtBootPath,"\\");
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ArmLoaderBlock.NtBootPathName = ArmNtBootPath;
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ArmLoaderBlock->NtBootPathName = ArmNtBootPath;
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//
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// Set the HAL paths
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//
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strncpy(ArmArcHalPath, ArmArcBootPath, 63);
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ArmLoaderBlock.ArcHalDeviceName = ArmArcHalPath;
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ArmLoaderBlock->ArcHalDeviceName = ArmArcHalPath;
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strcpy(ArmNtHalPath, "\\");
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ArmLoaderBlock.NtHalPathName = ArmNtHalPath;
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ArmLoaderBlock->NtHalPathName = ArmNtHalPath;
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/* Use this new command line */
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strncpy(ArmLoaderBlock.LoadOptions, HalPath + 2, 255);
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strncpy(ArmLoaderBlock->LoadOptions, HalPath + 2, 255);
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/* Parse it and change every slash to a space */
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BootPath = ArmLoaderBlock.LoadOptions;
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BootPath = ArmLoaderBlock->LoadOptions;
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do {if (*BootPath == '/') *BootPath = ' ';} while (*BootPath++);
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//
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// Setup cache information
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//
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CacheReg = KeArmCacheRegisterGet();
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ArmLoaderBlock.u.Arm.FirstLevelDcacheSize = SizeBits[CacheReg.DSize];
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ArmLoaderBlock.u.Arm.FirstLevelDcacheFillSize = LenBits[CacheReg.DLength];
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ArmLoaderBlock.u.Arm.FirstLevelDcacheFillSize <<= 2;
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ArmLoaderBlock.u.Arm.FirstLevelIcacheSize = SizeBits[CacheReg.ISize];
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ArmLoaderBlock.u.Arm.FirstLevelIcacheFillSize = LenBits[CacheReg.ILength];
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ArmLoaderBlock.u.Arm.FirstLevelIcacheFillSize <<= 2;
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ArmLoaderBlock.u.Arm.SecondLevelDcacheSize =
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ArmLoaderBlock.u.Arm.SecondLevelDcacheFillSize =
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ArmLoaderBlock.u.Arm.SecondLevelIcacheSize =
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ArmLoaderBlock.u.Arm.SecondLevelIcacheFillSize = 0;
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ArmLoaderBlock->u.Arm.FirstLevelDcacheSize = SizeBits[CacheReg.DSize];
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ArmLoaderBlock->u.Arm.FirstLevelDcacheFillSize = LenBits[CacheReg.DLength];
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ArmLoaderBlock->u.Arm.FirstLevelDcacheFillSize <<= 2;
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ArmLoaderBlock->u.Arm.FirstLevelIcacheSize = SizeBits[CacheReg.ISize];
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ArmLoaderBlock->u.Arm.FirstLevelIcacheFillSize = LenBits[CacheReg.ILength];
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ArmLoaderBlock->u.Arm.FirstLevelIcacheFillSize <<= 2;
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ArmLoaderBlock->u.Arm.SecondLevelDcacheSize =
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ArmLoaderBlock->u.Arm.SecondLevelDcacheFillSize =
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ArmLoaderBlock->u.Arm.SecondLevelIcacheSize =
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ArmLoaderBlock->u.Arm.SecondLevelIcacheFillSize = 0;
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//
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// Allocate the Interrupt stack
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//
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Base = MmAllocateMemoryWithType(KERNEL_STACK_SIZE, LoaderStartupDpcStack);
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ArmLoaderBlock.u.Arm.InterruptStack = KSEG0_BASE | (ULONG)Base;
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ArmLoaderBlock->u.Arm.InterruptStack = KSEG0_BASE | (ULONG)Base;
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//
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// Allocate the Kernel Boot stack
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//
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Base = MmAllocateMemoryWithType(KERNEL_STACK_SIZE, LoaderStartupKernelStack);
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ArmLoaderBlock.KernelStack = KSEG0_BASE | (ULONG)Base;
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ArmLoaderBlock->KernelStack = KSEG0_BASE | (ULONG)Base;
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//
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// Allocate the Abort stack
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//
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Base = MmAllocateMemoryWithType(KERNEL_STACK_SIZE, LoaderStartupPanicStack);
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ArmLoaderBlock.u.Arm.PanicStack = KSEG0_BASE | (ULONG)Base;
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ArmLoaderBlock->u.Arm.PanicStack = KSEG0_BASE | (ULONG)Base;
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//
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// Allocate the PCR page -- align it to 1MB (we only need 4KB)
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//
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Base = MmAllocateMemoryWithType(2 * 1024 * 1024, LoaderStartupPcrPage);
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Base = (PVOID)ROUND_UP(Base, 1 * 1024 * 1024);
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ArmLoaderBlock.u.Arm.PcrPage = (ULONG)Base >> TTB_SHIFT;
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ArmLoaderBlock->u.Arm.PcrPage = (ULONG)Base >> PDE_SHIFT;
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//
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// Allocate PDR pages -- align them to 1MB (we only need 3xKB)
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//
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Base = MmAllocateMemoryWithType(4 * 1024 * 1024, LoaderStartupPdrPage);
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Base = (PVOID)ROUND_UP(Base, 1 * 1024 * 1024);
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ArmLoaderBlock.u.Arm.PdrPage = (ULONG)Base >> TTB_SHIFT;
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ArmLoaderBlock->u.Arm.PdrPage = (ULONG)Base >> PDE_SHIFT;
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//
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// Set initial PRCB, Thread and Process on the last PDR page
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//
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Base = (PVOID)((ULONG)Base + 2 * 1024 * 1024);
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ArmLoaderBlock.Prcb = KSEG0_BASE | (ULONG)Base;
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ArmLoaderBlock.Process = ArmLoaderBlock.Prcb + sizeof(KPRCB);
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ArmLoaderBlock.Thread = ArmLoaderBlock.Process + sizeof(EPROCESS);
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ArmLoaderBlock->Prcb = KSEG0_BASE | (ULONG)Base;
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ArmLoaderBlock->Process = ArmLoaderBlock->Prcb + sizeof(KPRCB);
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ArmLoaderBlock->Thread = ArmLoaderBlock->Process + sizeof(EPROCESS);
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}
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VOID
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@ -5,7 +5,23 @@
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#pragma GCC system_header
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#endif
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#define TTB_SHIFT 20
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//
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// Number of bits corresponding to the area that a PDE entry represents (1MB)
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//
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#define PDE_SHIFT 20
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||||
#define PDE_SIZE (1 << PDE_SHIFT)
|
||||
|
||||
//
|
||||
// Number of bits corresponding to the area that a coarse page table entry represents (4KB)
|
||||
//
|
||||
#define PTE_SHIFT 12
|
||||
#define PAGE_SIZE (1 << PTE_SHIFT)
|
||||
|
||||
//
|
||||
// Number of bits corresponding to the area that a coarse page table occupies (1KB)
|
||||
//
|
||||
#define CPT_SHIFT 10
|
||||
#define CPT_SIZE (1 << CPT_SHIFT)
|
||||
|
||||
typedef union _ARM_PTE
|
||||
{
|
||||
|
|
@ -19,9 +35,10 @@ typedef union _ARM_PTE
|
|||
struct
|
||||
{
|
||||
ULONG Type:2;
|
||||
ULONG Reserved:3;
|
||||
ULONG Ignored:2;
|
||||
ULONG Reserved:1;
|
||||
ULONG Domain:4;
|
||||
ULONG Ignored:1;
|
||||
ULONG Ignored1:1;
|
||||
ULONG BaseAddress:22;
|
||||
} Coarse;
|
||||
struct
|
||||
|
|
@ -93,6 +110,11 @@ typedef struct _ARM_TRANSLATION_TABLE
|
|||
ARM_PTE Pte[4096];
|
||||
} ARM_TRANSLATION_TABLE, *PARM_TRANSLATION_TABLE;
|
||||
|
||||
typedef struct _ARM_COARSE_PAGE_TABLE
|
||||
{
|
||||
ARM_PTE Pte[256];
|
||||
} ARM_COARSE_PAGE_TABLE, *PARM_COARSE_PAGE_TABLE;
|
||||
|
||||
typedef enum _ARM_L1_PTE_TYPE
|
||||
{
|
||||
FaultPte,
|
||||
|
|
@ -101,6 +123,13 @@ typedef enum _ARM_L1_PTE_TYPE
|
|||
FinePte
|
||||
} ARM_L1_PTE_TYPE;
|
||||
|
||||
typedef enum _ARM_L2_PTE_TYPE
|
||||
{
|
||||
LargePte = 1,
|
||||
SmallPte,
|
||||
TinyPte
|
||||
} ARM_L2_PTE_TYPE;
|
||||
|
||||
typedef enum _ARM_PTE_ACCESS
|
||||
{
|
||||
FaultAccess,
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ KeFillFixedEntryTb(IN ARM_PTE Pte,
|
|||
PARM_TRANSLATION_TABLE TranslationTable;
|
||||
|
||||
//
|
||||
// Hack for 1MB Section Entries
|
||||
// Fixed TB entries must be section entries
|
||||
//
|
||||
Virtual = (PVOID)((ULONG)Virtual & 0xFFF00000);
|
||||
|
||||
|
|
@ -69,7 +69,7 @@ KeFillFixedEntryTb(IN ARM_PTE Pte,
|
|||
// Map the PTE for this virtual address
|
||||
//
|
||||
TranslationTable = (PVOID)KeArmTranslationTableRegisterGet().AsUlong;
|
||||
TranslationTable->Pte[(ULONG)Virtual >> TTB_SHIFT] = Pte;
|
||||
TranslationTable->Pte[(ULONG)Virtual >> PDE_SHIFT] = Pte;
|
||||
|
||||
//
|
||||
// Now force a miss
|
||||
|
|
@ -103,7 +103,7 @@ KeFillFixedEntryTb(IN ARM_PTE Pte,
|
|||
//
|
||||
// Clear the PTE
|
||||
//
|
||||
TranslationTable->Pte[(ULONG)Virtual >> TTB_SHIFT].AsUlong = 0;
|
||||
TranslationTable->Pte[(ULONG)Virtual >> PDE_SHIFT].AsUlong = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,10 +20,6 @@ ULONG KeNumberProcessIds;
|
|||
ULONG KeNumberTbEntries;
|
||||
#define __ARMV6__ KeIsArmV6
|
||||
|
||||
//
|
||||
// METAFIXME: We need to stop using 1MB Section Entry TTEs!
|
||||
//
|
||||
|
||||
/* FUNCTIONS ******************************************************************/
|
||||
|
||||
VOID
|
||||
|
|
|
|||
Loading…
Reference in a new issue