Intravision/reactos
1
0
Fork 0
mirror of https://github.com/reactos/reactos.git synced 2025-07-31 21:11:54 +00:00
Code Issues Projects Releases Packages Wiki Activity

[FREELDR][NTOS][HALPPC][SDK] Remove PowerPC code

Browse source 
Remove PowerPC-related code from the kernel, HAL, SDK and
Freeloader.
This commit is contained in:
Victor Perevertkin 2021-08-08 01:50:20 +03:00
parent 911fc3cf5b
commit 6ef6fabfc5
No known key found for this signature in database
GPG key ID: C750B7222E9C7830
88 changed files with 0 additions and 17348 deletions
Download patch file Download diff file Expand all files Collapse all files

277
sdk/include/reactos/libs/ppcmmu/mmu.h
View file

@ -1,277 +0,0 @@
#ifndef PPCMMU_H
#define PPCMMU_H
#include <string.h>
/* PPC MMU object --
* Always called from kernel mode, maps the first 16 megabytes and uses 16
* bytes per page between 0x30000 and 16 megs. Maximum memory size is 3 gig.
*
* Physical Memory Map:
* 0x00300 -- Data Miss
* 0x00400 -- Code Miss
* 0x10000 -- MMU ucode
* 0x20000 -- PTEG
* 0x30000 -- Full map
*
* Actions:
*
* 1** -- MMU Related
*
* 100 -- Initialize
* -- No arguments
* 101 -- Map page
* r4 -- virtual address
* r5 -- ppc_map_info_t
* 102 -- Erase page
* r4 -- virtual address
* 103 -- Set segment VSID
* r4 -- Start seg
* r5 -- End seg
* r6 -- Vsid
* 104 -- Set trap callback
* r4 -- Trap number
* r5 -- Callback address (VA)
* 105 -- Query page
* r4 -- Page addr
* r5 -- Address of info struct
* 106 -- Unit Test
* 107 -- Turn on paging
* 108 -- Unmap process
* 109 -- Get lowest unallocated page
* 10a -- Alloc vsid
* 10b -- Revoke vsid
* 10c -- Allocate a page and return it
* 10d -- Return from trap callback
* 10e -- Dump Map
*
* 2** -- Debug Stub and Interrupt Vectoring
*
* 200 -- GDB Initialize
* r4 -- Device type
* r4 -- Serial port addr
* 201 -- GDB Enter
* r4 -- Signal number
*/
#define MMUCODE 0x10000
#define HTABORG 0x20000
#define HTABSIZ 0x10000
#define PAGETAB 0x30000
#define PpcHashedPTE ((ppc_pteg_t*)(HTABORG))
#define PpcPageTable ((ppc_map_t*)(PAGETAB))
#define PPC_PAGE_ADDR(x) ((x) << 12)
#define PPC_PAGE_NUMBER(x) ((x) >> 12)
#define PPC_VSID_MASK 0xffffff
#define PPC_PAGE_MASK 0xfff
#define MMU_NONE 0
#define MMU_KR 8
#define MMU_KW 4
#define MMU_UR 2
#define MMU_UW 1
#define MMU_ALL_R 10
#define MMU_KRW 12
#define MMU_KRW_UR 14
#define MMU_ALL_RW 15
#define MMU_PAGE_ACCESS 0x40000000
#define MMU_PAGE_DIRTY 0x80000000
#define MMU_KMASK 12
#define MMU_UMASK 3
extern char _binary_mmucode_start[], _binary_mmucode_end[];
/* thanks geist */
typedef unsigned long paddr_t;
typedef unsigned long vaddr_t;
typedef struct _ppc_pte_t {
unsigned long pteh, ptel;
} ppc_pte_t;
typedef struct _ppc_pteg_t {
ppc_pte_t block[8];
} ppc_pteg_t;
typedef struct _ppc_map_t {
ppc_pte_t pte;
unsigned long proc;
vaddr_t addr;
} ppc_map_t;
typedef struct _ppc_map_info_t {
unsigned long flags, proc;
vaddr_t addr;
paddr_t phys;
} ppc_map_info_t;
typedef struct _ppc_trap_frame_t {
unsigned long gpr[32];
unsigned long long fpr[32];
unsigned long srr0, srr1, cr, lr, ctr, dsisr, dar, xer;
} ppc_trap_frame_t;
typedef int (*MmuTrapHandler)(int trapid, ppc_trap_frame_t *trap);
#include "mmuutil.h"
static inline int PPCMMU(int action, void *arg1, void *arg2, void *arg3)
{
/* Set Bat0 to mmu object address */
int i, batu, batl, usebat[2] = { 0, 1 }, gotbat = 0, pc, mask;
volatile int ret;
int (*mmumain)(int action, void *arg1, void *arg2, void *arg3) = (void *)MMUCODE;
__asm__("bl 1f\n\t"
"\n1:\n\t"
"mflr %0\n\t" : "=r" (pc));
for(i = 0, gotbat = 0; i < 4; i++)
{
/* Use the space above the trap handlers to store the old bats */
GetBat(i, 0, &batu, &batl);
SetPhys(0xf000 + i * 16, batu);
SetPhys(0xf004 + i * 16, batl);
GetBat(i, 1, &batu, &batl);
SetPhys(0xf008 + i * 16, batu);
SetPhys(0xf00c + i * 16, batl);
if (gotbat < 2)
{
if(batu & 0xffc)
{
mask = ~(0x1ffff | ((batu & 0xffc)>>2)<<17);
if(!(batu & 2) || ((batu & mask) != (pc & mask)))
usebat[gotbat++] = i;
} else {
mask = ~(0x1ffff | (batl << 17));
if(!(batl & 0x40) || ((batu & mask) != (pc & mask)))
usebat[gotbat++] = i;
}
}
}
batu = 0xff;
batl = 0x7f;
SetBat(usebat[0], 0, batu, batl);
SetBat(usebat[0], 1, batu, batl);
batu += 8192 * 1024;
batl += 8192 * 1024;
SetBat(usebat[1], 0, batu, batl);
SetBat(usebat[1], 1, batu, batl);
ret = mmumain(action, arg1, arg2, arg3);
return ret;
}
/* Expand this only if used ... That makes dependence on libmmu_code.a depend
* on whether MmuInit is called in a clean way.
*/
#define MmuInit() _MmuInit(&_binary_mmucode_start, &_binary_mmucode_end)
/* Copy in the mmu code and call init
* This bootstrap should only be called the first time (i.e. in the bootloader
* or the early boot code). Part of the purpose of this library is to
* eliminate the need to do a complex mmu handoff between boot stages.
*/
static inline void _MmuInit(void *_start, void *_end)
{
int target = MMUCODE, copy;
int *start = (int *)_start;
while(start < (int *)_end)
{
memcpy(&copy, start++, sizeof(int));
SetPhys(target, copy);
target += sizeof(int);
}
PPCMMU(0x100, 0, 0, 0);
}
static inline int MmuMapPage(ppc_map_info_t *info, int count)
{
return PPCMMU(0x101, info, (void *)count, 0);
}
static inline void MmuUnmapPage(ppc_map_info_t *info, int count)
{
PPCMMU(0x102, info, (void *)count, 0);
}
static inline void MmuSetVsid(int start, int end, int vsid)
{
PPCMMU(0x103, (void *)start, (void *)end, (void *)vsid);
}
static inline MmuTrapHandler MmuSetTrapHandler(int trap, MmuTrapHandler cb)
{
return (MmuTrapHandler)PPCMMU(0x104, (void *)trap, (void *)cb, 0);
}
static inline void MmuInqPage(ppc_map_info_t *info, int count)
{
PPCMMU(0x105, info, (void *)count, 0);
}
static inline int MmuUnitTest()
{
return PPCMMU(0x106, 0, 0, 0);
}
static inline int MmuTurnOn(void *fun, void *arg)
{
return PPCMMU(0x107, fun, arg, 0);
}
static inline void MmuSetMemorySize(paddr_t size)
{
PPCMMU(0x108, (void *)size, 0, 0);
}
static inline paddr_t MmuGetFirstPage()
{
return (paddr_t)PPCMMU(0x109, 0, 0, 0);
}
static inline void *MmuAllocVsid(int vsid, int mask)
{
return (void *)PPCMMU(0x10a, (void *)vsid, (void *)mask, 0);
}
static inline void MmuRevokeVsid(int vsid, int mask)
{
PPCMMU(0x10b, (void *)vsid, (void *)mask, 0);
}
static inline paddr_t MmuGetPage()
{
return PPCMMU(0x10c, 0,0,0);
}
static inline void MmuCallbackRet()
{
PPCMMU(0x10d, 0,0,0);
}
static inline void MmuDumpMap()
{
PPCMMU(0x10e, 0,0,0);
}
static inline void MmuDbgInit(int deviceType, int devicePort)
{
PPCMMU(0x200, (void *)deviceType, (void *)devicePort, 0);
}
static inline void MmuDbgEnter(int signal)
{
PPCMMU(0x201, (void *)signal, 0, 0);
}
#endif/*PPCMMU_H*/

23
sdk/include/reactos/libs/ppcmmu/mmuutil.h
View file

@ -1,23 +0,0 @@
#ifndef FREELDR_MMU_H
#define FREELDR_MMU_H
int GetDEC(void);
int GetMSR(void);
int GetPhys( paddr_t addr );
int GetPhysHalf( paddr_t addr );
int GetPhysByte( paddr_t addr );
void SetPhys( paddr_t addr, int val );
void SetPhysHalf( paddr_t addr, int val );
void SetPhysByte( paddr_t addr, int val );
int GetSR(int n);
void SetSR(int n, int val);
void GetBat( int bat, int inst, int *batHi, int *batLo );
void SetBat( int bat, int inst, int batHi, int batLo );
int GetSDR1(void);
void SetSDR1( int newsdr );
int BatHit( int bath, int batl, int virt );
int BatTranslate( int bath, int batl, int virt );
/* translate address */
int PpcVirt2phys( vaddr_t virt, int inst );
int PtegNumber( vaddr_t virt, int hfun );
#endif/*FREELDR_MMU_H*/

1
sdk/lib/CMakeLists.txt
View file

@ -34,7 +34,6 @@ endif()
add_subdirectory(ioevent)
add_subdirectory(lsalib)
add_subdirectory(nt)
add_subdirectory(ppcmmu)
add_subdirectory(pseh)
if(KDBG)

2
sdk/lib/crt/except/except.cmake
View file

@ -64,8 +64,6 @@ elseif(ARCH STREQUAL "amd64")
list(APPEND CHKSTK_ASM_SOURCE except/amd64/chkstk_ms.s)
elseif(ARCH STREQUAL "arm")
list(APPEND CHKSTK_ASM_SOURCE except/arm/chkstk_asm.s)
elseif(ARCH STREQUAL "powerpc")
list(APPEND CHKSTK_ASM_SOURCE except/powerpc/chkstk_asm.s)
endif()
add_asm_files(chkstk_lib_asm ${CHKSTK_ASM_SOURCE})

22
sdk/lib/crt/except/powerpc/chkstk_asm.s
View file

@ -1,22 +0,0 @@
/*
* COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS kernel
* PURPOSE: Stack checker
* FILE: lib/sdk/crt/except/powerpc/chkstk_asm.s
* PROGRAMER: arty
*/
.globl _chkstk
.globl _alloca_probe
/*
_chkstk() is called by all stack allocations of more than 4 KB. It grows the
stack in areas of 4 KB each, trying to access each area. This ensures that the
guard page for the stack is hit, and the stack growing triggered
*/
_chkstk:
_alloca_probe:
/* return */
blr
/* EOF */

75
sdk/lib/crt/except/powerpc/seh.s
View file

@ -1,75 +0,0 @@
/*
* COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS CRT
* FILE: lib/sdk/crt/except/powerpc/seh.s
* PURPOSE: SEH Support for the CRT
* PROGRAMMERS: arty
*/
/* INCLUDES ******************************************************************/
#include <ndk/asm.h>
#define DISPOSITION_DISMISS 0
#define DISPOSITION_CONTINUE_SEARCH 1
#define DISPOSITION_COLLIDED_UNWIND 3
/* GLOBALS *******************************************************************/
.globl _global_unwind2
.globl _local_unwind2
.globl _abnormal_termination
.globl _except_handler2
.globl _except_handler3
/* FUNCTIONS *****************************************************************/
unwind_handler:
blr
_global_unwind2:
blr
_local_unwind2:
blr
_except_handler2:
blr
_except_handler3:
blr
//
//
// REMOVE ME REMOVE ME REMOVE ME REMOVE ME REMOVE ME REMOVE ME REMOVE ME
// sorry
//
//
.globl RtlpGetStackLimits
RtlpGetStackLimits:
stwu 1,16(1)
mflr 0
stw 0,4(1)
stw 3,8(1)
stw 4,12(1)
/* Get the current thread */
lwz 3,KPCR_CURRENT_THREAD(13)
/* Get the stack limits */
lwz 4,KTHREAD_STACK_LIMIT(3)
lwz 5,KTHREAD_INITIAL_STACK(3)
subi 5,5,SIZEOF_FX_SAVE_AREA
/* Return them */
lwz 3,8(1)
stw 4,0(3)
lwz 3,12(1)
stw 5,0(3)
addi 1,1,16
/* return */
blr

8
sdk/lib/ppcmmu/CMakeLists.txt
View file

@ -1,8 +0,0 @@
list(APPEND SOURCE dummy.c)
if(ARCH STREQUAL "powerpc")
list(APPEND SOURCE mmuutil.c)
endif()
add_library(ppcmmu ${SOURCE})

222
sdk/lib/ppcmmu/devint.s
View file

@ -1,222 +0,0 @@
/* PowerPC Trap Handler first Half */
.text
.globl mmumain
.globl _mmumain
mmumain:
mr 0,1
lis 1,2
subi 1,1,448
stw 0,20(1)
stw 2,24(1)
stw 3,28(1)
stw 4,32(1)
stw 5,36(1)
stw 6,40(1)
stw 7,44(1)
stw 8,48(1)
stw 9,52(1)
stw 10,56(1)
stw 11,60(1)
stw 12,64(1)
stw 13,68(1)
stw 14,72(1)
stw 15,76(1)
stw 16,80(1)
stw 17,84(1)
stw 18,88(1)
stw 19,92(1)
stw 20,96(1)
stw 21,100(1)
stw 22,104(1)
stw 23,108(1)
stw 24,112(1)
stw 25,116(1)
stw 26,120(1)
stw 27,124(1)
stw 28,128(1)
stw 29,132(1)
stw 30,136(1)
stw 31,140(1)
mfsrr0 0
stw 0,400(1)
mfmsr 0
stw 0,404(1)
mfcr 0
stw 0,408(1)
mflr 0
stw 0,412(1)
mfctr 0
stw 0,416(1)
mfdsisr 0
stw 0,420(1)
mfdar 0
stw 0,424(1)
mfxer 0
stw 0,428(1)
addi 7,1,16
lis 8,_mmumain@ha
addi 8,8,_mmumain@l
mtctr 8
bctrl
addi 1,1,16
lwz 2,8(1)
/* Don't reload r3, since we'll return a result */
lwz 4,16(1)
lwz 5,20(1)
lwz 6,24(1)
lwz 7,28(1)
lwz 8,32(1)
lwz 9,36(1)
lwz 10,40(1)
lwz 11,44(1)
lwz 12,48(1)
lwz 13,52(1)
lwz 14,56(1)
lwz 15,60(1)
lwz 16,64(1)
lwz 17,68(1)
lwz 18,72(1)
lwz 19,76(1)
lwz 20,80(1)
lwz 21,84(1)
lwz 22,88(1)
lwz 23,92(1)
lwz 24,96(1)
lwz 25,100(1)
lwz 26,104(1)
lwz 27,108(1)
lwz 28,112(1)
lwz 29,116(1)
lwz 30,120(1)
lwz 31,124(1)
lwz 0,392(1)
mtcr 0
lwz 0,396(1)
mtsrr0 0
lwz 0,400(1)
mtctr 0
lwz 0,388(1) /* Copy out new MSR bits if needed */
lwz 1,4(1)
mtsrr1 0
rfi
.globl trap_start
.globl trap_end
trap_start:
mtsprg1 1
lis 1,2
subi 1,1,448
stw 0,16(1)
mfsprg1 0
stw 0,20(1)
stw 2,24(1)
stw 3,28(1)
stw 4,32(1)
stw 5,36(1)
stw 6,40(1)
stw 7,44(1)
stw 8,48(1)
stw 9,52(1)
stw 10,56(1)
stw 11,60(1)
stw 12,64(1)
stw 13,68(1)
stw 14,72(1)
stw 15,76(1)
stw 16,80(1)
stw 17,84(1)
stw 18,88(1)
stw 19,92(1)
stw 20,96(1)
stw 21,100(1)
stw 22,104(1)
stw 23,108(1)
stw 24,112(1)
stw 25,116(1)
stw 26,120(1)
stw 27,124(1)
stw 28,128(1)
stw 29,132(1)
stw 30,136(1)
stw 31,140(1)
mfsrr0 0
stw 0,400(1)
mfsrr1 0
stw 0,404(1)
mfcr 0
stw 0,408(1)
mflr 0
stw 0,412(1)
mfctr 0
stw 0,416(1)
mfdsisr 0
stw 0,420(1)
mfdar 0
stw 0,424(1)
mfxer 0
stw 0,428(1)
bl 1f
1: mflr 5
addi 4,1,16
rlwinm 3,5,24,0xff
lwz 5,36(5)
mtctr 5
lis 5,trap_finish_start@ha
addi 5,5,trap_finish_start@l
mtlr 5
bctr
trap_end:
.space 4
.globl trap_finish_start
trap_finish_start:
addi 1,1,16
lwz 2,8(1)
lwz 3,12(1)
lwz 4,16(1)
lwz 5,20(1)
lwz 6,24(1)
lwz 7,28(1)
lwz 8,32(1)
lwz 9,36(1)
lwz 10,40(1)
lwz 11,44(1)
lwz 12,48(1)
lwz 13,52(1)
lwz 14,56(1)
lwz 15,60(1)
lwz 16,64(1)
lwz 17,68(1)
lwz 18,72(1)
lwz 19,76(1)
lwz 20,80(1)
lwz 21,84(1)
lwz 22,88(1)
lwz 23,92(1)
lwz 24,96(1)
lwz 25,100(1)
lwz 26,104(1)
lwz 27,108(1)
lwz 28,112(1)
lwz 29,116(1)
lwz 30,120(1)
lwz 31,124(1)
lwz 0,384(1)
mtsrr0 0
lwz 0,388(1)
mtsrr1 0
lwz 0,392(1)
mtcr 0
lwz 0,396(1)
mtlr 0
lwz 0,400(1)
mtctr 0
lwz 0,404(1)
mtdsisr 0
lwz 0,412(1)
mtdar 0
lwz 0,416(1)
mtxer 0
lwz 0,0(1)
lwz 1,4(1)
rfi

0
sdk/lib/ppcmmu/dummy.c
View file

475
sdk/lib/ppcmmu/gdblib.c
View file

@ -1,475 +0,0 @@
/****************************************************************************
THIS SOFTWARE IS NOT COPYRIGHTED
HP offers the following for use in the public domain. HP makes no
warranty with regard to the software or it's performance and the
user accepts the software "AS IS" with all faults.
HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
****************************************************************************/
/****************************************************************************
* Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $
*
* Module name: remcom.c $
* Revision: 1.34 $
* Date: 91/03/09 12:29:49 $
* Contributor: Lake Stevens Instrument Division$
*
* Description: low level support for gdb debugger. $
*
* Considerations: only works on target hardware $
*
* Written by: Glenn Engel $
* ModuleState: Experimental $
*
* NOTES: See Below $
*
* Modified for 386 by Jim Kingdon, Cygnus Support.
* Modified for ReactOS by Casper S. Hornstrup <chorns@users.sourceforge.net>
* Modified heavily for PowerPC ReactOS by arty
*
* To enable debugger support, two things need to happen. One, setting
* up a routine so that it is in the exception path, is necessary in order
* to allow any breakpoints or error conditions to be properly intercepted
* and reported to gdb.
* Two, a breakpoint needs to be generated to begin communication.
ER*
* Because gdb will sometimes write to the stack area to execute function
* calls, this program cannot rely on using the supervisor stack so it
* uses it's own stack area.
*
*************
*
* The following gdb commands are supported:
*
* command function Return value
*
* g return the value of the CPU Registers hex data or ENN
* G set the value of the CPU Registers OK or ENN
*
* mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
* MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
*
* c Resume at current address SNN ( signal NN)
* cAA..AA Continue at address AA..AA SNN
*
* s Step one instruction SNN
* sAA..AA Step one instruction from AA..AA SNN
*
* k kill
*
* ? What was the last sigval ? SNN (signal NN)
*
* All commands and responses are sent with a packet which includes a
* Checksum. A packet consists of
*
* $<packet info>#<Checksum>.
*
* where
* <packet info> :: <characters representing the command or response>
* <Checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
*
* When a packet is received, it is first acknowledged with either '+' or '-'.
* '+' indicates a successful transfer. '-' indicates a failed transfer.
*
* Example:
*
* Host: Reply:
* $m0,10#2a +$00010203040506070809101112131415#42
*
****************************************************************************/
#include "ppcmmu/mmu.h"
#define GDB_SAVE_SIZE 0x66
typedef struct _BREAKPOINT {
int OldCode;
int *Address;
} BREAKPOINT, *PBREAKPOINT;
BREAKPOINT BreakPoints[64];
char DataOutBuffer[1024];
volatile int DataOutAddr, DataOutCsum;
char DataInBuffer[128];
volatile int DataInAddr, ParseState = 0, ComputedCsum, ActualCsum;
volatile int PacketSent = 0, SendSignal = 0;
volatile int Continue = 0, Signal = 0;
volatile ppc_trap_frame_t RegisterSaves, *RegisterSaveArea = &RegisterSaves;
char *hex = "0123456789abcdef";
#define RCV 0
#define THR 0
#define BAUDLOW 0
#define BAUDHIGH 1
#define IER 1
#define FCR 2
#define ISR 2
#define LCR 3
#define MCR 4
#define LSR 5
#define MSR 6
#define SPR 7
extern void send(char *serport, char c);
extern char recv(char *serport);
extern void setup(char *serport, int baud);
char *serport = (char *)0x800003f8;
int isxdigit(int ch)
{
return
(ch >= 'A' && ch <= 'F') ||
(ch >= 'a' && ch <= 'f') ||
(ch >= '0' && ch <= '9');
}
inline void sync() {
__asm__("eieio\n\t"
"sync");
}
inline void send(char *serport, char c) {
/* Wait for Clear to Send */
while( !(GetPhysByte((paddr_t)serport+LSR) & 0x20) ) sync();
SetPhysByte((paddr_t)serport+THR, c);
sync();
}
inline int rdy(char *serport)
{
sync();
return (GetPhysByte((paddr_t)serport+LSR) & 0x20);
}
inline int chr(char *serport)
{
sync();
return GetPhysByte((paddr_t)serport+LSR) & 1;
}
inline char recv(char *serport) {
char c;
while( !chr(serport) ) sync();
c = GetPhysByte((paddr_t)serport+RCV);
sync();
return c;
}
void setup(char *serport, int baud) {
int x = 115200 / baud;
SetPhysByte((paddr_t)serport+LCR, 128);
sync();
SetPhysByte((paddr_t)serport+BAUDLOW, x & 255);
sync();
SetPhysByte((paddr_t)serport+BAUDHIGH, x >> 8);
sync();
SetPhysByte((paddr_t)serport+LCR, 3);
sync();
}
void SerialSetUp(int deviceType, void *deviceAddr, int baud)
{
int i;
serport = deviceAddr;
setup(serport, baud);
}
extern int SerialInterrupt(int signal, ppc_trap_frame_t *tf);
void IntEnable()
{
SetPhysByte((paddr_t)serport+IER, GetPhysByte((paddr_t)serport+IER) | 1);
}
void SerialWrite(int ch)
{
send(serport, ch);
}
int SerialRead()
{
return recv(serport);
}
int hex2int(int ch)
{
if (ch >= 'a' && ch <= 'f') return ch + 10 - 'a';
else if (ch >= 'A' && ch <= 'F') return ch + 10 - 'A';
else return ch - '0';
}
int PacketReadHexNumber(int dig)
{
int i;
int result = 0;
for (i = 0; i < dig && isxdigit(DataInBuffer[DataInAddr]); i++)
{
result <<= 4;
result |= hex2int(DataInBuffer[DataInAddr++]);
}
return result;
}
void PacketWriteChar(int ch)
{
DataOutCsum += ch;
DataOutBuffer[DataOutAddr++] = ch;
}
int PacketWriteHexNumber(int hnum, int dig)
{
int i;
hnum <<= (8 - dig) * 4;
for (i = 0; i < dig; i++)
{
PacketWriteChar(hex[(hnum >> 28) & 15]);
hnum <<= 4;
}
return i;
}
void PacketStart()
{
DataOutCsum = 0;
DataOutAddr = 0;
}
void PacketFinish()
{
int i, ch, count = 0;
PacketSent = 0;
SerialWrite('$');
for (i = 0; i < DataOutAddr; i++)
{
SerialWrite(DataOutBuffer[i]);
}
SerialWrite('#');
SerialWrite(hex[(DataOutCsum >> 4) & 15]);
SerialWrite(hex[DataOutCsum & 15]);
while(!chr(serport) && ((ch = SerialRead()) != '+') && (ch != '$'));
if (ch == '$')
{
ParseState = 0;
DataInAddr = 0;
ComputedCsum = 0;
}
}
void PacketWriteString(char *str)
{
while(*str) PacketWriteChar(*str++);
}
void PacketOk()
{
PacketStart();
PacketWriteString("OK");
PacketFinish();
}
void PacketEmpty()
{
PacketStart();
PacketFinish();
}
void PacketWriteSignal(int code)
{
PacketStart();
PacketWriteChar('S');
PacketWriteHexNumber(code, 2);
PacketFinish();
}
void PacketWriteError(int code)
{
PacketStart();
PacketWriteChar('E');
PacketWriteHexNumber(code, 2);
PacketFinish();
}
void marker() { }
void GotPacket()
{
int i, memaddr, memsize;
Continue = 0;
switch (DataInBuffer[DataInAddr++])
{
case 'g':
PacketStart();
for (i = 0; i < GDB_SAVE_SIZE; i++)
{
PacketWriteHexNumber(((int *)RegisterSaveArea)[i], 8);
}
PacketFinish();
break;
case 'G':
for (i = 0; i < sizeof(*RegisterSaveArea) / sizeof(int); i++)
{
((int *)RegisterSaveArea)[i] = PacketReadHexNumber(8);
}
PacketOk();
break;
case 'm':
memaddr = PacketReadHexNumber(8);
DataInAddr++;
memsize = PacketReadHexNumber(8);
PacketStart();
while(memsize-- > 0)
{
PacketWriteHexNumber(*((char *)memaddr++), 2);
}
PacketFinish();
break;
case 'M':
memaddr = PacketReadHexNumber(8);
DataInAddr++;
memsize = PacketReadHexNumber(8);
DataInAddr++;
while(memsize-- > 0)
{
*((char *)memaddr++) = PacketReadHexNumber(2);
}
PacketOk();
break;
case '?':
PacketWriteSignal(Signal);
break;
case 'c':
PacketOk();
Continue = 1;
break;
case 'S':
PacketOk();
Continue = 0;
break;
case 's':
RegisterSaveArea->srr1 |= 0x400;
PacketOk();
Continue = 1;
marker();
break;
case 'q':
switch (DataInBuffer[1])
{
case 'S': /*upported => nothing*/
PacketEmpty();
break;
case 'O': /*ffsets*/
PacketEmpty();
break;
}
break;
default:
PacketEmpty();
break;
}
}
int SerialInterrupt(int signal, ppc_trap_frame_t *tf)
{
int ch;
if (!chr(serport)) return 0;
Signal = signal;
RegisterSaveArea = tf;
do
{
ch = SerialRead();
if (ch == 3) /* Break in - tehe */
{
Continue = 0;
PacketWriteSignal(3);
}
else if (ch == '+')
{
/* Nothing */
}
else if (ch == '$')
{
DataInAddr = 0;
ParseState = 0;
ComputedCsum = 0;
ActualCsum = 0;
}
else if (ch == '#' && ParseState == 0)
{
ParseState = 2;
}
else if (ParseState == 0)
{
ComputedCsum += ch;
DataInBuffer[DataInAddr++] = ch;
}
else if (ParseState == 2)
{
ActualCsum = ch;
ParseState++;
}
else if (ParseState == 3)
{
ActualCsum = hex2int(ch) | (hex2int(ActualCsum) << 4);
ComputedCsum &= 255;
ParseState = -1;
if (ComputedCsum == ActualCsum)
{
ComputedCsum = 0;
DataInBuffer[DataInAddr] = 0;
DataInAddr = 0;
Continue = 0;
SerialWrite('+');
GotPacket();
}
else
SerialWrite('-');
}
else if (ParseState == -1)
SerialWrite('-');
}
while (!Continue);
return 1;
}
int TakeException(int n, ppc_trap_frame_t *tf)
{
Signal = n;
RegisterSaveArea = tf;
PacketWriteSignal(Signal);
SendSignal = 0;
Continue = 0;
while(!Continue) SerialInterrupt(n, tf);
return 1;
}
/* EOF */

8
sdk/lib/ppcmmu/ldscript
View file

@ -1,8 +0,0 @@
OUTPUT_FORMAT(elf32-powerpc);
SECTIONS
{
.text : { *(.text) }
.data : { *(.data) *(.rodata) }
.bss : { *(.sbss) *(.bss) *(COMMON) }
}

766
sdk/lib/ppcmmu/mmuobject.c
View file

@ -1,766 +0,0 @@
#include <stdarg.h>
#include "ppcmmu/mmu.h"
#include "ppcmmu/mmuutil.h"
#include "mmuobject.h"
typedef unsigned long ULONG;
/*
The MMU Object:
0x00300 -- Data miss
0x00400 -- Instruction miss
0x10000 -- Entry point
... Code
0x20000 -- Physical map (PTE + Process Ptr + Address : 16 bytes)
4096 / 16 bytes = 256 entries per page
256 pages = 1Megabyte = 1 page table page
Setup by freeldr and used to build the kernel map, then used by the kernel
Calling:
r3 -- Action
r4 .. r6 -- Args
Actions:
00 Init
01 Map pages
02 erase pages
03 set segment vsid
04 page miss callback
05 inquire page
06 unit test
07 alloc page
08 set memory size
09 get first usable page
10 alloc vsid
11 revoke vsid
*/
#define MMU_ADDR_RESERVED ((vaddr_t)-2)
MmuTrapHandler callback[0x30];
typedef struct _MmuFreePage {
int page;
struct _MmuFreePage *next;
} MmuFreePage;
typedef struct _MmuFreeTree {
struct _MmuFreeTree *next;
} MmuFreeTree;
typedef struct _MmuVsidTree {
ppc_map_t *leaves[256];
} MmuVsidTree;
typedef struct _MmuVsidInfo {
int vsid;
struct _MmuVsidInfo *next;
MmuVsidTree *tree[256];
} MmuVsidInfo;
MmuFreePage *FreeList = 0;
// Pages are allocated one by one until NextPage == RamSize >> PPC_PAGE_SHIFT
// Then we take only from the free list
int Clock = 0, TreeAlloc = 0, GdbAttach = 0, Booted = 0, Vsid[16];
paddr_t RamSize, FirstUsablePage, NextPage;
MmuVsidTree *NextTreePage = 0;
MmuFreeTree *FreeTree;
MmuVsidInfo *Segs[16], *VsidHead = 0;
extern void fmtout(const char *fmt, ...);
extern char *serport;
int ptegreload(ppc_trap_frame_t *frame, vaddr_t addr);
void SerialSetUp(int deviceType, void *deviceAddr, int baud);
int SerialInterrupt(int n, ppc_trap_frame_t *tf);
void TakeException(int n, ppc_trap_frame_t *tf);
int mmuisfreepage(paddr_t pageno);
void copy(void *t, void *s, int b);
paddr_t mmunewpage();
void dumpmap();
void trapcallback(int action, ppc_trap_frame_t *trap_frame);
int _mmumain(int action, void *arg1, void *arg2, void *arg3, void *tf)
{
ppc_trap_frame_t *trap_frame = (action >= 0x100) ? tf : arg1;
int ret = 0, tmp, i;
switch(action)
{
/* Trap Handlers */
case 3:
if(!ptegreload(trap_frame, trap_frame->dar))
{
trapcallback(action, trap_frame);
}
break;
case 4:
if(!ptegreload(trap_frame, trap_frame->srr0))
{
trapcallback(action, trap_frame);
}
break;
case 5:
/* EE -- Try to get a serial interrupt if debugging enabled, then fall
* back to primary handler
*/
if (!SerialInterrupt(action, trap_frame) && callback[action])
{
trapcallback(action, trap_frame);
}
break;
case 0:
case 2:
case 6:
case 7:
case 8:
case 9:
case 0xa:
case 0xc:
case 0x20:
trapcallback(action, trap_frame);
break;
/* MMU Functions */
case 0x100:
initme();
trap_frame->srr1 |= 0x8000;
break;
case 0x101:
ret = mmuaddpage(arg1, (int)arg2);
break;
case 0x102:
mmudelpage(arg1, (int)arg2);
break;
case 0x103:
mmusetvsid((int)arg1, (int)arg2, (int)arg3);
break;
case 0x104:
ret = (int)callback[(int)arg1];
callback[(int)arg1] = (MmuTrapHandler)arg2;
break;
case 0x105:
mmugetpage(arg1, (int)arg2);
break;
case 0x106:
ret = mmunitest();
break;
case 0x107:
callkernel(arg1, arg2);
break;
case 0x108:
mmusetramsize((paddr_t)arg1);
break;
case 0x109:
return FirstUsablePage;
case 0x10a:
mmuallocvsid((int)arg1, (int)arg2);
break;
case 0x10b:
mmufreevsid((int)arg1, (int)arg2);
break;
case 0x10c:
ret = mmunewpage();
break;
case 0x10d:
copy(trap_frame, (void *)0xf040, sizeof(*trap_frame));
__asm__("mr 1,%0\n\tb trap_finish_start" : : "r"
(((int)trap_frame) - 16));
break;
case 0x10e:
dumpmap();
break;
case 0x200:
SerialSetUp((int)arg1, arg2, 9600);
break;
case 0x201:
TakeException((int)arg1, trap_frame);
break;
default:
while(1);
}
/* Restore bats when we were called voluntarily. We may not get a chance
* to do this after returning.
*
* At this point, we're in address space that matches physical space.
* We turn off mapping, restore bats, then let rfi switch us back to where
* we came.
*/
if (action >= 0x100)
{
__asm__("mfmsr %0" : "=r" (tmp));
tmp &= ~0x30;
__asm__("mtmsr %0" : : "r" (tmp));
for(i = 0; i < 4; i++) {
SetBat(i, 0, GetPhys(0xf000 + i * 16), GetPhys(0xf004 + i * 16));
SetBat(i, 1, GetPhys(0xf008 + i * 16), GetPhys(0xf00c + i * 16));
}
}
return ret;
}
void trapcallback(int action, ppc_trap_frame_t *trap_frame)
{
if ((paddr_t)callback[action] < PAGETAB)
callback[action](action, trap_frame);
else
{
int framecopy = 0xf040;
copy((void *)framecopy, trap_frame, sizeof(*trap_frame));
trap_frame->srr0 = (int)callback[action];
trap_frame->srr1 &= 0x7fff;
trap_frame->gpr[3] = action;
trap_frame->gpr[4] = framecopy;
__asm__("mr 1,%0\n\tsubi 1,1,16\n\tb trap_finish_start" : : "r" (trap_frame));
}
}
void outchar(char c)
{
SetPhysByte(0x800003f8, c);
}
void copy(void *target, void *src, int bytes)
{
while(bytes--) *((char *)target++) = *((char *)src++);
}
void outstr(const char *str)
{
while(*str) outchar(*str);
}
void outdig(int dig)
{
if(dig < 10) outchar(dig + '0');
else outchar(dig - 10 + 'A');
}
void outnum(unsigned long num)
{
int i;
for( i = 0; i < 8; i++ )
{
outdig(num >> 28);
num <<= 4;
}
}
void fmtout(const char *str, ...)
{
va_list ap;
va_start(ap, str);
while(*str)
{
if(*str == '%')
{
if(str[1] == '%')
{
outchar('%');
}
else if(str[1] == 's')
{
outstr(va_arg(ap, const char *));
}
else
{
outnum(va_arg(ap, int));
}
str++;
}
else
{
outchar(*str);
}
str++;
}
va_end(ap);
}
void mmusetramsize(paddr_t ramsize)
{
ppc_map_t *last_map = &PpcPageTable[PPC_PAGE_NUMBER(ramsize)];
if(!RamSize)
{
RamSize = ramsize;
FirstUsablePage = (paddr_t)last_map;
NextPage = PPC_PAGE_NUMBER(FirstUsablePage) + 1;
}
}
int ignore(int trapCode, ppc_trap_frame_t *trap)
{
return 1;
}
int fpenable(int trapCode, ppc_trap_frame_t *trap)
{
/* Turn on FP */
trap->srr1 |= 8192;
return 1;
}
extern int trap_start[], trap_end[];
void copy_trap_handler(int trap)
{
int i;
paddr_t targetArea = trap * 0x100;
/* Set target addr */
trap_end[0] = (int)_mmumain;
for (i = 0; i <= trap_end - trap_start; i++)
{
SetPhys(targetArea + (i * sizeof(int)), trap_start[i]);
}
}
void initme()
{
int i;
for(i = 0; i < HTABSIZ / sizeof(int); i++)
{
((int *)HTABORG)[i] = 0;
}
/* Default to hang on unknown exception */
for(i = 0; i < 30; i++)
{
callback[i] = (MmuTrapHandler)TakeException;
if (i != 1) /* Preserve reset handler */
copy_trap_handler(i);
}
/* Serial Interrupt */
callback[5] = 0; /* Do nothing until the user asks */
/* Program Exception */
callback[6] = (MmuTrapHandler)TakeException;
/* Floating point exception */
callback[8] = fpenable;
/* Ignore decrementer and EE */
callback[9] = ignore;
/* Single Step */
callback[0x20] = (MmuTrapHandler)TakeException;
}
ppc_map_t *allocpage()
{
MmuFreePage *FreePage = 0;
if (FreeList)
{
if ((void *)FreeList == (void *)PpcPageTable)
{
fmtout("Problem! FreeList: page 0 is free\n");
while(1);
}
FreePage = FreeList;
FreeList = FreeList->next;
((ppc_map_t*)FreePage)->addr = MMU_ADDR_RESERVED;
return ((ppc_map_t*)FreePage);
}
else
{
while(!mmuisfreepage(NextPage) && NextPage < PPC_PAGE_NUMBER(RamSize))
{
NextPage++;
}
if (NextPage < PPC_PAGE_NUMBER(RamSize))
{
if (NextPage < 0x30)
{
fmtout("Problem! NextPage is low (%x)\n", NextPage);
while(1);
}
PpcPageTable[NextPage].addr = MMU_ADDR_RESERVED;
return &PpcPageTable[NextPage++];
}
else
{
return NULL;
}
}
}
void freepage(ppc_map_t *PagePtr)
{
MmuFreePage *FreePage = (MmuFreePage*)PagePtr;
PagePtr->proc = PagePtr->addr = 0;
FreePage->next = FreeList;
FreeList = FreePage;
}
MmuVsidTree *allocvsidtree()
{
if(FreeTree)
{
MmuVsidTree *result = (MmuVsidTree*)FreeTree;
FreeTree = FreeTree->next;
return result;
}
else if(TreeAlloc >= 3 || !NextTreePage)
{
ppc_map_t *map = allocpage();
NextTreePage = (MmuVsidTree*)PPC_PAGE_ADDR((map - PpcPageTable));
TreeAlloc = 1;
return NextTreePage;
}
else
{
return &NextTreePage[TreeAlloc++];
}
}
void freevsidtree(MmuVsidTree *tree)
{
int i;
for(i = 0; i < 256; i++)
if(tree->leaves[i])
freepage(tree->leaves[i]);
MmuFreeTree *NextFreeTree = (MmuFreeTree *)tree;
NextFreeTree->next = FreeTree;
FreeTree = NextFreeTree;
}
void *allocvsid(int vsid)
{
ppc_map_t *map = allocpage();
MmuVsidInfo *info;
if(!map) return 0;
map->pte.pteh = map->pte.ptel = 0;
info = (MmuVsidInfo*)PPC_PAGE_ADDR((map - PpcPageTable));
info->vsid = vsid;
info->next = VsidHead;
VsidHead = info;
return info;
}
void mmuallocvsid(int vsid, int mask)
{
int i;
for(i = 0; i < 16; i++)
{
if(mask & (1 << i))
allocvsid((vsid << 4) + i);
}
}
MmuVsidInfo *findvsid(int vsid)
{
MmuVsidInfo *info;
for(info = VsidHead; info; info = info->next)
{
if(info->vsid == vsid) return info;
}
return 0;
}
void freevsid(int vsid)
{
int i;
MmuVsidInfo *info = findvsid(vsid);
if(!info) return;
ppc_map_t *map = &PpcPageTable[PPC_PAGE_NUMBER((paddr_t)info)];
for(i = 0; i < 256; i++)
{
if(info->tree[i])
freevsidtree(info->tree[i]);
}
freepage(map);
}
void mmufreevsid(int vsid, int mask)
{
int i;
for(i = 0; i < 16; i++)
{
if(mask & (1 << i))
freevsid((vsid << 4) + i);
}
}
int mmuaddpage(ppc_map_info_t *info, int count)
{
int i, iva = 0, vsid, phys, virt;
int ptehi;
int ptelo, vsid_table_hi, vsid_table_lo;
ppc_map_t *PagePtr;
MmuVsidInfo *VsidInfo;
MmuVsidTree *VsidTree;
for(i = 0; i < count; i++)
{
info[i].phys &= ~PPC_PAGE_MASK;
info[i].addr &= ~PPC_PAGE_MASK;
virt = info[i].addr;
vsid = ((info[i].addr >> 28) & 15) | (info[i].proc << 4);
VsidInfo = findvsid(vsid);
if(!VsidInfo) return -1;
ptehi = (1 << 31) | (vsid << 7) | ((virt >> 22) & 0x3f);
if(info[i].phys) {
PagePtr = &PpcPageTable[PPC_PAGE_NUMBER(info[i].phys)];
} else {
PagePtr = allocpage();
if(!PagePtr)
{
return 0;
}
}
phys = PPC_PAGE_ADDR((PagePtr - PpcPageTable));
ptelo = phys & ~PPC_PAGE_MASK;
if (phys < 0x30000)
{
/* Should not be allocating physical */
fmtout("Allocated physical: %x, logical %x\n", phys, virt);
fmtout("PagePtr %x (page %d)\n", PagePtr, i);
fmtout("info [ %x %x %x %x ]\n", info[i].proc, info[i].addr, info[i].flags, info[i].phys);
while(1);
}
/* Update page data */
PagePtr->pte.pteh = ptehi;
PagePtr->pte.ptel = ptelo;
PagePtr->proc = info[i].proc;
PagePtr->addr = virt;
vsid_table_hi = virt >> 20 & 255;
vsid_table_lo = virt >> 12 & 255;
if(!VsidInfo->tree[vsid_table_hi])
VsidInfo->tree[vsid_table_hi] = allocvsidtree();
VsidTree = VsidInfo->tree[vsid_table_hi];
if(!VsidTree) return 0;
VsidTree->leaves[vsid_table_lo] = PagePtr;
__asm__("tlbie %0\n\tsync\n\tisync" : : "r" (iva));
}
return 1;
}
paddr_t mmunewpage()
{
ppc_map_t *PagePtr = allocpage();
if (!PagePtr) return 0;
return PPC_PAGE_ADDR(PagePtr - PpcPageTable);
}
ppc_pteg_t *PtegFromPage(ppc_map_t *map, int hfun)
{
if(!map->proc && !map->addr) return 0;
return &PpcHashedPTE[PtegNumber(map->addr, hfun)];
}
int PageMatch(vaddr_t addr, ppc_pte_t pte)
{
int vsid_pte = (pte.pteh >> 7) & 15, api_pte = pte.pteh & 63;
return
(((addr >> 28) & 15) == vsid_pte) &&
(((addr >> 22) & 63) == api_pte);
}
ppc_map_t *mmuvirtmap(vaddr_t addr)
{
int seg = (addr >> 28) & 15;
MmuVsidInfo *seginfo = Segs[seg];
MmuVsidTree *segtree = 0;
if(!seginfo) return 0;
segtree = seginfo->tree[(addr >> 20) & 255];
if(!segtree) return 0;
return segtree->leaves[(addr >> 12) & 255];
}
void mmudelpage(ppc_map_info_t *info, int count)
{
int i, j, k, ipa;
ppc_map_t *PagePtr;
ppc_pteg_t *PageEntry;
ppc_pte_t ZeroPte = { 0 };
for(i = 0; i < count; i++)
{
if (info[i].phys)
{
ipa = info[i].phys;
PagePtr = &PpcPageTable[ipa];
info[i].proc = PagePtr->proc;
info[i].addr = PagePtr->addr;
}
else
{
PagePtr = mmuvirtmap(info[i].addr);
ipa = PPC_PAGE_ADDR(PagePtr - PpcPageTable);
}
for(j = 0; j < 2; j++)
{
PageEntry = PtegFromPage(PagePtr, j);
for(k = 0; k < 8; k++)
{
if(PageMatch(ipa, PageEntry->block[k]))
{
if(PageEntry->block[k].ptel & 0x100)
info[i].flags |= MMU_PAGE_DIRTY;
PageEntry->block[k] = ZeroPte;
}
}
}
freepage(PagePtr);
__asm__("tlbie %0\n\tsync\n\tisync" : : "r" (info[i].addr));
}
}
void mmugetpage(ppc_map_info_t *info, int count)
{
int i;
ppc_map_t *PagePtr;
for( i = 0; i < count; i++ )
{
if(!info[i].addr && !info[i].proc)
{
PagePtr = &((ppc_map_t*)PAGETAB)[info[i].phys];
info[i].proc = PagePtr->proc;
info[i].addr = PagePtr->addr;
info[i].flags = MMU_ALL_RW;
} else {
vaddr_t addr = info[i].addr;
int vsid = ((addr >> 28) & 15) | (info[i].proc << 4);
PagePtr = mmuvirtmap(info[i].addr);
if(!PagePtr)
info[i].phys = 0;
else
{
info[i].phys = PPC_PAGE_ADDR(PagePtr - PpcPageTable);
info[i].flags = MMU_ALL_RW; // HACK
}
}
}
}
int mmuisfreepage(paddr_t pageno)
{
ppc_map_t *PagePtr = PpcPageTable + pageno;
return !PagePtr->addr;
}
void mmusetvsid(int start, int end, int vsid)
{
int i, sr, s_vsid;
for(i = start; i < end; i++)
{
s_vsid = (vsid << 4) | (i & 15);
sr = (GetSR(i) & ~PPC_VSID_MASK) | s_vsid;
if (Booted)
SetSR(i, sr);
Segs[i] = findvsid(s_vsid);
Vsid[i] = vsid;
}
}
int ptegreload(ppc_trap_frame_t *frame, vaddr_t addr)
{
int hfun = (Clock >> 3) & 1, ptegnum = PtegNumber(addr, hfun);
ppc_map_t *map = mmuvirtmap(addr);
if(!map) return 0;
map->pte.pteh = (map->pte.pteh & ~64) | (hfun << 6);
PpcHashedPTE[ptegnum].block[Clock & 7] = map->pte;
#if 0
fmtout("Reloading addr %x (phys %x) at %x[%x] (%x:%x)\r\n",
addr, PPC_PAGE_ADDR(map - PpcPageTable), ptegnum, Clock & 15,
PpcHashedPTE[ptegnum].block[Clock&7].pteh,
PpcHashedPTE[ptegnum].block[Clock&7].ptel);
#endif
Clock++;
__asm__("tlbie %0\n\tsync\n\tisync" : : "r" (addr));
return 1;
}
void printmap(vaddr_t vaddr, ppc_map_t *map)
{
fmtout("%x: proc %x addr %x\n",
PPC_PAGE_ADDR(map - PpcPageTable),
map->proc, vaddr);
}
void dumptree(vaddr_t vaddr, MmuVsidTree *tree)
{
int j;
for (j = 0; j < 256; j++)
{
if (tree->leaves[j])
{
printmap(vaddr | (j << 12), tree->leaves[j]);
}
}
}
void dumpvsid(MmuVsidInfo *vsid)
{
int i;
fmtout("vsid %d (%x):\n", vsid->vsid>>4, vsid->vsid<<28);
for (i = 0; i < 256; i++)
{
if (vsid->tree[i])
{
dumptree((vsid->vsid<<28) | i << 20, vsid->tree[i]);
}
}
}
void dumpmap()
{
int i,j;
ppc_map_t *map;
MmuVsidInfo *vsid;
fmtout("Address spaces:\n");
for (vsid = VsidHead; vsid; vsid = vsid->next)
{
dumpvsid(vsid);
}
}
void callkernel(void *fun_ptr, void *arg)
{
int i;
Booted = 1;
for (i = 0; i < 16; i++)
{
// Patch up the vsid map. We shouldn't muck with these until we're
// booted.
mmusetvsid(i, i+1, Vsid[i]);
}
void (*fun)(void *) = fun_ptr;
__asm__("mfmsr 3\n\t"
"ori 3,3,0x30\n\t"
"mtmsr 3\n\t"
"mtsdr1 %0\n\t"
"mr 0,%2\n\t"
"mtctr 0\n\t"
"mr 3,%1\n\t"
"bctrl\n\t"
: : "r" (HTABORG), "r" (arg), "r" (fun));
/* BYE ! */
}

14
sdk/lib/ppcmmu/mmuobject.h
View file

@ -1,14 +0,0 @@
#pragma once
void initme(void);
void mmusetramsize(paddr_t size);
int mmuaddpage(ppc_map_info_t *info, int count);
void mmudelpage(ppc_map_info_t *info, int count);
void mmugetpage(ppc_map_info_t *info, int count);
void mmusetvsid(int start, int end, int vsid);
void *allocvsid(int);
void mmuallocvsid(int vsid, int mask);
void freevsid(int);
void mmufreevsid(int vsid, int mask);
int mmunitest(void);
void callkernel(void *fun_ptr, void *arg);

23
sdk/lib/ppcmmu/mmutest.c
View file

@ -1,23 +0,0 @@
#include "ppcmmu/mmu.h"
#include "ppcmmu/mmuutil.h"
#include "mmuobject.h"
int mmunitest()
{
int ret;
int (*fun)(int ret) = (void *)0x80000000;
ppc_map_info_t info = { 0 };
volatile int oldmsr, msr = 0x2030;
__asm__("mfmsr 0\n\tstw 0,0(%0)" : : "r" (&oldmsr));
mmusetvsid(8, 9, 0);
info.flags = MMU_ALL_RW;
info.proc = 0;
info.addr = (vaddr_t)fun;
mmuaddpage(&info, 1);
__asm__("mtmsr %0" : : "r" (msr));
__asm__("mtsdr1 %0" : : "r" (HTABORG));
*((int *)fun) = 0x4e800020;
ret = fun(3);
__asm__("mtmsr %0" : : "r" (oldmsr));
return ret != 3;
}

411
sdk/lib/ppcmmu/mmuutil.c
View file

@ -1,411 +0,0 @@
#include "ppcmmu/mmu.h"
#include "ppcmmu/mmuutil.h"
inline int GetMSR() {
register int res asm ("r3");
__asm__("mfmsr 3");
return res;
}
inline int GetDEC() {
register int res asm ("r3");
__asm__("mfdec 3");
return res;
}
__asm__("\t.globl GetPhys\n"
"GetPhys:\t\n"
"mflr 0\n\t"
"stwu 0,-16(1)\n\t"
"mfmsr 5\n\t"
"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
"mtmsr 6\n\t"
"isync\n\t"
"sync\n\t"
"lwz 3,0(3)\n\t" /* Get actual value at phys addr r3 */
"mtmsr 5\n\t"
"isync\n\t"
"sync\n\t"
"lwz 0,0(1)\n\t"
"addi 1,1,16\n\t"
"mtlr 0\n\t"
"blr"
);
__asm__("\t.globl GetPhysHalf\n"
"GetPhysHalf:\t\n"
"mflr 0\n\t"
"stwu 0,-16(1)\n\t"
"mfmsr 5\n\t"
"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
"mtmsr 6\n\t"
"isync\n\t"
"sync\n\t"
"lhz 3,0(3)\n\t" /* Get actual value at phys addr r3 */
"mtmsr 5\n\t"
"isync\n\t"
"sync\n\t"
"lwz 0,0(1)\n\t"
"addi 1,1,16\n\t"
"mtlr 0\n\t"
"blr"
);
__asm__("\t.globl GetPhysByte\n"
"GetPhysByte:\t\n"
"mflr 0\n\t"
"stwu 0,-16(1)\n\t"
"mfmsr 5\n\t"
"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
"mtmsr 6\n\t"
"isync\n\t"
"sync\n\t"
"lbz 3,0(3)\n\t" /* Get actual value at phys addr r3 */
"mtmsr 5\n\t"
"isync\n\t"
"sync\n\t"
"lwz 0,0(1)\n\t"
"addi 1,1,16\n\t"
"mtlr 0\n\t"
"blr"
);
__asm__("\t.globl SetPhys\n"
"SetPhys:\t\n"
"mflr 0\n\t"
"stwu 0,-16(1)\n\t"
"mfmsr 5\n\t"
"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
"mtmsr 6\n\t"
"sync\n\t"
"eieio\n\t"
"stw 4,0(3)\n\t" /* Set actual value at phys addr r3 */
"dcbst 0,3\n\t"
"mtmsr 5\n\t"
"sync\n\t"
"eieio\n\t"
"mr 3,4\n\t"
"lwz 0,0(1)\n\t"
"addi 1,1,16\n\t"
"mtlr 0\n\t"
"blr"
);
__asm__("\t.globl SetPhysHalf\n"
"SetPhysHalf:\t\n"
"mflr 0\n\t"
"stwu 0,-16(1)\n\t"
"mfmsr 5\n\t"
"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
"mtmsr 6\n\t"
"sync\n\t"
"eieio\n\t"
"sth 4,0(3)\n\t" /* Set actual value at phys addr r3 */
"dcbst 0,3\n\t"
"mtmsr 5\n\t"
"sync\n\t"
"eieio\n\t"
"mr 3,4\n\t"
"lwz 0,0(1)\n\t"
"addi 1,1,16\n\t"
"mtlr 0\n\t"
"blr"
);
__asm__("\t.globl SetPhysByte\n"
"SetPhysByte:\t\n"
"mflr 0\n\t"
"stwu 0,-16(1)\n\t"
"mfmsr 5\n\t"
"andi. 6,5,0xffef\n\t"/* turn off MSR[DR] */
"mtmsr 6\n\t"
"sync\n\t"
"eieio\n\t"
"stb 4,0(3)\n\t" /* Set actual value at phys addr r3 */
"dcbst 0,3\n\t"
"mtmsr 5\n\t"
"sync\n\t"
"eieio\n\t"
"mr 3,4\n\t"
"lwz 0,0(1)\n\t"
"addi 1,1,16\n\t"
"mtlr 0\n\t"
"blr"
);
inline int GetSR(int n) {
register int res = 0;
switch( n ) {
case 0:
__asm__("mfsr %0,0" : "=r" (res));
break;
case 1:
__asm__("mfsr %0,1" : "=r" (res));
break;
case 2:
__asm__("mfsr %0,2" : "=r" (res));
break;
case 3:
__asm__("mfsr %0,3" : "=r" (res));
break;
case 4:
__asm__("mfsr %0,4" : "=r" (res));
break;
case 5:
__asm__("mfsr %0,5" : "=r" (res));
break;
case 6:
__asm__("mfsr %0,6" : "=r" (res));
break;
case 7:
__asm__("mfsr %0,7" : "=r" (res));
break;
case 8:
__asm__("mfsr %0,8" : "=r" (res));
break;
case 9:
__asm__("mfsr %0,9" : "=r" (res));
break;
case 10:
__asm__("mfsr %0,10" : "=r" (res));
break;
case 11:
__asm__("mfsr %0,11" : "=r" (res));
break;
case 12:
__asm__("mfsr %0,12" : "=r" (res));
break;
case 13:
__asm__("mfsr %0,13" : "=r" (res));
break;
case 14:
__asm__("mfsr %0,14" : "=r" (res));
break;
case 15:
__asm__("mfsr %0,15" : "=r" (res));
break;
}
return res;
}
inline void SetSR(int n, int val) {
switch( n ) {
case 0:
__asm__("mtsr 0,%0" : : "r" (val));
break;
case 1:
__asm__("mtsr 1,%0" : : "r" (val));
break;
case 2:
__asm__("mtsr 2,%0" : : "r" (val));
break;
case 3:
__asm__("mtsr 3,%0" : : "r" (val));
break;
case 4:
__asm__("mtsr 4,%0" : : "r" (val));
break;
case 5:
__asm__("mtsr 5,%0" : : "r" (val));
break;
case 6:
__asm__("mtsr 6,%0" : : "r" (val));
break;
case 7:
__asm__("mtsr 7,%0" : : "r" (val));
break;
case 8:
__asm__("mtsr 8,%0" : : "r" (val));
break;
case 9:
__asm__("mtsr 9,%0" : : "r" (val));
break;
case 10:
__asm__("mtsr 10,%0" : : "r" (val));
break;
case 11:
__asm__("mtsr 11,%0" : : "r" (val));
break;
case 12:
__asm__("mtsr 12,%0" : : "r" (val));
break;
case 13:
__asm__("mtsr 13,%0" : : "r" (val));
break;
case 14:
__asm__("mtsr 14,%0" : : "r" (val));
break;
case 15:
__asm__("mtsr 15,%0" : : "r" (val));
break;
}
}
void GetBat( int bat, int inst, int *batHi, int *batLo ) {
register int bh asm("r3"), bl asm("r4");
if( inst ) {
switch( bat ) {
case 0:
__asm__("mfibatu 3,0");
__asm__("mfibatl 4,0");
break;
case 1:
__asm__("mfibatu 3,1");
__asm__("mfibatl 4,1");
break;
case 2:
__asm__("mfibatu 3,2");
__asm__("mfibatl 4,2");
break;
case 3:
__asm__("mfibatu 3,3");
__asm__("mfibatl 4,3");
break;
}
} else {
switch( bat ) {
case 0:
__asm__("mfdbatu 3,0");
__asm__("mfdbatl 4,0");
break;
case 1:
__asm__("mfdbatu 3,1");
__asm__("mfdbatl 4,1");
break;
case 2:
__asm__("mfdbatu 3,2");
__asm__("mfdbatl 4,2");
break;
case 3:
__asm__("mfdbatu 3,3");
__asm__("mfdbatl 4,3");
break;
}
}
*batHi = bh;
*batLo = bl;
}
#define BATSET(n,t) \
case n: __asm__("mt" #t "batu " #n ",%0\n\tmt" #t "batl " #n ",%1" \
: : "r" (batHi), "r" (batLo)); break;
void SetBat( int bat, int inst, int batHi, int batLo ) {
if( inst ) {
switch( bat ) {
BATSET(0,i);
BATSET(1,i);
BATSET(2,i);
BATSET(3,i);
}
} else {
switch( bat ) {
BATSET(0,d);
BATSET(1,d);
BATSET(2,d);
BATSET(3,d);
}
}
__asm__("isync\n\tsync");
}
inline int GetSDR1() {
register int res asm("r3");
__asm__("mfsdr1 3");
return res;
}
inline void SetSDR1( int sdr ) {
int i,j;
__asm__("mtsdr1 3");
__asm__("sync");
__asm__("isync");
for( i = 0; i < 256; i++ ) {
j = i << 12;
__asm__("tlbie %0,0" : : "r" (j));
}
__asm__("eieio");
__asm__("tlbsync");
__asm__("ptesync");
}
inline int BatTranslate( int batu, int batl, int virt ) {
int mask;
if(batu & 0x3fc)
{
mask = ~(0x1ffff | ((batu & 0x3fc)>>2)<<17);
if((batu & 2) && ((batu & mask) == (virt & mask)))
return (batl & mask) | (virt & ~mask);
} else {
mask = ~(0x1ffff | (batl << 17));
if(!(batl & 0x40) || ((batu & mask) != (virt & mask)))
return (batl & mask) | (virt & ~mask);
}
return -1;
}
inline int BatHit( int batu, int batl, int virt ) {
return BatTranslate( batu, batl, virt ) != -1;
}
/* translate address */
int PpcVirt2phys( vaddr_t virt, int inst ) {
int msr = GetMSR();
int txmask = inst ? 0x20 : 0x10;
int i, bath, batl, sr, sdr1, physbase, vahi, valo;
int npteg, hash, hashmask, ptehi, ptelo, ptegaddr;
int vsid, pteh, ptevsid, pteapi;
if( msr & txmask ) {
sr = GetSR( virt >> 28 );
vsid = sr & 0xfffffff;
vahi = vsid >> 4;
valo = (vsid << 28) | (virt & 0xfffffff);
if( sr & 0x80000000 ) {
return valo;
}
for( i = 0; i < 4; i++ ) {
GetBat( i, inst, &bath, &batl );
if( BatHit( bath, batl, virt ) ) {
return BatTranslate( bath, batl, virt );
}
}
sdr1 = GetSDR1();
physbase = sdr1 & ~0xffff;
hashmask = ((sdr1 & 0x1ff) << 10) | 0x3ff;
hash = (vsid & 0x7ffff) ^ ((valo >> 12) & 0xffff);
npteg = hashmask + 1;
for( pteh = 0; pteh < 0x80; pteh += 64, hash ^= 0x7ffff ) {
ptegaddr = ((hashmask & hash) * 64) + physbase;
for( i = 0; i < 8; i++ ) {
ptehi = GetPhys( ptegaddr + (i * 8) );
ptelo = GetPhys( ptegaddr + (i * 8) + 4 );
ptevsid = (ptehi >> 7) & 0xffffff;
pteapi = ptehi & 0x3f;
if( (ptehi & 64) != pteh ) continue;
if( ptevsid != (vsid & 0xffffff) ) continue;
if( pteapi != ((virt >> 22) & 0x3f) ) continue;
return (ptelo & 0xfffff000) | (virt & 0xfff);
}
}
return -1;
} else {
return virt;
}
}
int PtegNumber(vaddr_t virt, int hfun)
{
int sr = GetSR( (virt >> 28) & 0xf );
int vsid = sr & PPC_VSID_MASK;
return ((((vsid & 0x7ffff) ^ ((virt >> 12) & 0xffff)) ^ (hfun ? -1 : 0)) & ((HTABSIZ - 1) >> 3) & 0x3ff);
}

2
sdk/lib/pseh/CMakeLists.txt
View file

@ -43,8 +43,6 @@ else()
i386/framebased-gcchack-asm.S)
elseif(ARCH STREQUAL "amd64")
list(APPEND SOURCE amd64/framebased.S)
elseif(ARCH STREQUAL "powerpc")
list(APPEND SOURCE powerpc/framebased.S)
endif()
add_library(pseh ${SOURCE} ${ASM_SOURCE})

69
sdk/lib/pseh/powerpc/framebased.S
View file

@ -1,69 +0,0 @@
// Copyright (c) 2004/2005 KJK::Hyperion
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to dos so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
.text
.globl _SEHCleanHandlerEnvironment
_SEHCleanHandlerEnvironment:
blr
.globl _SEHCurrentRegistration
_SEHCurrentRegistration:
lwz 3,0(13)
blr
// R3: Frame to store in
.globl _SEHRegisterFrame
_SEHRegisterFrame:
lwz 4,0(13)
stw 3,0(13)
stw 4,0(3)
blr
.globl _SEHUnregisterFrame
_SEHUnregisterFrame:
lwz 3,0(13)
lwz 3,0(3)
stw 3,0(13)
blr
.globl _SEHGlobalUnwind
_SEHGlobalUnwind:
.extern _SEHRtlUnwind
// RtlUnwind clobbers all the "don't clobber" registers, so we save them
lwz 3,4(1)
stwu 1,-132(1)
stmw 2,-128(1)
xor 6,6,6
xor 5,5,5
lis 4,.RestoreRegisters@ha
addi 4,4,.RestoreRegisters@l # Where to jump back to
# We already have r3
bl _SEHRtlUnwind
.RestoreRegisters:
lmw 2,-128(1)
addi 1,1,132
blr
// EOF

10
sdk/lib/rtl/CMakeLists.txt
View file

@ -104,16 +104,6 @@ elseif(ARCH STREQUAL "arm")
arm/except.c
byteswap.c
mem.c)
elseif(ARCH STREQUAL "powerpc")
list(APPEND ASM_SOURCE
powerpc/rtlmem.s
powerpc/rtlswap.s)
list(APPEND SOURCE
byteswap.c
powerpc/debug.c
powerpc/except.c
powerpc/interlocked.c
powerpc/thread.c)
endif()
add_asm_files(rtl_asm ${ASM_SOURCE})

41
sdk/lib/rtl/powerpc/debug.c
View file

@ -1,41 +0,0 @@
#include <ntddk.h>
#include <winddk.h>
NTKERNELAPI
VOID
DbgBreakPoint() { __asm__("ti 31,0,0"); }
NTKERNELAPI
VOID
DbgBreakPointWithStatus(ULONG Status) { __asm__("ti 31,0,0"); }
ULONG
NTAPI
DebugService
(ULONG Service, PVOID Argument1, PVOID Argument1, PVOID Argument3, PVOID Argument4)
{
ULONG Result;
__asm__("mr 0,%1\n\t"
"mr 3,%2\n\t"
"mr 4,%3\n\t"
"mr 5,%4\n\t"
"mr 6,%5\n\t"
"mr 7,%6\n\t"
"sc\n\t"
"mr %0,3\n\t" :
"=r" (Result) :
"r" (0x10000),
"r" (Service),
"r" (Argument1),
"r" (Argument2),
"r" (Argument3),
"r" (Argument4) );
return Result;
}
VOID
NTAPI
DebugService2
(PVOID Arg1, PVOID Arg2, ULONG Service)
{
}

54
sdk/lib/rtl/powerpc/except.c
View file

@ -1,54 +0,0 @@
/* COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS Runtime Library
* PURPOSE: User-Mode Exception Support
* FILE: lib/rtl/powerpc/except.c
* PROGRAMERS: Alex Ionescu (alex@relsoft.net)
* David Welch <welch@cwcom.net>
* Skywing <skywing@valhallalegends.com>
* KJK::Hyperion <noog@libero.it>
*/
/* INCLUDES *****************************************************************/
#include <rtl.h>
#define NDEBUG
#include <debug.h>
NTSYSAPI
VOID
NTAPI
RtlCaptureContext
(OUT PCONTEXT ContextRecord)
{
// XXX arty fixme
}
NTSYSAPI
BOOLEAN
NTAPI
RtlDispatchException
(IN PEXCEPTION_RECORD ExceptionRecord,
IN PCONTEXT Context)
{
// XXX arty fixme
return TRUE;
}
VOID
NTAPI
RtlUnwind(IN PVOID TargetFrame OPTIONAL,
IN PVOID TargetIp OPTIONAL,
IN PEXCEPTION_RECORD ExceptionRecord OPTIONAL,
IN PVOID ReturnValue)
{
// XXX arty fixme
}
NTSYSAPI
VOID
NTAPI
RtlGetCallersAddress(
OUT PVOID *CallersAddress,
OUT PVOID *CallersCaller)
{
}

128
sdk/lib/rtl/powerpc/interlocked.c
View file

@ -1,128 +0,0 @@
typedef unsigned int size_t;
#include <ntddk.h>
#include <winddk.h>
#include <string.h>
#include <intrin.h>
NTKERNELAPI
LONG
FASTCALL
InterlockedExchange(
LONG volatile *Target, LONG Value)
{
return _InterlockedExchange(Target, Value);
}
NTKERNELAPI
LONG
FASTCALL
InterlockedExchangeAdd(
LONG volatile *Target, LONG Value)
{
return _InterlockedExchangeAdd(Target, Value);
}
NTKERNELAPI
LONG
WINAPI
InterlockedCompareExchange(
LONG volatile *Destination,
LONG Exchange, LONG Comparand)
{
return _InterlockedCompareExchange(Destination, Exchange, Comparand);
}
NTKERNELAPI
LONG
FASTCALL
InterlockedIncrement
(IN OUT LONG volatile *Addend)
{
return _InterlockedIncrement(Addend);
}
NTKERNELAPI
LONG
FASTCALL
InterlockedDecrement(
IN OUT LONG volatile *Addend)
{
return _InterlockedDecrement(Addend);
}
PSLIST_ENTRY
WINAPI
InterlockedPopEntrySList(
PSLIST_HEADER ListHead)
{
PSLIST_ENTRY Result = NULL;
KIRQL OldIrql;
static BOOLEAN GLLInit = FALSE;
static KSPIN_LOCK GlobalListLock;
if(!GLLInit)
{
KeInitializeSpinLock(&GlobalListLock);
GLLInit = TRUE;
}
KeAcquireSpinLock(&GlobalListLock, &OldIrql);
if(ListHead->Next.Next)
{
Result = ListHead->Next.Next;
ListHead->Next.Next = Result->Next;
}
KeReleaseSpinLock(&GlobalListLock, OldIrql);
return Result;
}
NTKERNELAPI
PSLIST_ENTRY
FASTCALL
InterlockedPushEntrySList(
IN PSLIST_HEADER ListHead,
IN PSLIST_ENTRY ListEntry)
{
PVOID PrevValue;
do
{
PrevValue = ListHead->Next.Next;
ListEntry->Next = PrevValue;
}
while (InterlockedCompareExchangePointer(&ListHead->Next.Next,
ListEntry,
PrevValue) != PrevValue);
return (PSLIST_ENTRY)PrevValue;
}
NTKERNELAPI
VOID
FASTCALL
ExInterlockedAddLargeStatistic(
IN PLARGE_INTEGER Addend,
IN ULONG Increment)
{
_InterlockedAddLargeStatistic(&Addend->QuadPart, Increment);
}
NTKERNELAPI
LONGLONG
FASTCALL
ExInterlockedCompareExchange64(
IN OUT PLONGLONG Destination,
IN PLONGLONG Exchange,
IN PLONGLONG Comparand,
IN PKSPIN_LOCK Lock)
{
KIRQL OldIrql;
LONGLONG Result;
KeAcquireSpinLock(Lock, &OldIrql);
Result = *Destination;
if(*Destination == Result)
*Destination = *Exchange;
KeReleaseSpinLock(Lock, OldIrql);
return Result;
}

101
sdk/lib/rtl/powerpc/rtlmem.s
View file

@ -1,101 +0,0 @@
/*
*
*/
.globl RtlCompareMemory
.globl RtlCompareMemoryUlong
.globl RtlFillMemory
.globl RtlFillMemoryUlong
.globl RtlFillMemoryUlonglong
.globl RtlMoveMemory
.globl RtlZeroMemory
RtlCompareMemory:
1:
mr 0,5
cmpwi 0,5,4
blt 2f
lwz 6,0(3)
lwz 7,0(3)
addi 6,6,-7
cmpwi 0,6,0
bne 2f
addi 3,3,4
addi 4,4,4
subi 5,5,4
b 1b
2:
cmpwi 0,5,0
beq 3f
lbz 6,0(3)
lbz 7,0(4)
addi 6,6,-7
cmpwi 0,6,0
bne 3f
addi 3,3,1
addi 4,4,1
subi 5,5,1
b 2b
3:
mr 4,0
sub 3,4,5
blr
RtlCompareMemoryUlong:
or 6,3,4
or 6,6,5
andi. 6,6,3
bne RtlCompareMemory
xor 3,3,3
blr
RtlFillMemory:
rlwinm 6,5,8,0xff00
rlwinm 7,5,0,0xff
or 7,6,7
rlwinm 5,7,16,0xffff0000
or 5,7,5
1:
cmpwi 0,4,4
blt 2f
stw 5,0(3)
addi 3,3,4
subi 4,4,4
b 1b
2:
cmpwi 0,4,0
beq 3f
stb 5,0(3)
addi 3,3,1
subi 4,4,1
b 2b
3:
blr
RtlFillMemoryUlong:
b RtlFillMemory
RtlFillMemoryUlonglong:
b RtlFillMemoryUlong
RtlMoveMemory:
b memmove
RtlZeroMemory:
mr 5,4
xor 4,4,4
b memset

41
sdk/lib/rtl/powerpc/rtlswap.s
View file

@ -1,41 +0,0 @@
/*
* COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS Run-Time Library
* PURPOSE: Byte swap functions
* FILE: lib/rtl/powerpc/rtlswap.s
* PROGRAMER: Alex Ionescu (alex.ionescu@reactos.org)
*/
.globl RtlUshortByteSwap
.globl RtlUlongByteSwap
.globl RtlUlonglongByteSwap
/* FUNCTIONS ***************************************************************/
RtlUshortByteSwap:
/* Swap high and low bits */
rlwinm 4,3,24,0xff
rlwinm 5,3,8,0xff00
or 3,4,5
blr
RtlUlongByteSwap:
rlwinm 4,3,8,0xff
rlwinm 5,3,24,0xff000000
or 4,4,5
rlwinm 5,3,8,0xff0000
rlwinm 3,3,24,0xff00
or 3,4,5
or 3,3,6
blr
RtlUlonglongByteSwap:
stwu 1,16(1)
stw 4,4(1)
bl RtlUlongByteSwap
stw 3,4(1)
lwz 3,4(1)
bl RtlUlongByteSwap
lwz 4,4(1)
subi 1,1,16
blr

38
sdk/lib/rtl/powerpc/thread.c
View file

@ -1,38 +0,0 @@
/*
* COPYRIGHT: See COPYING in the top level directory
* PROJECT: ReactOS system libraries
* PURPOSE: Rtl user thread functions
* FILE: lib/rtl/powerpc/thread.c
* PROGRAMERS:
* Alex Ionescu (alex@relsoft.net)
* Eric Kohl
* KJK::Hyperion
*/
/* INCLUDES *****************************************************************/
#include <rtl.h>
#include "i386/ketypes.h"
#define NDEBUG
#include <debug.h>
/* PRIVATE FUNCTIONS *******************************************************/
/*
* @implemented
*/
VOID
NTAPI
RtlInitializeContext(IN HANDLE ProcessHandle,
OUT PCONTEXT ThreadContext,
IN PVOID ThreadStartParam OPTIONAL,
IN PTHREAD_START_ROUTINE ThreadStartAddress,
IN PINITIAL_TEB InitialTeb)
{
DPRINT("RtlInitializeContext: (hProcess: %p, ThreadContext: %p, Teb: %p\n",
ProcessHandle, ThreadContext, InitialTeb);
// XXX arty fixme
}
/* EOF */