mirror of
https://github.com/reactos/reactos.git
synced 2024-09-03 09:09:19 +00:00
Moved/added some declarations
Fixed ide drive identification svn path=/trunk/; revision=2329
This commit is contained in:
parent
af347caa8c
commit
6d21eb028c
|
@ -1,4 +1,4 @@
|
||||||
/* $Id: ide.c,v 1.45 2001/09/09 21:28:05 ekohl Exp $
|
/* $Id: ide.c,v 1.46 2001/11/01 00:28:57 ekohl Exp $
|
||||||
*
|
*
|
||||||
* IDE.C - IDE Disk driver
|
* IDE.C - IDE Disk driver
|
||||||
* written by Rex Jolliff
|
* written by Rex Jolliff
|
||||||
|
@ -81,48 +81,6 @@
|
||||||
|
|
||||||
// ------------------------------------------------------- File Static Data
|
// ------------------------------------------------------- File Static Data
|
||||||
|
|
||||||
#define PCI_TYPE0_ADDRESSES 6
|
|
||||||
#define PCI_TYPE1_ADDRESSES 2
|
|
||||||
|
|
||||||
typedef struct _PCI_COMMON_CONFIG
|
|
||||||
{
|
|
||||||
USHORT VendorID; // (ro)
|
|
||||||
USHORT DeviceID; // (ro)
|
|
||||||
USHORT Command; // Device control
|
|
||||||
USHORT Status;
|
|
||||||
UCHAR RevisionID; // (ro)
|
|
||||||
UCHAR ProgIf; // (ro)
|
|
||||||
UCHAR SubClass; // (ro)
|
|
||||||
UCHAR BaseClass; // (ro)
|
|
||||||
UCHAR CacheLineSize; // (ro+)
|
|
||||||
UCHAR LatencyTimer; // (ro+)
|
|
||||||
UCHAR HeaderType; // (ro)
|
|
||||||
UCHAR BIST; // Built in self test
|
|
||||||
|
|
||||||
union
|
|
||||||
{
|
|
||||||
struct _PCI_HEADER_TYPE_0
|
|
||||||
{
|
|
||||||
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
|
|
||||||
ULONG CIS;
|
|
||||||
USHORT SubVendorID;
|
|
||||||
USHORT SubSystemID;
|
|
||||||
ULONG ROMBaseAddress;
|
|
||||||
ULONG Reserved2[2];
|
|
||||||
|
|
||||||
UCHAR InterruptLine; //
|
|
||||||
UCHAR InterruptPin; // (ro)
|
|
||||||
UCHAR MinimumGrant; // (ro)
|
|
||||||
UCHAR MaximumLatency; // (ro)
|
|
||||||
} type0;
|
|
||||||
|
|
||||||
|
|
||||||
} u;
|
|
||||||
|
|
||||||
UCHAR DeviceSpecific[192];
|
|
||||||
|
|
||||||
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct _IDE_CONTROLLER_PARAMETERS
|
typedef struct _IDE_CONTROLLER_PARAMETERS
|
||||||
{
|
{
|
||||||
|
@ -645,6 +603,7 @@ IDEResetController(IN WORD CommandPort,
|
||||||
return IDEReadError(CommandPort) == 1;
|
return IDEReadError(CommandPort) == 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
// IDECreateDevices
|
// IDECreateDevices
|
||||||
//
|
//
|
||||||
// DESCRIPTION:
|
// DESCRIPTION:
|
||||||
|
@ -683,7 +642,6 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
|
||||||
PDEVICE_OBJECT DiskDeviceObject;
|
PDEVICE_OBJECT DiskDeviceObject;
|
||||||
PDEVICE_OBJECT PartitionDeviceObject;
|
PDEVICE_OBJECT PartitionDeviceObject;
|
||||||
PIDE_DEVICE_EXTENSION DiskDeviceExtension;
|
PIDE_DEVICE_EXTENSION DiskDeviceExtension;
|
||||||
// PIDE_DEVICE_EXTENSION PartitionDeviceExtension;
|
|
||||||
UNICODE_STRING UnicodeDeviceDirName;
|
UNICODE_STRING UnicodeDeviceDirName;
|
||||||
OBJECT_ATTRIBUTES DeviceDirAttributes;
|
OBJECT_ATTRIBUTES DeviceDirAttributes;
|
||||||
HANDLE Handle;
|
HANDLE Handle;
|
||||||
|
@ -703,7 +661,8 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
|
||||||
/* Get the Drive Identification Data */
|
/* Get the Drive Identification Data */
|
||||||
if (!IDEGetDriveIdentification(CommandPort, DriveIdx, &DrvParms))
|
if (!IDEGetDriveIdentification(CommandPort, DriveIdx, &DrvParms))
|
||||||
{
|
{
|
||||||
DPRINT("Giving up on drive %d on controller %d...\n",
|
CHECKPOINT1;
|
||||||
|
DbgPrint("Giving up on drive %d on controller %d...\n",
|
||||||
DriveIdx,
|
DriveIdx,
|
||||||
ControllerExtension->Number);
|
ControllerExtension->Number);
|
||||||
return FALSE;
|
return FALSE;
|
||||||
|
@ -756,10 +715,6 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
|
||||||
/* Increase number of available physical disk drives */
|
/* Increase number of available physical disk drives */
|
||||||
IoGetConfigurationInformation()->DiskCount++;
|
IoGetConfigurationInformation()->DiskCount++;
|
||||||
|
|
||||||
/* Initialize device extension for the disk device */
|
|
||||||
// DiskDeviceExtension = (PIDE_DEVICE_EXTENSION)DiskDeviceObject->DeviceExtension;
|
|
||||||
// DiskDeviceExtension->DiskExtension = (PVOID)DiskDeviceExtension;
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Initialize the controller timer here
|
* Initialize the controller timer here
|
||||||
* (since it has to be tied to a device)
|
* (since it has to be tied to a device)
|
||||||
|
@ -809,18 +764,11 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
|
||||||
HarddiskIdx,
|
HarddiskIdx,
|
||||||
&DrvParms,
|
&DrvParms,
|
||||||
PartitionEntry);
|
PartitionEntry);
|
||||||
// PartitionEntry->PartitionNumber,
|
|
||||||
// PartitionEntry->StartingOffset.QuadPart / 512 /* DrvParms.BytesPerSector*/,
|
|
||||||
// PartitionEntry->PartitionLength.QuadPart / 512 /*DrvParms.BytesPerSector*/);
|
|
||||||
if (!NT_SUCCESS(Status))
|
if (!NT_SUCCESS(Status))
|
||||||
{
|
{
|
||||||
DbgPrint("IDECreateDevice() failed\n");
|
DbgPrint("IDECreateDevice() failed\n");
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Initialize pointer to disk device extension */
|
|
||||||
// PartitionDeviceExtension = (PIDE_DEVICE_EXTENSION)PartitionDeviceObject->DeviceExtension;
|
|
||||||
// PartitionDeviceExtension->DiskExtension = (PVOID)DiskDeviceExtension;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (PartitionList != NULL)
|
if (PartitionList != NULL)
|
||||||
|
@ -856,6 +804,7 @@ IDEGetDriveIdentification(IN int CommandPort,
|
||||||
if (IDEPolledRead(CommandPort, 0, 0, 0, 0, 0, (DriveNum ? IDE_DH_DRV1 : 0),
|
if (IDEPolledRead(CommandPort, 0, 0, 0, 0, 0, (DriveNum ? IDE_DH_DRV1 : 0),
|
||||||
IDE_CMD_IDENT_DRV, (BYTE *)DrvParms) != 0)
|
IDE_CMD_IDENT_DRV, (BYTE *)DrvParms) != 0)
|
||||||
{
|
{
|
||||||
|
CHECKPOINT1;
|
||||||
return FALSE;
|
return FALSE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1045,9 +994,6 @@ IDECreatePartitionDevice(IN PDRIVER_OBJECT DriverObject,
|
||||||
IN ULONG DiskNumber,
|
IN ULONG DiskNumber,
|
||||||
IN PIDE_DRIVE_IDENTIFY DrvParms,
|
IN PIDE_DRIVE_IDENTIFY DrvParms,
|
||||||
IN PPARTITION_INFORMATION PartitionInfo)
|
IN PPARTITION_INFORMATION PartitionInfo)
|
||||||
// IN ULONG PartitionNumber,
|
|
||||||
// IN ULONGLONG Offset,
|
|
||||||
// IN ULONGLONG Size)
|
|
||||||
{
|
{
|
||||||
WCHAR NameBuffer[IDE_MAX_NAME_LENGTH];
|
WCHAR NameBuffer[IDE_MAX_NAME_LENGTH];
|
||||||
WCHAR ArcNameBuffer[IDE_MAX_NAME_LENGTH + 15];
|
WCHAR ArcNameBuffer[IDE_MAX_NAME_LENGTH + 15];
|
||||||
|
@ -1157,7 +1103,7 @@ static int
|
||||||
IDEPolledRead(IN WORD Address,
|
IDEPolledRead(IN WORD Address,
|
||||||
IN BYTE PreComp,
|
IN BYTE PreComp,
|
||||||
IN BYTE SectorCnt,
|
IN BYTE SectorCnt,
|
||||||
IN BYTE SectorNum ,
|
IN BYTE SectorNum,
|
||||||
IN BYTE CylinderLow,
|
IN BYTE CylinderLow,
|
||||||
IN BYTE CylinderHigh,
|
IN BYTE CylinderHigh,
|
||||||
IN BYTE DrvHead,
|
IN BYTE DrvHead,
|
||||||
|
@ -1171,7 +1117,8 @@ IDEPolledRead(IN WORD Address,
|
||||||
for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
|
for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
|
||||||
{
|
{
|
||||||
Status = IDEReadStatus(Address);
|
Status = IDEReadStatus(Address);
|
||||||
if (!(Status & IDE_SR_BUSY))
|
if (!(Status & IDE_SR_BUSY) && !(Status & IDE_SR_DRQ))
|
||||||
|
// if (!(Status & IDE_SR_BUSY))
|
||||||
{
|
{
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -1185,11 +1132,11 @@ IDEPolledRead(IN WORD Address,
|
||||||
/* Write Drive/Head to select drive */
|
/* Write Drive/Head to select drive */
|
||||||
IDEWriteDriveHead(Address, IDE_DH_FIXED | DrvHead);
|
IDEWriteDriveHead(Address, IDE_DH_FIXED | DrvHead);
|
||||||
|
|
||||||
/* Wait for STATUS.BUSY to clear and STATUS.DRDY to assert */
|
/* Wait for STATUS.BUSY and STATUS.DRQ to clear */
|
||||||
for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
|
for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
|
||||||
{
|
{
|
||||||
Status = IDEReadStatus(Address);
|
Status = IDEReadStatus(Address);
|
||||||
if (!(Status & IDE_SR_BUSY) && (Status & IDE_SR_DRDY))
|
if (!(Status & IDE_SR_BUSY) && !(Status & IDE_SR_DRQ))
|
||||||
{
|
{
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -1197,6 +1144,7 @@ IDEPolledRead(IN WORD Address,
|
||||||
}
|
}
|
||||||
if (RetryCount == IDE_MAX_BUSY_RETRIES)
|
if (RetryCount == IDE_MAX_BUSY_RETRIES)
|
||||||
{
|
{
|
||||||
|
CHECKPOINT1;
|
||||||
return IDE_ER_ABRT;
|
return IDE_ER_ABRT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1235,22 +1183,20 @@ IDEPolledRead(IN WORD Address,
|
||||||
|
|
||||||
while (1)
|
while (1)
|
||||||
{
|
{
|
||||||
|
/* wait for DRQ or error */
|
||||||
// wait for DRQ or error
|
|
||||||
for (RetryCount = 0; RetryCount < IDE_MAX_POLL_RETRIES; RetryCount++)
|
for (RetryCount = 0; RetryCount < IDE_MAX_POLL_RETRIES; RetryCount++)
|
||||||
{
|
{
|
||||||
Status = IDEReadStatus(Address);
|
Status = IDEReadStatus(Address);
|
||||||
if (!(Status & IDE_SR_BUSY))
|
if (!(Status & IDE_SR_BUSY))
|
||||||
{
|
{
|
||||||
if (Status & IDE_SR_ERR)
|
if (Status & IDE_SR_DRQ)
|
||||||
{
|
|
||||||
BYTE Err = IDEReadError(Address);
|
|
||||||
return Err;
|
|
||||||
}
|
|
||||||
else if (Status & IDE_SR_DRQ)
|
|
||||||
{
|
{
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return IDE_ER_ABRT;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
KeStallExecutionProcessor(10);
|
KeStallExecutionProcessor(10);
|
||||||
}
|
}
|
||||||
|
@ -1259,19 +1205,27 @@ IDEPolledRead(IN WORD Address,
|
||||||
return IDE_ER_ABRT;
|
return IDE_ER_ABRT;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Read data into buffer
|
/* Read data into buffer */
|
||||||
IDEReadBlock(Address, Buffer, IDE_SECTOR_BUF_SZ);
|
IDEReadBlock(Address, Buffer, IDE_SECTOR_BUF_SZ);
|
||||||
Buffer += IDE_SECTOR_BUF_SZ;
|
Buffer += IDE_SECTOR_BUF_SZ;
|
||||||
|
|
||||||
// Check for more sectors to read
|
/* Check for more sectors to read */
|
||||||
for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES &&
|
for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
|
||||||
(IDEReadStatus(Address) & IDE_SR_DRQ); RetryCount++)
|
{
|
||||||
;
|
Status = IDEReadStatus(Address);
|
||||||
if (!(IDEReadStatus(Address) & IDE_SR_BUSY))
|
if (!(Status & IDE_SR_BUSY))
|
||||||
|
{
|
||||||
|
if (Status & IDE_SR_DRQ)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
else
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// ------------------------------------------- Nondiscardable statics
|
// ------------------------------------------- Nondiscardable statics
|
||||||
|
|
|
@ -1,4 +1,4 @@
|
||||||
/* $Id: haltypes.h,v 1.2 2001/09/23 22:14:03 chorns Exp $
|
/* $Id: haltypes.h,v 1.3 2001/11/01 00:25:28 ekohl Exp $
|
||||||
*
|
*
|
||||||
* COPYRIGHT: See COPYING in the top level directory
|
* COPYRIGHT: See COPYING in the top level directory
|
||||||
* PROJECT: ReactOS kernel
|
* PROJECT: ReactOS kernel
|
||||||
|
@ -68,6 +68,166 @@ typedef struct _DEVICE_DESCRIPTION
|
||||||
} DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
|
} DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
|
||||||
|
|
||||||
|
|
||||||
|
/* PCI bus definitions */
|
||||||
|
|
||||||
|
#define PCI_TYPE0_ADDRESSES 6
|
||||||
|
#define PCI_TYPE1_ADDRESSES 2
|
||||||
|
#define PCI_TYPE2_ADDRESSES 5
|
||||||
|
|
||||||
|
typedef struct _PCI_COMMON_CONFIG
|
||||||
|
{
|
||||||
|
USHORT VendorID; /* read-only */
|
||||||
|
USHORT DeviceID; /* read-only */
|
||||||
|
USHORT Command;
|
||||||
|
USHORT Status;
|
||||||
|
UCHAR RevisionID; /* read-only */
|
||||||
|
UCHAR ProgIf; /* read-only */
|
||||||
|
UCHAR SubClass; /* read-only */
|
||||||
|
UCHAR BaseClass; /* read-only */
|
||||||
|
UCHAR CacheLineSize; /* read-only */
|
||||||
|
UCHAR LatencyTimer; /* read-only */
|
||||||
|
UCHAR HeaderType; /* read-only */
|
||||||
|
UCHAR BIST;
|
||||||
|
union
|
||||||
|
{
|
||||||
|
struct _PCI_HEADER_TYPE_0
|
||||||
|
{
|
||||||
|
ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
|
||||||
|
ULONG CIS;
|
||||||
|
USHORT SubVendorID;
|
||||||
|
USHORT SubSystemID;
|
||||||
|
ULONG ROMBaseAddress;
|
||||||
|
ULONG Reserved2[2];
|
||||||
|
|
||||||
|
UCHAR InterruptLine;
|
||||||
|
UCHAR InterruptPin; /* read-only */
|
||||||
|
UCHAR MinimumGrant; /* read-only */
|
||||||
|
UCHAR MaximumLatency; /* read-only */
|
||||||
|
} type0;
|
||||||
|
|
||||||
|
/* PCI to PCI Bridge */
|
||||||
|
struct _PCI_HEADER_TYPE_1
|
||||||
|
{
|
||||||
|
ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
|
||||||
|
UCHAR PrimaryBus;
|
||||||
|
UCHAR SecondaryBus;
|
||||||
|
UCHAR SubordinateBus;
|
||||||
|
UCHAR SecondaryLatency;
|
||||||
|
UCHAR IOBase;
|
||||||
|
UCHAR IOLimit;
|
||||||
|
USHORT SecondaryStatus;
|
||||||
|
USHORT MemoryBase;
|
||||||
|
USHORT MemoryLimit;
|
||||||
|
USHORT PrefetchBase;
|
||||||
|
USHORT PrefetchLimit;
|
||||||
|
ULONG PrefetchBaseUpper32;
|
||||||
|
ULONG PrefetchLimitUpper32;
|
||||||
|
USHORT IOBaseUpper16;
|
||||||
|
USHORT IOLimitUpper16;
|
||||||
|
UCHAR CapabilitiesPtr;
|
||||||
|
UCHAR Reserved1[3];
|
||||||
|
ULONG ROMBaseAddress;
|
||||||
|
UCHAR InterruptLine;
|
||||||
|
UCHAR InterruptPin;
|
||||||
|
USHORT BridgeControl;
|
||||||
|
} type1;
|
||||||
|
|
||||||
|
/* PCI to CARDBUS Bridge */
|
||||||
|
struct _PCI_HEADER_TYPE_2
|
||||||
|
{
|
||||||
|
ULONG SocketRegistersBaseAddress;
|
||||||
|
UCHAR CapabilitiesPtr;
|
||||||
|
UCHAR Reserved;
|
||||||
|
USHORT SecondaryStatus;
|
||||||
|
UCHAR PrimaryBus;
|
||||||
|
UCHAR SecondaryBus;
|
||||||
|
UCHAR SubordinateBus;
|
||||||
|
UCHAR SecondaryLatency;
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
ULONG Base;
|
||||||
|
ULONG Limit;
|
||||||
|
} Range[PCI_TYPE2_ADDRESSES-1];
|
||||||
|
UCHAR InterruptLine;
|
||||||
|
UCHAR InterruptPin;
|
||||||
|
USHORT BridgeControl;
|
||||||
|
} type2;
|
||||||
|
} u;
|
||||||
|
UCHAR DeviceSpecific[192];
|
||||||
|
} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
|
||||||
|
|
||||||
|
#define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
|
||||||
|
|
||||||
|
#define PCI_MAX_DEVICES 32
|
||||||
|
#define PCI_MAX_FUNCTION 8
|
||||||
|
|
||||||
|
#define PCI_INVALID_VENDORID 0xFFFF
|
||||||
|
|
||||||
|
|
||||||
|
/* Bit encodings for PCI_COMMON_CONFIG.HeaderType */
|
||||||
|
|
||||||
|
#define PCI_MULTIFUNCTION 0x80
|
||||||
|
#define PCI_DEVICE_TYPE 0x00
|
||||||
|
#define PCI_BRIDGE_TYPE 0x01
|
||||||
|
|
||||||
|
|
||||||
|
/* Bit encodings for PCI_COMMON_CONFIG.Command */
|
||||||
|
|
||||||
|
#define PCI_ENABLE_IO_SPACE 0x0001
|
||||||
|
#define PCI_ENABLE_MEMORY_SPACE 0x0002
|
||||||
|
#define PCI_ENABLE_BUS_MASTER 0x0004
|
||||||
|
#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
|
||||||
|
#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
|
||||||
|
#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
|
||||||
|
#define PCI_ENABLE_PARITY 0x0040
|
||||||
|
#define PCI_ENABLE_WAIT_CYCLE 0x0080
|
||||||
|
#define PCI_ENABLE_SERR 0x0100
|
||||||
|
#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200
|
||||||
|
|
||||||
|
|
||||||
|
/* Bit encodings for PCI_COMMON_CONFIG.Status */
|
||||||
|
|
||||||
|
#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080
|
||||||
|
#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
|
||||||
|
#define PCI_STATUS_DEVSEL 0x0600 /* 2 bits wide */
|
||||||
|
#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
|
||||||
|
#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
|
||||||
|
#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
|
||||||
|
#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
|
||||||
|
#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
|
||||||
|
|
||||||
|
|
||||||
|
/* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
|
||||||
|
|
||||||
|
#define PCI_ADDRESS_IO_SPACE 0x00000001
|
||||||
|
#define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006
|
||||||
|
#define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008
|
||||||
|
|
||||||
|
#define PCI_TYPE_32BIT 0
|
||||||
|
#define PCI_TYPE_20BIT 2
|
||||||
|
#define PCI_TYPE_64BIT 4
|
||||||
|
|
||||||
|
|
||||||
|
/* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
|
||||||
|
|
||||||
|
#define PCI_ROMADDRESS_ENABLED 0x00000001
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct _PCI_SLOT_NUMBER
|
||||||
|
{
|
||||||
|
union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
ULONG DeviceNumber:5;
|
||||||
|
ULONG FunctionNumber:3;
|
||||||
|
ULONG Reserved:24;
|
||||||
|
} bits;
|
||||||
|
ULONG AsULONG;
|
||||||
|
} u;
|
||||||
|
} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
|
||||||
|
|
||||||
|
|
||||||
/* Hal dispatch table */
|
/* Hal dispatch table */
|
||||||
|
|
||||||
typedef enum _HAL_QUERY_INFORMATION_CLASS
|
typedef enum _HAL_QUERY_INFORMATION_CLASS
|
||||||
|
|
|
@ -246,6 +246,8 @@ enum
|
||||||
IRP_MJ_MAXIMUM_FUNCTION,
|
IRP_MJ_MAXIMUM_FUNCTION,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#define IRP_MJ_SCSI IRP_MJ_INTERNAL_DEVICE_CONTROL
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Minor function numbers for IRP_MJ_FILE_SYSTEM_CONTROL
|
* Minor function numbers for IRP_MJ_FILE_SYSTEM_CONTROL
|
||||||
*/
|
*/
|
||||||
|
@ -254,6 +256,11 @@ enum
|
||||||
#define IRP_MN_VERIFY_VOLUME 0x02
|
#define IRP_MN_VERIFY_VOLUME 0x02
|
||||||
#define IRP_MN_LOAD_FILE_SYSTEM 0x03
|
#define IRP_MN_LOAD_FILE_SYSTEM 0x03
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Minor function numbers for IRP_MJ_SCSI
|
||||||
|
*/
|
||||||
|
#define IRP_MN_SCSI_CLASS 0x01
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Minor function codes for IRP_MJ_POWER
|
* Minor function codes for IRP_MJ_POWER
|
||||||
*/
|
*/
|
||||||
|
|
Loading…
Reference in a new issue