mirror of
https://github.com/reactos/reactos.git
synced 2024-07-08 05:35:06 +00:00
Moved/added some declarations
Fixed ide drive identification svn path=/trunk/; revision=2329
This commit is contained in:
Eric Kohl
parent
af347caa8c
commit
6d21eb028c
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@ -1,4 +1,4 @@
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/* $Id: ide.c,v 1.45 2001/09/09 21:28:05 ekohl Exp $
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/* $Id: ide.c,v 1.46 2001/11/01 00:28:57 ekohl Exp $
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*
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* IDE.C - IDE Disk driver
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* written by Rex Jolliff
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@ -81,48 +81,6 @@
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// ------------------------------------------------------- File Static Data
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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typedef struct _PCI_COMMON_CONFIG
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{
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USHORT VendorID; // (ro)
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USHORT DeviceID; // (ro)
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USHORT Command; // Device control
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USHORT Status;
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UCHAR RevisionID; // (ro)
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UCHAR ProgIf; // (ro)
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UCHAR SubClass; // (ro)
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UCHAR BaseClass; // (ro)
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UCHAR CacheLineSize; // (ro+)
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UCHAR LatencyTimer; // (ro+)
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UCHAR HeaderType; // (ro)
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UCHAR BIST; // Built in self test
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union
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{
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struct _PCI_HEADER_TYPE_0
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{
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ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
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ULONG CIS;
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USHORT SubVendorID;
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USHORT SubSystemID;
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ULONG ROMBaseAddress;
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ULONG Reserved2[2];
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UCHAR InterruptLine; //
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UCHAR InterruptPin; // (ro)
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UCHAR MinimumGrant; // (ro)
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UCHAR MaximumLatency; // (ro)
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} type0;
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} u;
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UCHAR DeviceSpecific[192];
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} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
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typedef struct _IDE_CONTROLLER_PARAMETERS
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{
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@ -645,6 +603,7 @@ IDEResetController(IN WORD CommandPort,
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return IDEReadError(CommandPort) == 1;
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}
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// IDECreateDevices
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//
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// DESCRIPTION:
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@ -683,7 +642,6 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
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PDEVICE_OBJECT DiskDeviceObject;
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PDEVICE_OBJECT PartitionDeviceObject;
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PIDE_DEVICE_EXTENSION DiskDeviceExtension;
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// PIDE_DEVICE_EXTENSION PartitionDeviceExtension;
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UNICODE_STRING UnicodeDeviceDirName;
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OBJECT_ATTRIBUTES DeviceDirAttributes;
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HANDLE Handle;
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@ -703,7 +661,8 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
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/* Get the Drive Identification Data */
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if (!IDEGetDriveIdentification(CommandPort, DriveIdx, &DrvParms))
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{
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DPRINT("Giving up on drive %d on controller %d...\n",
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CHECKPOINT1;
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DbgPrint("Giving up on drive %d on controller %d...\n",
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DriveIdx,
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ControllerExtension->Number);
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return FALSE;
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@ -756,10 +715,6 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
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/* Increase number of available physical disk drives */
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IoGetConfigurationInformation()->DiskCount++;
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/* Initialize device extension for the disk device */
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// DiskDeviceExtension = (PIDE_DEVICE_EXTENSION)DiskDeviceObject->DeviceExtension;
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// DiskDeviceExtension->DiskExtension = (PVOID)DiskDeviceExtension;
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/*
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* Initialize the controller timer here
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* (since it has to be tied to a device)
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@ -809,18 +764,11 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
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HarddiskIdx,
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&DrvParms,
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PartitionEntry);
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// PartitionEntry->PartitionNumber,
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// PartitionEntry->StartingOffset.QuadPart / 512 /* DrvParms.BytesPerSector*/,
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// PartitionEntry->PartitionLength.QuadPart / 512 /*DrvParms.BytesPerSector*/);
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if (!NT_SUCCESS(Status))
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{
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DbgPrint("IDECreateDevice() failed\n");
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break;
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}
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/* Initialize pointer to disk device extension */
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// PartitionDeviceExtension = (PIDE_DEVICE_EXTENSION)PartitionDeviceObject->DeviceExtension;
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// PartitionDeviceExtension->DiskExtension = (PVOID)DiskDeviceExtension;
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}
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if (PartitionList != NULL)
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@ -847,15 +795,16 @@ IDECreateDevices(IN PDRIVER_OBJECT DriverObject,
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//
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BOOLEAN
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IDEGetDriveIdentification(IN int CommandPort,
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IN int DriveNum,
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OUT PIDE_DRIVE_IDENTIFY DrvParms)
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IDEGetDriveIdentification(IN int CommandPort,
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IN int DriveNum,
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OUT PIDE_DRIVE_IDENTIFY DrvParms)
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{
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// Get the Drive Identify block from drive or die
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if (IDEPolledRead(CommandPort, 0, 0, 0, 0, 0, (DriveNum ? IDE_DH_DRV1 : 0),
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IDE_CMD_IDENT_DRV, (BYTE *)DrvParms) != 0)
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{
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CHECKPOINT1;
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return FALSE;
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}
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@ -1045,9 +994,6 @@ IDECreatePartitionDevice(IN PDRIVER_OBJECT DriverObject,
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IN ULONG DiskNumber,
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IN PIDE_DRIVE_IDENTIFY DrvParms,
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IN PPARTITION_INFORMATION PartitionInfo)
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// IN ULONG PartitionNumber,
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// IN ULONGLONG Offset,
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// IN ULONGLONG Size)
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{
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WCHAR NameBuffer[IDE_MAX_NAME_LENGTH];
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WCHAR ArcNameBuffer[IDE_MAX_NAME_LENGTH + 15];
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@ -1153,31 +1099,32 @@ IDECreatePartitionDevice(IN PDRIVER_OBJECT DriverObject,
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// int 0 is success, non 0 is an error code
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//
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static int
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IDEPolledRead(IN WORD Address,
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IN BYTE PreComp,
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IN BYTE SectorCnt,
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IN BYTE SectorNum ,
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IN BYTE CylinderLow,
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IN BYTE CylinderHigh,
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IN BYTE DrvHead,
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IN BYTE Command,
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OUT BYTE *Buffer)
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static int
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IDEPolledRead(IN WORD Address,
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IN BYTE PreComp,
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IN BYTE SectorCnt,
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IN BYTE SectorNum,
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IN BYTE CylinderLow,
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IN BYTE CylinderHigh,
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IN BYTE DrvHead,
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IN BYTE Command,
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OUT BYTE *Buffer)
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{
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BYTE Status;
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int RetryCount;
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/* Wait for STATUS.BUSY to clear */
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for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
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for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
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{
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Status = IDEReadStatus(Address);
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if (!(Status & IDE_SR_BUSY))
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if (!(Status & IDE_SR_BUSY) && !(Status & IDE_SR_DRQ))
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// if (!(Status & IDE_SR_BUSY))
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{
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break;
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}
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KeStallExecutionProcessor(10);
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}
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if (RetryCount == IDE_MAX_BUSY_RETRIES)
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if (RetryCount == IDE_MAX_BUSY_RETRIES)
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{
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return IDE_ER_ABRT;
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}
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@ -1185,39 +1132,40 @@ IDEPolledRead(IN WORD Address,
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/* Write Drive/Head to select drive */
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IDEWriteDriveHead(Address, IDE_DH_FIXED | DrvHead);
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/* Wait for STATUS.BUSY to clear and STATUS.DRDY to assert */
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for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
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/* Wait for STATUS.BUSY and STATUS.DRQ to clear */
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for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
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{
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Status = IDEReadStatus(Address);
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if (!(Status & IDE_SR_BUSY) && (Status & IDE_SR_DRDY))
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if (!(Status & IDE_SR_BUSY) && !(Status & IDE_SR_DRQ))
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{
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break;
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}
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KeStallExecutionProcessor(10);
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}
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if (RetryCount == IDE_MAX_BUSY_RETRIES)
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if (RetryCount == IDE_MAX_BUSY_RETRIES)
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{
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CHECKPOINT1;
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return IDE_ER_ABRT;
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}
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/* Issue command to drive */
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if (DrvHead & IDE_DH_LBA)
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if (DrvHead & IDE_DH_LBA)
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{
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DPRINT("READ:DRV=%d:LBA=1:BLK=%08d:SC=%02x:CM=%02x\n",
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DrvHead & IDE_DH_DRV1 ? 1 : 0,
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DrvHead & IDE_DH_DRV1 ? 1 : 0,
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((DrvHead & 0x0f) << 24) + (CylinderHigh << 16) + (CylinderLow << 8) + SectorNum,
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SectorCnt,
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SectorCnt,
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Command);
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}
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else
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}
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else
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{
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DPRINT("READ:DRV=%d:LBA=0:CH=%02x:CL=%02x:HD=%01x:SN=%02x:SC=%02x:CM=%02x\n",
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DrvHead & IDE_DH_DRV1 ? 1 : 0,
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CylinderHigh,
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CylinderLow,
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DrvHead & 0x0f,
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SectorNum,
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SectorCnt,
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DrvHead & IDE_DH_DRV1 ? 1 : 0,
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CylinderHigh,
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CylinderLow,
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DrvHead & 0x0f,
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SectorNum,
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SectorCnt,
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Command);
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}
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@ -1233,24 +1181,22 @@ IDEPolledRead(IN WORD Address,
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IDEWriteCommand(Address, Command);
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KeStallExecutionProcessor(50);
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while (1)
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while (1)
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{
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// wait for DRQ or error
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/* wait for DRQ or error */
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for (RetryCount = 0; RetryCount < IDE_MAX_POLL_RETRIES; RetryCount++)
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{
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Status = IDEReadStatus(Address);
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if (!(Status & IDE_SR_BUSY))
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if (!(Status & IDE_SR_BUSY))
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{
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if (Status & IDE_SR_ERR)
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{
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BYTE Err = IDEReadError(Address);
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return Err;
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}
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else if (Status & IDE_SR_DRQ)
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if (Status & IDE_SR_DRQ)
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{
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break;
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}
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else
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{
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return IDE_ER_ABRT;
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}
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}
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KeStallExecutionProcessor(10);
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}
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@ -1259,17 +1205,25 @@ IDEPolledRead(IN WORD Address,
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return IDE_ER_ABRT;
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}
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// Read data into buffer
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/* Read data into buffer */
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IDEReadBlock(Address, Buffer, IDE_SECTOR_BUF_SZ);
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Buffer += IDE_SECTOR_BUF_SZ;
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// Check for more sectors to read
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for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES &&
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(IDEReadStatus(Address) & IDE_SR_DRQ); RetryCount++)
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;
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if (!(IDEReadStatus(Address) & IDE_SR_BUSY))
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/* Check for more sectors to read */
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for (RetryCount = 0; RetryCount < IDE_MAX_BUSY_RETRIES; RetryCount++)
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{
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return 0;
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Status = IDEReadStatus(Address);
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if (!(Status & IDE_SR_BUSY))
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{
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if (Status & IDE_SR_DRQ)
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{
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break;
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}
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else
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{
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return 0;
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}
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}
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}
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}
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}
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@ -1,4 +1,4 @@
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/* $Id: haltypes.h,v 1.2 2001/09/23 22:14:03 chorns Exp $
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/* $Id: haltypes.h,v 1.3 2001/11/01 00:25:28 ekohl Exp $
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*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS kernel
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@ -68,6 +68,166 @@ typedef struct _DEVICE_DESCRIPTION
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} DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
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/* PCI bus definitions */
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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#define PCI_TYPE2_ADDRESSES 5
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typedef struct _PCI_COMMON_CONFIG
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{
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USHORT VendorID; /* read-only */
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USHORT DeviceID; /* read-only */
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USHORT Command;
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USHORT Status;
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UCHAR RevisionID; /* read-only */
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UCHAR ProgIf; /* read-only */
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UCHAR SubClass; /* read-only */
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UCHAR BaseClass; /* read-only */
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UCHAR CacheLineSize; /* read-only */
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UCHAR LatencyTimer; /* read-only */
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UCHAR HeaderType; /* read-only */
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UCHAR BIST;
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union
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{
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struct _PCI_HEADER_TYPE_0
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{
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ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
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ULONG CIS;
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USHORT SubVendorID;
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USHORT SubSystemID;
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ULONG ROMBaseAddress;
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ULONG Reserved2[2];
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UCHAR InterruptLine;
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UCHAR InterruptPin; /* read-only */
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UCHAR MinimumGrant; /* read-only */
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UCHAR MaximumLatency; /* read-only */
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} type0;
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/* PCI to PCI Bridge */
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struct _PCI_HEADER_TYPE_1
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{
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ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
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UCHAR PrimaryBus;
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UCHAR SecondaryBus;
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UCHAR SubordinateBus;
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UCHAR SecondaryLatency;
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UCHAR IOBase;
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UCHAR IOLimit;
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USHORT SecondaryStatus;
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USHORT MemoryBase;
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USHORT MemoryLimit;
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USHORT PrefetchBase;
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USHORT PrefetchLimit;
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ULONG PrefetchBaseUpper32;
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ULONG PrefetchLimitUpper32;
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USHORT IOBaseUpper16;
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USHORT IOLimitUpper16;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved1[3];
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ULONG ROMBaseAddress;
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} type1;
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/* PCI to CARDBUS Bridge */
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struct _PCI_HEADER_TYPE_2
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{
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ULONG SocketRegistersBaseAddress;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved;
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USHORT SecondaryStatus;
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UCHAR PrimaryBus;
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UCHAR SecondaryBus;
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UCHAR SubordinateBus;
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UCHAR SecondaryLatency;
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struct
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{
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ULONG Base;
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ULONG Limit;
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} Range[PCI_TYPE2_ADDRESSES-1];
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} type2;
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} u;
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UCHAR DeviceSpecific[192];
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} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
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#define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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#define PCI_INVALID_VENDORID 0xFFFF
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/* Bit encodings for PCI_COMMON_CONFIG.HeaderType */
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#define PCI_MULTIFUNCTION 0x80
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#define PCI_DEVICE_TYPE 0x00
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#define PCI_BRIDGE_TYPE 0x01
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/* Bit encodings for PCI_COMMON_CONFIG.Command */
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#define PCI_ENABLE_IO_SPACE 0x0001
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#define PCI_ENABLE_MEMORY_SPACE 0x0002
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#define PCI_ENABLE_BUS_MASTER 0x0004
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#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
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#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
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#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
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#define PCI_ENABLE_PARITY 0x0040
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#define PCI_ENABLE_WAIT_CYCLE 0x0080
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#define PCI_ENABLE_SERR 0x0100
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#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200
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/* Bit encodings for PCI_COMMON_CONFIG.Status */
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#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080
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#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
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#define PCI_STATUS_DEVSEL 0x0600 /* 2 bits wide */
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#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
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#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
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#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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/* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
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#define PCI_ADDRESS_IO_SPACE 0x00000001
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#define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006
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#define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008
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#define PCI_TYPE_32BIT 0
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#define PCI_TYPE_20BIT 2
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#define PCI_TYPE_64BIT 4
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/* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
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#define PCI_ROMADDRESS_ENABLED 0x00000001
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typedef struct _PCI_SLOT_NUMBER
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{
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union
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{
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struct
|
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{
|
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ULONG DeviceNumber:5;
|
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ULONG FunctionNumber:3;
|
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ULONG Reserved:24;
|
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} bits;
|
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ULONG AsULONG;
|
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} u;
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} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
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/* Hal dispatch table */
|
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typedef enum _HAL_QUERY_INFORMATION_CLASS
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|||
|
|
@ -119,50 +119,50 @@ enum
|
|||
/*
|
||||
* Possible device types
|
||||
*/
|
||||
#define FILE_DEVICE_BEEP 0x00000001
|
||||
#define FILE_DEVICE_CD_ROM 0x00000002
|
||||
#define FILE_DEVICE_BEEP 0x00000001
|
||||
#define FILE_DEVICE_CD_ROM 0x00000002
|
||||
#define FILE_DEVICE_CD_ROM_FILE_SYSTEM 0x00000003
|
||||
#define FILE_DEVICE_CONTROLLER 0x00000004
|
||||
#define FILE_DEVICE_DATALINK 0x00000005
|
||||
#define FILE_DEVICE_DFS 0x00000006
|
||||
#define FILE_DEVICE_DISK 0x00000007
|
||||
#define FILE_DEVICE_DISK_FILE_SYSTEM 0x00000008
|
||||
#define FILE_DEVICE_FILE_SYSTEM 0x00000009
|
||||
#define FILE_DEVICE_INPORT_PORT 0x0000000a
|
||||
#define FILE_DEVICE_KEYBOARD 0x0000000b
|
||||
#define FILE_DEVICE_MAILSLOT 0x0000000c
|
||||
#define FILE_DEVICE_MIDI_IN 0x0000000d
|
||||
#define FILE_DEVICE_MIDI_OUT 0x0000000e
|
||||
#define FILE_DEVICE_MOUSE 0x0000000f
|
||||
#define FILE_DEVICE_CONTROLLER 0x00000004
|
||||
#define FILE_DEVICE_DATALINK 0x00000005
|
||||
#define FILE_DEVICE_DFS 0x00000006
|
||||
#define FILE_DEVICE_DISK 0x00000007
|
||||
#define FILE_DEVICE_DISK_FILE_SYSTEM 0x00000008
|
||||
#define FILE_DEVICE_FILE_SYSTEM 0x00000009
|
||||
#define FILE_DEVICE_INPORT_PORT 0x0000000a
|
||||
#define FILE_DEVICE_KEYBOARD 0x0000000b
|
||||
#define FILE_DEVICE_MAILSLOT 0x0000000c
|
||||
#define FILE_DEVICE_MIDI_IN 0x0000000d
|
||||
#define FILE_DEVICE_MIDI_OUT 0x0000000e
|
||||
#define FILE_DEVICE_MOUSE 0x0000000f
|
||||
#define FILE_DEVICE_MULTI_UNC_PROVIDER 0x00000010
|
||||
#define FILE_DEVICE_NAMED_PIPE 0x00000011
|
||||
#define FILE_DEVICE_NETWORK 0x00000012
|
||||
#define FILE_DEVICE_NETWORK_BROWSER 0x00000013
|
||||
#define FILE_DEVICE_NAMED_PIPE 0x00000011
|
||||
#define FILE_DEVICE_NETWORK 0x00000012
|
||||
#define FILE_DEVICE_NETWORK_BROWSER 0x00000013
|
||||
#define FILE_DEVICE_NETWORK_FILE_SYSTEM 0x00000014
|
||||
#define FILE_DEVICE_NULL 0x00000015
|
||||
#define FILE_DEVICE_PARALLEL_PORT 0x00000016
|
||||
#define FILE_DEVICE_PHYSICAL_NETCARD 0x00000017
|
||||
#define FILE_DEVICE_PRINTER 0x00000018
|
||||
#define FILE_DEVICE_SCANNER 0x00000019
|
||||
#define FILE_DEVICE_NULL 0x00000015
|
||||
#define FILE_DEVICE_PARALLEL_PORT 0x00000016
|
||||
#define FILE_DEVICE_PHYSICAL_NETCARD 0x00000017
|
||||
#define FILE_DEVICE_PRINTER 0x00000018
|
||||
#define FILE_DEVICE_SCANNER 0x00000019
|
||||
#define FILE_DEVICE_SERIAL_MOUSE_PORT 0x0000001a
|
||||
#define FILE_DEVICE_SERIAL_PORT 0x0000001b
|
||||
#define FILE_DEVICE_SCREEN 0x0000001c
|
||||
#define FILE_DEVICE_SOUND 0x0000001d
|
||||
#define FILE_DEVICE_STREAMS 0x0000001e
|
||||
#define FILE_DEVICE_TAPE 0x0000001f
|
||||
#define FILE_DEVICE_TAPE_FILE_SYSTEM 0x00000020
|
||||
#define FILE_DEVICE_TRANSPORT 0x00000021
|
||||
#define FILE_DEVICE_UNKNOWN 0x00000022
|
||||
#define FILE_DEVICE_VIDEO 0x00000023
|
||||
#define FILE_DEVICE_VIRTUAL_DISK 0x00000024
|
||||
#define FILE_DEVICE_WAVE_IN 0x00000025
|
||||
#define FILE_DEVICE_WAVE_OUT 0x00000026
|
||||
#define FILE_DEVICE_8042_PORT 0x00000027
|
||||
#define FILE_DEVICE_SERIAL_PORT 0x0000001b
|
||||
#define FILE_DEVICE_SCREEN 0x0000001c
|
||||
#define FILE_DEVICE_SOUND 0x0000001d
|
||||
#define FILE_DEVICE_STREAMS 0x0000001e
|
||||
#define FILE_DEVICE_TAPE 0x0000001f
|
||||
#define FILE_DEVICE_TAPE_FILE_SYSTEM 0x00000020
|
||||
#define FILE_DEVICE_TRANSPORT 0x00000021
|
||||
#define FILE_DEVICE_UNKNOWN 0x00000022
|
||||
#define FILE_DEVICE_VIDEO 0x00000023
|
||||
#define FILE_DEVICE_VIRTUAL_DISK 0x00000024
|
||||
#define FILE_DEVICE_WAVE_IN 0x00000025
|
||||
#define FILE_DEVICE_WAVE_OUT 0x00000026
|
||||
#define FILE_DEVICE_8042_PORT 0x00000027
|
||||
#define FILE_DEVICE_NETWORK_REDIRECTOR 0x00000028
|
||||
#define FILE_DEVICE_BATTERY 0x00000029
|
||||
#define FILE_DEVICE_BUS_EXTENDER 0x0000002a
|
||||
#define FILE_DEVICE_MODEM 0x0000002b
|
||||
#define FILE_DEVICE_VDM 0x0000002c
|
||||
#define FILE_DEVICE_BATTERY 0x00000029
|
||||
#define FILE_DEVICE_BUS_EXTENDER 0x0000002a
|
||||
#define FILE_DEVICE_MODEM 0x0000002b
|
||||
#define FILE_DEVICE_VDM 0x0000002c
|
||||
#define FILE_DEVICE_MASS_STORAGE 0x0000002d
|
||||
#define FILE_DEVICE_SMB 0x0000002e
|
||||
#define FILE_DEVICE_KS 0x0000002f
|
||||
|
|
@ -246,6 +246,8 @@ enum
|
|||
IRP_MJ_MAXIMUM_FUNCTION,
|
||||
};
|
||||
|
||||
#define IRP_MJ_SCSI IRP_MJ_INTERNAL_DEVICE_CONTROL
|
||||
|
||||
/*
|
||||
* Minor function numbers for IRP_MJ_FILE_SYSTEM_CONTROL
|
||||
*/
|
||||
|
|
@ -254,6 +256,11 @@ enum
|
|||
#define IRP_MN_VERIFY_VOLUME 0x02
|
||||
#define IRP_MN_LOAD_FILE_SYSTEM 0x03
|
||||
|
||||
/*
|
||||
* Minor function numbers for IRP_MJ_SCSI
|
||||
*/
|
||||
#define IRP_MN_SCSI_CLASS 0x01
|
||||
|
||||
/*
|
||||
* Minor function codes for IRP_MJ_POWER
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue