mirror of
https://github.com/reactos/reactos.git
synced 2025-08-06 07:52:56 +00:00
- Continue cleanup, use new peripheral headers (And fix them)
- Fix ARM HAL headers and use them svn path=/trunk/; revision=33981
This commit is contained in:
ReactOS Portable Systems Group
parent
480243927a
commit
69bc0881f9
6 changed files with 156 additions and 305 deletions
|
|
@ -1,28 +1,14 @@
|
||||||
/*
|
/*
|
||||||
* COPYRIGHT: See COPYING in the top level directory
|
* PROJECT: ReactOS HAL
|
||||||
* PROJECT: ReactOS kernel
|
* LICENSE: GPL - See COPYING in the top level directory
|
||||||
* FILE: hal/hal.c
|
* FILE: hal/halarm/generic/hal.c
|
||||||
* PURPOSE: Hardware Abstraction Layer DLL
|
* PURPOSE: Hardware Abstraction Layer
|
||||||
* PROGRAMMER: Casper S. Hornstrup (chorns@users.sourceforge.net)
|
* PROGRAMMERS: ReactOS Portable Systems Group
|
||||||
* REVISION HISTORY:
|
|
||||||
* 01-08-2001 CSH Created
|
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* INCLUDES ******************************************************************/
|
/* INCLUDES *******************************************************************/
|
||||||
|
|
||||||
#include <ntddk.h>
|
|
||||||
#include <ntdddisk.h>
|
|
||||||
#include <arc/arc.h>
|
|
||||||
#include <intrin.h>
|
|
||||||
#include <ndk/halfuncs.h>
|
|
||||||
#include <ndk/iofuncs.h>
|
|
||||||
#include <ndk/kdfuncs.h>
|
|
||||||
#include <ndk/kefuncs.h>
|
|
||||||
#include <ndk/rtlfuncs.h>
|
|
||||||
#include <internal/arm/ke.h>
|
|
||||||
#include <internal/arm/intrin_i.h>
|
|
||||||
#include <bugcodes.h>
|
|
||||||
|
|
||||||
|
#include <hal.h>
|
||||||
#define NDEBUG
|
#define NDEBUG
|
||||||
#include <debug.h>
|
#include <debug.h>
|
||||||
|
|
||||||
|
|
@ -42,6 +28,77 @@
|
||||||
|
|
||||||
ULONG _KdComPortInUse = 0;
|
ULONG _KdComPortInUse = 0;
|
||||||
|
|
||||||
|
ULONG HalpIrqlTable[HIGH_LEVEL + 1] =
|
||||||
|
{
|
||||||
|
0xFFFFFFFF, // IRQL 0 PASSIVE_LEVEL
|
||||||
|
0xFFFFFFFD, // IRQL 1 APC_LEVEL
|
||||||
|
0xFFFFFFF9, // IRQL 2 DISPATCH_LEVEL
|
||||||
|
0xFFFFFFD9, // IRQL 3
|
||||||
|
0xFFFFFF99, // IRQL 4
|
||||||
|
0xFFFFFF19, // IRQL 5
|
||||||
|
0xFFFFFE19, // IRQL 6
|
||||||
|
0xFFFFFC19, // IRQL 7
|
||||||
|
0xFFFFF819, // IRQL 8
|
||||||
|
0xFFFFF019, // IRQL 9
|
||||||
|
0xFFFFE019, // IRQL 10
|
||||||
|
0xFFFFC019, // IRQL 11
|
||||||
|
0xFFFF8019, // IRQL 12
|
||||||
|
0xFFFF0019, // IRQL 13
|
||||||
|
0xFFFE0019, // IRQL 14
|
||||||
|
0xFFFC0019, // IRQL 15
|
||||||
|
0xFFF80019, // IRQL 16
|
||||||
|
0xFFF00019, // IRQL 17
|
||||||
|
0xFFE00019, // IRQL 18
|
||||||
|
0xFFC00019, // IRQL 19
|
||||||
|
0xFF800019, // IRQL 20
|
||||||
|
0xFF000019, // IRQL 21
|
||||||
|
0xFE000019, // IRQL 22
|
||||||
|
0xFC000019, // IRQL 23
|
||||||
|
0xF0000019, // IRQL 24
|
||||||
|
0x80000019, // IRQL 25
|
||||||
|
0x19, // IRQL 26
|
||||||
|
0x18, // IRQL 27 PROFILE_LEVEL
|
||||||
|
0x10, // IRQL 28 CLOCK2_LEVEL
|
||||||
|
0x00, // IRQL 29 IPI_LEVEL
|
||||||
|
0x00, // IRQL 30 POWER_LEVEL
|
||||||
|
0x00, // IRQL 31 HIGH_LEVEL
|
||||||
|
};
|
||||||
|
|
||||||
|
UCHAR HalpMaskTable[HIGH_LEVEL + 1] =
|
||||||
|
{
|
||||||
|
PROFILE_LEVEL, // INT 0 WATCHDOG
|
||||||
|
APC_LEVEL, // INT 1 SOFTWARE INTERRUPT
|
||||||
|
DISPATCH_LEVEL,// INT 2 COMM RX
|
||||||
|
IPI_LEVEL, // INT 3 COMM TX
|
||||||
|
CLOCK2_LEVEL, // INT 4 TIMER 0
|
||||||
|
3,
|
||||||
|
4,
|
||||||
|
5,
|
||||||
|
6,
|
||||||
|
7,
|
||||||
|
8,
|
||||||
|
9,
|
||||||
|
10,
|
||||||
|
11,
|
||||||
|
12,
|
||||||
|
13,
|
||||||
|
14,
|
||||||
|
15,
|
||||||
|
16,
|
||||||
|
17,
|
||||||
|
18,
|
||||||
|
19,
|
||||||
|
20,
|
||||||
|
21,
|
||||||
|
22,
|
||||||
|
23,
|
||||||
|
24,
|
||||||
|
25,
|
||||||
|
26,
|
||||||
|
26,
|
||||||
|
26
|
||||||
|
};
|
||||||
|
|
||||||
/* FUNCTIONS *****************************************************************/
|
/* FUNCTIONS *****************************************************************/
|
||||||
|
|
||||||
NTSTATUS
|
NTSTATUS
|
||||||
|
|
@ -396,124 +453,6 @@ HalpGetParameters(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
//
|
|
||||||
// INTs on the Versatile:
|
|
||||||
//
|
|
||||||
// 0 WATCHDOG -> We use it for profiling
|
|
||||||
// 1 SOFTWARE INTERRUPT -> We use it for APC delivery
|
|
||||||
// 2 COMM RX -> We use it for DPC delivery
|
|
||||||
// 3 COMM TX -> We use it for IPI delivery
|
|
||||||
// 4 TIMER0/1 -> Use for Clock Interrupt.
|
|
||||||
// 5+ XXX -> Mapped to to actual device
|
|
||||||
//
|
|
||||||
// So we have the following IRQL masks:
|
|
||||||
// PASSIVE_LEVEL - 0xFFFFFFFF (enable all interrupts)
|
|
||||||
// APC_LEVEL - 0xFFFFFFFD (disable interrupt 1)
|
|
||||||
// DISPATCH_LEVEL - 0xFFFFFFF9 (disable interrupts 1, 2)
|
|
||||||
// DEVICE_LEVEL_0 - 0xFFFFFFD9 (disable interrupts 1, 2, 5)
|
|
||||||
// DEVICE_LEVEL_N - 0x19 (everything disabled except 0, 3, 4)
|
|
||||||
// PROFILE_LEVEL - 0x18 (everything disabled except, 3, 4)
|
|
||||||
// CLOCK_LEVEL - 0x10 (everything disabled except 4)
|
|
||||||
// POWER_LEVEL, IPI_LEVEL, HIGH_LEVEL - 0x00 (everything disabled)
|
|
||||||
|
|
||||||
ULONG HalpIrqlTable[HIGH_LEVEL + 1] =
|
|
||||||
{
|
|
||||||
0xFFFFFFFF, // IRQL 0 PASSIVE_LEVEL
|
|
||||||
0xFFFFFFFD, // IRQL 1 APC_LEVEL
|
|
||||||
0xFFFFFFF9, // IRQL 2 DISPATCH_LEVEL
|
|
||||||
0xFFFFFFD9, // IRQL 3
|
|
||||||
0xFFFFFF99, // IRQL 4
|
|
||||||
0xFFFFFF19, // IRQL 5
|
|
||||||
0xFFFFFE19, // IRQL 6
|
|
||||||
0xFFFFFC19, // IRQL 7
|
|
||||||
0xFFFFF819, // IRQL 8
|
|
||||||
0xFFFFF019, // IRQL 9
|
|
||||||
0xFFFFE019, // IRQL 10
|
|
||||||
0xFFFFC019, // IRQL 11
|
|
||||||
0xFFFF8019, // IRQL 12
|
|
||||||
0xFFFF0019, // IRQL 13
|
|
||||||
0xFFFE0019, // IRQL 14
|
|
||||||
0xFFFC0019, // IRQL 15
|
|
||||||
0xFFF80019, // IRQL 16
|
|
||||||
0xFFF00019, // IRQL 17
|
|
||||||
0xFFE00019, // IRQL 18
|
|
||||||
0xFFC00019, // IRQL 19
|
|
||||||
0xFF800019, // IRQL 20
|
|
||||||
0xFF000019, // IRQL 21
|
|
||||||
0xFE000019, // IRQL 22
|
|
||||||
0xFC000019, // IRQL 23
|
|
||||||
0xF0000019, // IRQL 24
|
|
||||||
0x80000019, // IRQL 25
|
|
||||||
0x19, // IRQL 26
|
|
||||||
0x18, // IRQL 27 PROFILE_LEVEL
|
|
||||||
0x10, // IRQL 28 CLOCK2_LEVEL
|
|
||||||
0x00, // IRQL 29 IPI_LEVEL
|
|
||||||
0x00, // IRQL 30 POWER_LEVEL
|
|
||||||
0x00, // IRQL 31 HIGH_LEVEL
|
|
||||||
};
|
|
||||||
|
|
||||||
UCHAR HalpMaskTable[HIGH_LEVEL + 1] =
|
|
||||||
{
|
|
||||||
PROFILE_LEVEL,
|
|
||||||
APC_LEVEL,
|
|
||||||
DISPATCH_LEVEL,
|
|
||||||
IPI_LEVEL,
|
|
||||||
CLOCK2_LEVEL,
|
|
||||||
3,
|
|
||||||
4,
|
|
||||||
5,
|
|
||||||
6,
|
|
||||||
7,
|
|
||||||
8,
|
|
||||||
9,
|
|
||||||
10,
|
|
||||||
11,
|
|
||||||
12,
|
|
||||||
13,
|
|
||||||
14,
|
|
||||||
15,
|
|
||||||
16,
|
|
||||||
17,
|
|
||||||
18,
|
|
||||||
19,
|
|
||||||
20,
|
|
||||||
21,
|
|
||||||
22,
|
|
||||||
23,
|
|
||||||
24,
|
|
||||||
25,
|
|
||||||
26,
|
|
||||||
26,
|
|
||||||
26
|
|
||||||
};
|
|
||||||
|
|
||||||
#define VICINTSTATUS (PVOID)0xE0040000
|
|
||||||
#define VICINTENABLE (PVOID)0xE0040010
|
|
||||||
#define VICINTENCLEAR (PVOID)0xE0040014
|
|
||||||
#define VICSOFTINT (PVOID)0xE0040018
|
|
||||||
#define VICSOFTINTCLEAR (PVOID)0xE004001C
|
|
||||||
|
|
||||||
#define TIMER_LOAD (PVOID)0xE00E2000
|
|
||||||
#define TIMER_VALUE (PVOID)0xE00E2004
|
|
||||||
#define TIMER_CONTROL (PVOID)0xE00E2008
|
|
||||||
#define TIMER_INT_CLEAR (PVOID)0xE00E200C
|
|
||||||
#define TIMER_INT_STATUS (PVOID)0xE00E2010
|
|
||||||
#define TIMER_INT_MASK (PVOID)0xE00E2014
|
|
||||||
#define TIMER_BACKGROUND_LOAD (PVOID)0xE00E2018
|
|
||||||
|
|
||||||
#define TIMER2_LOAD (PVOID)0xE00E3000
|
|
||||||
#define TIMER2_VALUE (PVOID)0xE00E3004
|
|
||||||
#define TIMER2_CONTROL (PVOID)0xE00E3008
|
|
||||||
#define TIMER2_INT_CLEAR (PVOID)0xE00E300C
|
|
||||||
#define TIMER2_INT_STATUS (PVOID)0xE00E3010
|
|
||||||
#define TIMER2_INT_MASK (PVOID)0xE00E3014
|
|
||||||
#define TIMER2_BACKGROUND_LOAD (PVOID)0xE00E3018
|
|
||||||
|
|
||||||
#define _clz(a) \
|
|
||||||
({ ULONG __value, __arg = (a); \
|
|
||||||
asm ("clz\t%0, %1": "=r" (__value): "r" (__arg)); \
|
|
||||||
__value; })
|
|
||||||
|
|
||||||
ULONG
|
ULONG
|
||||||
HalGetInterruptSource(VOID)
|
HalGetInterruptSource(VOID)
|
||||||
{
|
{
|
||||||
|
|
@ -522,7 +461,7 @@ HalGetInterruptSource(VOID)
|
||||||
//
|
//
|
||||||
// Get the interrupt status, and return the highest bit set
|
// Get the interrupt status, and return the highest bit set
|
||||||
//
|
//
|
||||||
InterruptStatus = READ_REGISTER_ULONG(VICINTSTATUS);
|
InterruptStatus = READ_REGISTER_ULONG(VIC_INT_STATUS);
|
||||||
return 31 - _clz(InterruptStatus);
|
return 31 - _clz(InterruptStatus);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -533,7 +472,7 @@ HalpClockInterrupt(VOID)
|
||||||
// Clear the interrupt
|
// Clear the interrupt
|
||||||
//
|
//
|
||||||
//DPRINT1("CLOCK INTERRUPT!!!\n");
|
//DPRINT1("CLOCK INTERRUPT!!!\n");
|
||||||
WRITE_REGISTER_ULONG(TIMER_INT_CLEAR, 1);
|
WRITE_REGISTER_ULONG(TIMER0_INT_CLEAR, 1);
|
||||||
//while (TRUE);
|
//while (TRUE);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -543,7 +482,7 @@ HalpStallInterrupt(VOID)
|
||||||
//
|
//
|
||||||
// Clear the interrupt
|
// Clear the interrupt
|
||||||
//
|
//
|
||||||
WRITE_REGISTER_ULONG(TIMER_INT_CLEAR, 1);
|
WRITE_REGISTER_ULONG(TIMER0_INT_CLEAR, 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
|
|
@ -551,18 +490,18 @@ HalpInitializeInterrupts(VOID)
|
||||||
{
|
{
|
||||||
PKPCR Pcr = (PKPCR)KeGetPcr();
|
PKPCR Pcr = (PKPCR)KeGetPcr();
|
||||||
ULONG ClockInterval;
|
ULONG ClockInterval;
|
||||||
|
SP804_CONTROL_REGISTER ControlRegister;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Fill out the IRQL mappings
|
// Fill out the IRQL mappings
|
||||||
//
|
//
|
||||||
RtlCopyMemory(Pcr->IrqlTable, HalpIrqlTable, sizeof(Pcr->IrqlTable));
|
RtlCopyMemory(Pcr->IrqlTable, HalpIrqlTable, sizeof(Pcr->IrqlTable));
|
||||||
RtlCopyMemory(Pcr->IrqlMask, HalpMaskTable, sizeof(Pcr->IrqlMask));
|
RtlCopyMemory(Pcr->IrqlMask, HalpMaskTable, sizeof(Pcr->IrqlMask));
|
||||||
|
|
||||||
//
|
//
|
||||||
// Setup the clock and profile interrupt
|
// Setup the clock and profile interrupt
|
||||||
//
|
//
|
||||||
Pcr->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt;
|
Pcr->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt;
|
||||||
// Pcr->InterruptRoutine[PROFILE_LEVEL] = HalpCountInterrupt;
|
|
||||||
|
|
||||||
//
|
//
|
||||||
// Configure the interval to 10ms
|
// Configure the interval to 10ms
|
||||||
|
|
@ -571,18 +510,21 @@ HalpInitializeInterrupts(VOID)
|
||||||
// (TIMCLKENXdiv (1) * PRESCALEdiv (1))
|
// (TIMCLKENXdiv (1) * PRESCALEdiv (1))
|
||||||
//
|
//
|
||||||
ClockInterval = 0x2710;
|
ClockInterval = 0x2710;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Configure the timer
|
||||||
|
//
|
||||||
|
ControlRegister.AsUlong = 0;
|
||||||
|
ControlRegister.Wide = TRUE;
|
||||||
|
ControlRegister.Periodic = TRUE;
|
||||||
|
ControlRegister.Interrupt = TRUE;
|
||||||
|
ControlRegister.Enabled = TRUE;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Enable the timer
|
// Enable the timer
|
||||||
//
|
//
|
||||||
WRITE_REGISTER_ULONG(TIMER_LOAD, ClockInterval);
|
WRITE_REGISTER_ULONG(TIMER0_LOAD, ClockInterval);
|
||||||
WRITE_REGISTER_ULONG(TIMER_CONTROL,
|
WRITE_REGISTER_ULONG(TIMER0_CONTROL, ControlRegister.AsUlong);
|
||||||
0 << 0 | // wrapping mode
|
|
||||||
1 << 1 | // 32-bit mode
|
|
||||||
0 << 2 | // 0 stages of prescale, divided by 1
|
|
||||||
1 << 5 | // enable interrupt
|
|
||||||
1 << 6 | // periodic mode
|
|
||||||
1 << 7); // enable it
|
|
||||||
}
|
}
|
||||||
|
|
||||||
ULONG HalpCurrentTimeIncrement, HalpNextTimeIncrement, HalpNextIntervalCount;
|
ULONG HalpCurrentTimeIncrement, HalpNextTimeIncrement, HalpNextIntervalCount;
|
||||||
|
|
@ -805,7 +747,7 @@ HalRequestSoftwareInterrupt(IN KIRQL Request)
|
||||||
// Force a software interrupt
|
// Force a software interrupt
|
||||||
//
|
//
|
||||||
DPRINT1("[SOFTINT]: %d\n", Request);
|
DPRINT1("[SOFTINT]: %d\n", Request);
|
||||||
WRITE_REGISTER_ULONG(VICSOFTINT, 1 << Request);
|
WRITE_REGISTER_ULONG(VIC_SOFT_INT, 1 << Request);
|
||||||
}
|
}
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
|
|
@ -816,7 +758,7 @@ HalClearSoftwareInterrupt(IN KIRQL Request)
|
||||||
// Force a software interrupt
|
// Force a software interrupt
|
||||||
//
|
//
|
||||||
DPRINT1("[SOFTINTC] %d\n", Request);
|
DPRINT1("[SOFTINTC] %d\n", Request);
|
||||||
WRITE_REGISTER_ULONG(VICSOFTINTCLEAR, 1 << Request);
|
WRITE_REGISTER_ULONG(VIC_SOFT_INT_CLEAR, 1 << Request);
|
||||||
}
|
}
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
|
|
@ -1081,31 +1023,27 @@ VOID
|
||||||
NTAPI
|
NTAPI
|
||||||
KeStallExecutionProcessor(IN ULONG Microseconds)
|
KeStallExecutionProcessor(IN ULONG Microseconds)
|
||||||
{
|
{
|
||||||
//
|
SP804_CONTROL_REGISTER ControlRegister;
|
||||||
// Configure the interval to xxx Micrseconds
|
|
||||||
// (INTERVAL (xxx us) * TIMCLKfreq (1MHz))
|
|
||||||
// ---------------------------------------
|
|
||||||
// (TIMCLKENXdiv (1) * PRESCALEdiv (1))
|
|
||||||
//
|
|
||||||
// This works out great, since 1MHz * 1 us = 1!
|
|
||||||
//
|
|
||||||
|
|
||||||
//
|
//
|
||||||
// Enable the timer
|
// Enable the timer
|
||||||
//
|
//
|
||||||
WRITE_REGISTER_ULONG(TIMER2_LOAD, Microseconds);
|
WRITE_REGISTER_ULONG(TIMER1_LOAD, Microseconds);
|
||||||
WRITE_REGISTER_ULONG(TIMER2_CONTROL,
|
|
||||||
1 << 0 | // one-shot mode
|
//
|
||||||
1 << 1 | // 32-bit mode
|
// Configure the timer
|
||||||
0 << 2 | // 0 stages of prescale, divided by 1
|
//
|
||||||
0 << 5 | // no interrupt
|
ControlRegister.AsUlong = 0;
|
||||||
1 << 6 | // periodic mode
|
ControlRegister.OneShot = TRUE;
|
||||||
1 << 7); // enable it
|
ControlRegister.Wide = TRUE;
|
||||||
|
ControlRegister.Periodic = TRUE;
|
||||||
|
ControlRegister.Enabled = TRUE;
|
||||||
|
WRITE_REGISTER_ULONG(TIMER1_CONTROL, ControlRegister.AsUlong);
|
||||||
|
|
||||||
//
|
//
|
||||||
// Now we will loop until the timer reached 0
|
// Now we will loop until the timer reached 0
|
||||||
//
|
//
|
||||||
while (READ_REGISTER_ULONG(TIMER2_VALUE));
|
while (READ_REGISTER_ULONG(TIMER1_VALUE));
|
||||||
}
|
}
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
|
|
@ -1137,13 +1075,13 @@ KfLowerIrql(IN KIRQL NewIrql)
|
||||||
//
|
//
|
||||||
// Clear interrupts associated to the old IRQL
|
// Clear interrupts associated to the old IRQL
|
||||||
//
|
//
|
||||||
WRITE_REGISTER_ULONG(VICINTENCLEAR, 0xFFFFFFFF);
|
WRITE_REGISTER_ULONG(VIC_INT_CLEAR, 0xFFFFFFFF);
|
||||||
|
|
||||||
//
|
//
|
||||||
// Set the new interrupt mask
|
// Set the new interrupt mask
|
||||||
// PL190 VIC support only for now
|
// PL190 VIC support only for now
|
||||||
//
|
//
|
||||||
WRITE_REGISTER_ULONG(VICINTENABLE, InterruptMask);
|
WRITE_REGISTER_ULONG(VIC_INT_ENABLE, InterruptMask);
|
||||||
|
|
||||||
//
|
//
|
||||||
// Save the new IRQL
|
// Save the new IRQL
|
||||||
|
|
@ -1183,13 +1121,13 @@ KfRaiseIrql(IN KIRQL NewIrql)
|
||||||
//
|
//
|
||||||
// Clear interrupts associated to the old IRQL
|
// Clear interrupts associated to the old IRQL
|
||||||
//
|
//
|
||||||
WRITE_REGISTER_ULONG(VICINTENCLEAR, 0xFFFFFFFF);
|
WRITE_REGISTER_ULONG(VIC_INT_CLEAR, 0xFFFFFFFF);
|
||||||
|
|
||||||
//
|
//
|
||||||
// Set the new interrupt mask
|
// Set the new interrupt mask
|
||||||
// PL190 VIC support only for now
|
// PL190 VIC support only for now
|
||||||
//
|
//
|
||||||
WRITE_REGISTER_ULONG(VICINTENABLE, InterruptMask);
|
WRITE_REGISTER_ULONG(VIC_INT_ENABLE, InterruptMask);
|
||||||
|
|
||||||
//
|
//
|
||||||
// Save the new IRQL
|
// Save the new IRQL
|
||||||
|
|
|
||||||
|
|
@ -1,9 +1,9 @@
|
||||||
/*
|
/*
|
||||||
* COPYRIGHT: See COPYING in the top level directory
|
* PROJECT: ReactOS HAL
|
||||||
* PROJECT: ReactOS Hardware Abstraction Layer
|
* LICENSE: GPL - See COPYING in the top level directory
|
||||||
* FILE: hal/halx86/include/hal.h
|
* FILE: hal/halarm/include/hal.h
|
||||||
* PURPOSE: HAL Header
|
* PURPOSE: Hardware Abstraction Layer Header
|
||||||
* PROGRAMMER: Alex Ionescu (alex@relsoft.net)
|
* PROGRAMMERS: ReactOS Portable Systems Group
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* INCLUDES ******************************************************************/
|
/* INCLUDES ******************************************************************/
|
||||||
|
|
|
||||||
|
|
@ -1,114 +1,22 @@
|
||||||
/*
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __INTERNAL_HAL_HAL_H
|
#ifndef __INTERNAL_HAL_HAL_H
|
||||||
#define __INTERNAL_HAL_HAL_H
|
#define __INTERNAL_HAL_HAL_H
|
||||||
|
|
||||||
/* WDK Hack */
|
//
|
||||||
|
// ARM Headers
|
||||||
|
//
|
||||||
|
#include <internal/arm/ke.h>
|
||||||
|
#include <internal/arm/intrin_i.h>
|
||||||
|
|
||||||
|
//
|
||||||
|
// Versatile Peripherals
|
||||||
|
//
|
||||||
|
#include <peripherals/pl011.h>
|
||||||
|
#include <peripherals/pl190.h>
|
||||||
|
#include <peripherals/sp804.h>
|
||||||
|
|
||||||
|
//
|
||||||
|
// WDK Hack
|
||||||
|
//
|
||||||
#define KdComPortInUse _KdComPortInUse
|
#define KdComPortInUse _KdComPortInUse
|
||||||
|
|
||||||
#define HAL_APC_REQUEST 0
|
|
||||||
#define HAL_DPC_REQUEST 1
|
|
||||||
|
|
||||||
/* Conversion functions */
|
|
||||||
#define BCD_INT(bcd) \
|
|
||||||
(((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
|
|
||||||
#define INT_BCD(int) \
|
|
||||||
(UCHAR)(((int / 10) << 4) + (int % 10))
|
|
||||||
|
|
||||||
/* adapter.c */
|
|
||||||
PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
|
|
||||||
|
|
||||||
/* bus.c */
|
|
||||||
VOID NTAPI HalpInitNonBusHandler (VOID);
|
|
||||||
|
|
||||||
/* irql.c */
|
|
||||||
VOID NTAPI HalpInitPICs(VOID);
|
|
||||||
|
|
||||||
/* udelay.c */
|
|
||||||
VOID NTAPI HalpInitializeClock(VOID);
|
|
||||||
|
|
||||||
/* pci.c */
|
|
||||||
VOID HalpInitPciBus (VOID);
|
|
||||||
|
|
||||||
/* dma.c */
|
|
||||||
VOID HalpInitDma (VOID);
|
|
||||||
|
|
||||||
/* Non-generic initialization */
|
|
||||||
VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
|
|
||||||
VOID HalpInitPhase1(VOID);
|
|
||||||
VOID NTAPI HalpClockInterrupt(VOID);
|
|
||||||
|
|
||||||
//
|
|
||||||
// KD Support
|
|
||||||
//
|
|
||||||
VOID
|
|
||||||
NTAPI
|
|
||||||
HalpCheckPowerButton(
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
NTAPI
|
|
||||||
HalpRegisterKdSupportFunctions(
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
NTSTATUS
|
|
||||||
NTAPI
|
|
||||||
HalpSetupPciDeviceForDebugging(
|
|
||||||
IN PVOID LoaderBlock,
|
|
||||||
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
|
|
||||||
);
|
|
||||||
|
|
||||||
NTSTATUS
|
|
||||||
NTAPI
|
|
||||||
HalpReleasePciDeviceForDebugging(
|
|
||||||
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
|
|
||||||
);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Memory routines
|
|
||||||
//
|
|
||||||
PVOID
|
|
||||||
NTAPI
|
|
||||||
HalpMapPhysicalMemory64(
|
|
||||||
IN PHYSICAL_ADDRESS PhysicalAddress,
|
|
||||||
IN ULONG NumberPage
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
NTAPI
|
|
||||||
HalpUnmapVirtualAddress(
|
|
||||||
IN PVOID VirtualAddress,
|
|
||||||
IN ULONG NumberPages
|
|
||||||
);
|
|
||||||
|
|
||||||
/* sysinfo.c */
|
|
||||||
NTSTATUS
|
|
||||||
NTAPI
|
|
||||||
HaliQuerySystemInformation(
|
|
||||||
IN HAL_QUERY_INFORMATION_CLASS InformationClass,
|
|
||||||
IN ULONG BufferSize,
|
|
||||||
IN OUT PVOID Buffer,
|
|
||||||
OUT PULONG ReturnedLength
|
|
||||||
);
|
|
||||||
|
|
||||||
NTSTATUS
|
|
||||||
NTAPI
|
|
||||||
HaliSetSystemInformation(
|
|
||||||
IN HAL_SET_INFORMATION_CLASS InformationClass,
|
|
||||||
IN ULONG BufferSize,
|
|
||||||
IN OUT PVOID Buffer
|
|
||||||
);
|
|
||||||
|
|
||||||
typedef struct tagHALP_HOOKS
|
|
||||||
{
|
|
||||||
void (*InitPciBus)(ULONG BusNumber, PBUS_HANDLER BusHandler);
|
|
||||||
} HALP_HOOKS, *PHALP_HOOKS;
|
|
||||||
|
|
||||||
extern HALP_HOOKS HalpHooks;
|
|
||||||
extern KSPIN_LOCK HalpSystemHardwareLock;
|
|
||||||
|
|
||||||
#endif /* __INTERNAL_HAL_HAL_H */
|
#endif /* __INTERNAL_HAL_HAL_H */
|
||||||
|
|
|
||||||
|
|
@ -289,6 +289,10 @@ static __inline__ __attribute__((always_inline)) unsigned long _rotl(const unsig
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#define _clz(a) \
|
||||||
|
({ ULONG __value, __arg = (a); \
|
||||||
|
asm ("clz\t%0, %1": "=r" (__value): "r" (__arg)); \
|
||||||
|
__value; })
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
/* EOF */
|
/* EOF */
|
||||||
|
|
|
||||||
|
|
@ -16,5 +16,5 @@
|
||||||
#define VIC_INT_STATUS (VIC_BASE + 0x00)
|
#define VIC_INT_STATUS (VIC_BASE + 0x00)
|
||||||
#define VIC_INT_ENABLE (VIC_BASE + 0x10)
|
#define VIC_INT_ENABLE (VIC_BASE + 0x10)
|
||||||
#define VIC_INT_CLEAR (VIC_BASE + 0x14)
|
#define VIC_INT_CLEAR (VIC_BASE + 0x14)
|
||||||
#define VIC_SOFT_INT (VIC_BASE + 0x18
|
#define VIC_SOFT_INT (VIC_BASE + 0x18)
|
||||||
#define VIC_SOFT_INT_CLEAR (VIC_BASE + 0x1C)
|
#define VIC_SOFT_INT_CLEAR (VIC_BASE + 0x1C)
|
||||||
|
|
|
||||||
|
|
@ -12,20 +12,20 @@
|
||||||
// Timer Registers
|
// Timer Registers
|
||||||
//
|
//
|
||||||
#define TIMER_BASE(x) (PVOID)(0xE00E2000 + (x * 0x1000)) /* HACK: freeldr mapped it here */
|
#define TIMER_BASE(x) (PVOID)(0xE00E2000 + (x * 0x1000)) /* HACK: freeldr mapped it here */
|
||||||
#define TIMER0_LOAD TIMER_BASE(0, 0x00)
|
#define TIMER0_LOAD TIMER_BASE(0) + 0x00
|
||||||
#define TIMER0_VALUE TIMER_BASE(0, 0x04)
|
#define TIMER0_VALUE TIMER_BASE(0) + 0x04
|
||||||
#define TIMER0_CONTROL TIMER_BASE(0, 0x08)
|
#define TIMER0_CONTROL TIMER_BASE(0) + 0x08
|
||||||
#define TIMER0_INT_CLEAR TIMER_BASE(0, 0x0C)
|
#define TIMER0_INT_CLEAR TIMER_BASE(0) + 0x0C
|
||||||
#define TIMER0_INT_STATUS TIMER_BASE(0, 0x10)
|
#define TIMER0_INT_STATUS TIMER_BASE(0) + 0x10
|
||||||
#define TIMER0_INT_MASK TIMER_BASE(0, 0x14)
|
#define TIMER0_INT_MASK TIMER_BASE(0) + 0x14
|
||||||
#define TIMER0_BACKGROUND_LOAD TIMER_BASE(0, 0x18)
|
#define TIMER0_BACKGROUND_LOAD TIMER_BASE(1) + 0x18
|
||||||
#define TIMER1_LOAD TIMER_BASE(1, 0x00)
|
#define TIMER1_LOAD TIMER_BASE(1) + 0x00
|
||||||
#define TIMER1_VALUE TIMER_BASE(1, 0x04)
|
#define TIMER1_VALUE TIMER_BASE(1) + 0x04
|
||||||
#define TIMER1_CONTROL TIMER_BASE(1, 0x08)
|
#define TIMER1_CONTROL TIMER_BASE(1) + 0x08
|
||||||
#define TIMER1_INT_CLEAR TIMER_BASE(1, 0x0C)
|
#define TIMER1_INT_CLEAR TIMER_BASE(1) + 0x0C
|
||||||
#define TIMER1_INT_STATUS TIMER_BASE(1, 0x10)
|
#define TIMER1_INT_STATUS TIMER_BASE(1) + 0x10
|
||||||
#define TIMER1_INT_MASK TIMER_BASE(1, 0x14)
|
#define TIMER1_INT_MASK TIMER_BASE(1) + 0x14
|
||||||
#define TIMER1_BACKGROUND_LOAD TIMER_BASE(1, 0x18)
|
#define TIMER1_BACKGROUND_LOAD TIMER_BASE(1) + 0x18
|
||||||
|
|
||||||
//
|
//
|
||||||
// Control Register
|
// Control Register
|
||||||
|
|
@ -34,13 +34,14 @@ typedef union _SP804_CONTROL_REGISTER
|
||||||
{
|
{
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
ULONG Wrap:1;
|
ULONG OneShot:1;
|
||||||
ULONG Wide:1;
|
ULONG Wide:1;
|
||||||
ULONG Prescale:2;
|
ULONG Prescale:2;
|
||||||
ULONG Reserved:1;
|
ULONG Reserved:1;
|
||||||
ULONG Interrupt:1;
|
ULONG Interrupt:1;
|
||||||
ULONG Periodic:1;
|
ULONG Periodic:1;
|
||||||
ULONG Enabled:1;
|
ULONG Enabled:1;
|
||||||
|
ULONG Unused:24;
|
||||||
};
|
};
|
||||||
ULONG AsUlong;
|
ULONG AsUlong;
|
||||||
} SP804_CONTROL_REGISTER, *PSP804_CONTROL_REGISTER;
|
} SP804_CONTROL_REGISTER, *PSP804_CONTROL_REGISTER;
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue