mirror of
https://github.com/reactos/reactos.git
synced 2024-12-28 10:04:49 +00:00
- Continue cleanup, use new peripheral headers (And fix them)
- Fix ARM HAL headers and use them svn path=/trunk/; revision=33981
This commit is contained in:
ReactOS Portable Systems Group
parent
480243927a
commit
69bc0881f9
6 changed files with 156 additions and 305 deletions
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@ -1,28 +1,14 @@
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/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS kernel
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* FILE: hal/hal.c
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* PURPOSE: Hardware Abstraction Layer DLL
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* PROGRAMMER: Casper S. Hornstrup (chorns@users.sourceforge.net)
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* REVISION HISTORY:
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* 01-08-2001 CSH Created
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* PROJECT: ReactOS HAL
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: hal/halarm/generic/hal.c
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* PURPOSE: Hardware Abstraction Layer
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES ******************************************************************/
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#include <ntddk.h>
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#include <ntdddisk.h>
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#include <arc/arc.h>
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#include <intrin.h>
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#include <ndk/halfuncs.h>
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#include <ndk/iofuncs.h>
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#include <ndk/kdfuncs.h>
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#include <ndk/kefuncs.h>
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#include <ndk/rtlfuncs.h>
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#include <internal/arm/ke.h>
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#include <internal/arm/intrin_i.h>
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#include <bugcodes.h>
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/* INCLUDES *******************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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@ -42,6 +28,77 @@
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ULONG _KdComPortInUse = 0;
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ULONG HalpIrqlTable[HIGH_LEVEL + 1] =
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{
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0xFFFFFFFF, // IRQL 0 PASSIVE_LEVEL
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0xFFFFFFFD, // IRQL 1 APC_LEVEL
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0xFFFFFFF9, // IRQL 2 DISPATCH_LEVEL
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0xFFFFFFD9, // IRQL 3
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0xFFFFFF99, // IRQL 4
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0xFFFFFF19, // IRQL 5
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0xFFFFFE19, // IRQL 6
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0xFFFFFC19, // IRQL 7
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0xFFFFF819, // IRQL 8
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0xFFFFF019, // IRQL 9
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0xFFFFE019, // IRQL 10
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0xFFFFC019, // IRQL 11
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0xFFFF8019, // IRQL 12
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0xFFFF0019, // IRQL 13
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0xFFFE0019, // IRQL 14
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0xFFFC0019, // IRQL 15
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0xFFF80019, // IRQL 16
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0xFFF00019, // IRQL 17
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0xFFE00019, // IRQL 18
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0xFFC00019, // IRQL 19
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0xFF800019, // IRQL 20
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0xFF000019, // IRQL 21
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0xFE000019, // IRQL 22
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0xFC000019, // IRQL 23
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0xF0000019, // IRQL 24
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0x80000019, // IRQL 25
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0x19, // IRQL 26
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0x18, // IRQL 27 PROFILE_LEVEL
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0x10, // IRQL 28 CLOCK2_LEVEL
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0x00, // IRQL 29 IPI_LEVEL
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0x00, // IRQL 30 POWER_LEVEL
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0x00, // IRQL 31 HIGH_LEVEL
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};
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UCHAR HalpMaskTable[HIGH_LEVEL + 1] =
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{
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PROFILE_LEVEL, // INT 0 WATCHDOG
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APC_LEVEL, // INT 1 SOFTWARE INTERRUPT
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DISPATCH_LEVEL,// INT 2 COMM RX
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IPI_LEVEL, // INT 3 COMM TX
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CLOCK2_LEVEL, // INT 4 TIMER 0
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3,
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4,
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5,
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6,
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7,
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8,
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9,
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10,
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11,
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12,
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13,
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14,
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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26,
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26
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};
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/* FUNCTIONS *****************************************************************/
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NTSTATUS
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@ -396,124 +453,6 @@ HalpGetParameters(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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}
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}
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//
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// INTs on the Versatile:
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//
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// 0 WATCHDOG -> We use it for profiling
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// 1 SOFTWARE INTERRUPT -> We use it for APC delivery
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// 2 COMM RX -> We use it for DPC delivery
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// 3 COMM TX -> We use it for IPI delivery
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// 4 TIMER0/1 -> Use for Clock Interrupt.
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// 5+ XXX -> Mapped to to actual device
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//
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// So we have the following IRQL masks:
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// PASSIVE_LEVEL - 0xFFFFFFFF (enable all interrupts)
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// APC_LEVEL - 0xFFFFFFFD (disable interrupt 1)
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// DISPATCH_LEVEL - 0xFFFFFFF9 (disable interrupts 1, 2)
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// DEVICE_LEVEL_0 - 0xFFFFFFD9 (disable interrupts 1, 2, 5)
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// DEVICE_LEVEL_N - 0x19 (everything disabled except 0, 3, 4)
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// PROFILE_LEVEL - 0x18 (everything disabled except, 3, 4)
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// CLOCK_LEVEL - 0x10 (everything disabled except 4)
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// POWER_LEVEL, IPI_LEVEL, HIGH_LEVEL - 0x00 (everything disabled)
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ULONG HalpIrqlTable[HIGH_LEVEL + 1] =
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{
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0xFFFFFFFF, // IRQL 0 PASSIVE_LEVEL
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0xFFFFFFFD, // IRQL 1 APC_LEVEL
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0xFFFFFFF9, // IRQL 2 DISPATCH_LEVEL
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0xFFFFFFD9, // IRQL 3
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0xFFFFFF99, // IRQL 4
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0xFFFFFF19, // IRQL 5
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0xFFFFFE19, // IRQL 6
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0xFFFFFC19, // IRQL 7
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0xFFFFF819, // IRQL 8
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0xFFFFF019, // IRQL 9
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0xFFFFE019, // IRQL 10
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0xFFFFC019, // IRQL 11
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0xFFFF8019, // IRQL 12
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0xFFFF0019, // IRQL 13
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0xFFFE0019, // IRQL 14
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0xFFFC0019, // IRQL 15
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0xFFF80019, // IRQL 16
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0xFFF00019, // IRQL 17
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0xFFE00019, // IRQL 18
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0xFFC00019, // IRQL 19
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0xFF800019, // IRQL 20
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0xFF000019, // IRQL 21
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0xFE000019, // IRQL 22
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0xFC000019, // IRQL 23
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0xF0000019, // IRQL 24
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0x80000019, // IRQL 25
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0x19, // IRQL 26
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0x18, // IRQL 27 PROFILE_LEVEL
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0x10, // IRQL 28 CLOCK2_LEVEL
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0x00, // IRQL 29 IPI_LEVEL
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0x00, // IRQL 30 POWER_LEVEL
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0x00, // IRQL 31 HIGH_LEVEL
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};
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UCHAR HalpMaskTable[HIGH_LEVEL + 1] =
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{
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PROFILE_LEVEL,
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APC_LEVEL,
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DISPATCH_LEVEL,
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IPI_LEVEL,
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CLOCK2_LEVEL,
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3,
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4,
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5,
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6,
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7,
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8,
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9,
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10,
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11,
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12,
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13,
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14,
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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26,
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26
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};
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#define VICINTSTATUS (PVOID)0xE0040000
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#define VICINTENABLE (PVOID)0xE0040010
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#define VICINTENCLEAR (PVOID)0xE0040014
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#define VICSOFTINT (PVOID)0xE0040018
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#define VICSOFTINTCLEAR (PVOID)0xE004001C
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#define TIMER_LOAD (PVOID)0xE00E2000
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#define TIMER_VALUE (PVOID)0xE00E2004
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#define TIMER_CONTROL (PVOID)0xE00E2008
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#define TIMER_INT_CLEAR (PVOID)0xE00E200C
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#define TIMER_INT_STATUS (PVOID)0xE00E2010
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#define TIMER_INT_MASK (PVOID)0xE00E2014
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#define TIMER_BACKGROUND_LOAD (PVOID)0xE00E2018
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#define TIMER2_LOAD (PVOID)0xE00E3000
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#define TIMER2_VALUE (PVOID)0xE00E3004
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#define TIMER2_CONTROL (PVOID)0xE00E3008
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#define TIMER2_INT_CLEAR (PVOID)0xE00E300C
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#define TIMER2_INT_STATUS (PVOID)0xE00E3010
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#define TIMER2_INT_MASK (PVOID)0xE00E3014
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#define TIMER2_BACKGROUND_LOAD (PVOID)0xE00E3018
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#define _clz(a) \
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({ ULONG __value, __arg = (a); \
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asm ("clz\t%0, %1": "=r" (__value): "r" (__arg)); \
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__value; })
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ULONG
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HalGetInterruptSource(VOID)
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{
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@ -522,7 +461,7 @@ HalGetInterruptSource(VOID)
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//
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// Get the interrupt status, and return the highest bit set
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//
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InterruptStatus = READ_REGISTER_ULONG(VICINTSTATUS);
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InterruptStatus = READ_REGISTER_ULONG(VIC_INT_STATUS);
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return 31 - _clz(InterruptStatus);
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}
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@ -533,7 +472,7 @@ HalpClockInterrupt(VOID)
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// Clear the interrupt
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//
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//DPRINT1("CLOCK INTERRUPT!!!\n");
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WRITE_REGISTER_ULONG(TIMER_INT_CLEAR, 1);
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WRITE_REGISTER_ULONG(TIMER0_INT_CLEAR, 1);
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//while (TRUE);
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}
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@ -543,7 +482,7 @@ HalpStallInterrupt(VOID)
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//
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// Clear the interrupt
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//
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WRITE_REGISTER_ULONG(TIMER_INT_CLEAR, 1);
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WRITE_REGISTER_ULONG(TIMER0_INT_CLEAR, 1);
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}
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VOID
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@ -551,18 +490,18 @@ HalpInitializeInterrupts(VOID)
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{
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PKPCR Pcr = (PKPCR)KeGetPcr();
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ULONG ClockInterval;
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SP804_CONTROL_REGISTER ControlRegister;
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//
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// Fill out the IRQL mappings
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//
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RtlCopyMemory(Pcr->IrqlTable, HalpIrqlTable, sizeof(Pcr->IrqlTable));
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RtlCopyMemory(Pcr->IrqlMask, HalpMaskTable, sizeof(Pcr->IrqlMask));
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//
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// Setup the clock and profile interrupt
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//
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Pcr->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt;
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// Pcr->InterruptRoutine[PROFILE_LEVEL] = HalpCountInterrupt;
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//
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// Configure the interval to 10ms
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@ -571,18 +510,21 @@ HalpInitializeInterrupts(VOID)
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// (TIMCLKENXdiv (1) * PRESCALEdiv (1))
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//
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ClockInterval = 0x2710;
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//
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// Configure the timer
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//
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ControlRegister.AsUlong = 0;
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ControlRegister.Wide = TRUE;
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ControlRegister.Periodic = TRUE;
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ControlRegister.Interrupt = TRUE;
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ControlRegister.Enabled = TRUE;
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//
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// Enable the timer
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//
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WRITE_REGISTER_ULONG(TIMER_LOAD, ClockInterval);
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WRITE_REGISTER_ULONG(TIMER_CONTROL,
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0 << 0 | // wrapping mode
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1 << 1 | // 32-bit mode
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0 << 2 | // 0 stages of prescale, divided by 1
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1 << 5 | // enable interrupt
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1 << 6 | // periodic mode
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1 << 7); // enable it
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WRITE_REGISTER_ULONG(TIMER0_LOAD, ClockInterval);
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WRITE_REGISTER_ULONG(TIMER0_CONTROL, ControlRegister.AsUlong);
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}
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ULONG HalpCurrentTimeIncrement, HalpNextTimeIncrement, HalpNextIntervalCount;
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@ -805,7 +747,7 @@ HalRequestSoftwareInterrupt(IN KIRQL Request)
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// Force a software interrupt
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//
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DPRINT1("[SOFTINT]: %d\n", Request);
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WRITE_REGISTER_ULONG(VICSOFTINT, 1 << Request);
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WRITE_REGISTER_ULONG(VIC_SOFT_INT, 1 << Request);
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}
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VOID
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@ -816,7 +758,7 @@ HalClearSoftwareInterrupt(IN KIRQL Request)
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// Force a software interrupt
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//
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DPRINT1("[SOFTINTC] %d\n", Request);
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WRITE_REGISTER_ULONG(VICSOFTINTCLEAR, 1 << Request);
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WRITE_REGISTER_ULONG(VIC_SOFT_INT_CLEAR, 1 << Request);
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}
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VOID
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@ -1081,31 +1023,27 @@ VOID
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NTAPI
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KeStallExecutionProcessor(IN ULONG Microseconds)
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{
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//
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// Configure the interval to xxx Micrseconds
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// (INTERVAL (xxx us) * TIMCLKfreq (1MHz))
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// ---------------------------------------
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// (TIMCLKENXdiv (1) * PRESCALEdiv (1))
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//
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// This works out great, since 1MHz * 1 us = 1!
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//
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SP804_CONTROL_REGISTER ControlRegister;
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//
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// Enable the timer
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//
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WRITE_REGISTER_ULONG(TIMER2_LOAD, Microseconds);
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WRITE_REGISTER_ULONG(TIMER2_CONTROL,
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1 << 0 | // one-shot mode
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1 << 1 | // 32-bit mode
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0 << 2 | // 0 stages of prescale, divided by 1
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0 << 5 | // no interrupt
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1 << 6 | // periodic mode
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1 << 7); // enable it
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WRITE_REGISTER_ULONG(TIMER1_LOAD, Microseconds);
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//
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// Configure the timer
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//
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ControlRegister.AsUlong = 0;
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ControlRegister.OneShot = TRUE;
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ControlRegister.Wide = TRUE;
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ControlRegister.Periodic = TRUE;
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ControlRegister.Enabled = TRUE;
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WRITE_REGISTER_ULONG(TIMER1_CONTROL, ControlRegister.AsUlong);
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//
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// Now we will loop until the timer reached 0
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//
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while (READ_REGISTER_ULONG(TIMER2_VALUE));
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while (READ_REGISTER_ULONG(TIMER1_VALUE));
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}
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VOID
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@ -1137,13 +1075,13 @@ KfLowerIrql(IN KIRQL NewIrql)
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//
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// Clear interrupts associated to the old IRQL
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//
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WRITE_REGISTER_ULONG(VICINTENCLEAR, 0xFFFFFFFF);
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WRITE_REGISTER_ULONG(VIC_INT_CLEAR, 0xFFFFFFFF);
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//
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// Set the new interrupt mask
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// PL190 VIC support only for now
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//
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WRITE_REGISTER_ULONG(VICINTENABLE, InterruptMask);
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WRITE_REGISTER_ULONG(VIC_INT_ENABLE, InterruptMask);
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//
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// Save the new IRQL
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@ -1183,13 +1121,13 @@ KfRaiseIrql(IN KIRQL NewIrql)
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//
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// Clear interrupts associated to the old IRQL
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//
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WRITE_REGISTER_ULONG(VICINTENCLEAR, 0xFFFFFFFF);
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WRITE_REGISTER_ULONG(VIC_INT_CLEAR, 0xFFFFFFFF);
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//
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// Set the new interrupt mask
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// PL190 VIC support only for now
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//
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WRITE_REGISTER_ULONG(VICINTENABLE, InterruptMask);
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WRITE_REGISTER_ULONG(VIC_INT_ENABLE, InterruptMask);
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//
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// Save the new IRQL
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@ -1,9 +1,9 @@
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/*
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* COPYRIGHT: See COPYING in the top level directory
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* PROJECT: ReactOS Hardware Abstraction Layer
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* FILE: hal/halx86/include/hal.h
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* PURPOSE: HAL Header
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* PROGRAMMER: Alex Ionescu (alex@relsoft.net)
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* PROJECT: ReactOS HAL
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* LICENSE: GPL - See COPYING in the top level directory
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* FILE: hal/halarm/include/hal.h
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* PURPOSE: Hardware Abstraction Layer Header
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES ******************************************************************/
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|
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@ -1,114 +1,22 @@
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/*
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*
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*/
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#ifndef __INTERNAL_HAL_HAL_H
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#define __INTERNAL_HAL_HAL_H
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/* WDK Hack */
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//
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// ARM Headers
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//
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#include <internal/arm/ke.h>
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#include <internal/arm/intrin_i.h>
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//
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// Versatile Peripherals
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//
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#include <peripherals/pl011.h>
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#include <peripherals/pl190.h>
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#include <peripherals/sp804.h>
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//
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// WDK Hack
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//
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#define KdComPortInUse _KdComPortInUse
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#define HAL_APC_REQUEST 0
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#define HAL_DPC_REQUEST 1
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/* Conversion functions */
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#define BCD_INT(bcd) \
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(((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
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#define INT_BCD(int) \
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(UCHAR)(((int / 10) << 4) + (int % 10))
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/* adapter.c */
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PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
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/* bus.c */
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VOID NTAPI HalpInitNonBusHandler (VOID);
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/* irql.c */
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VOID NTAPI HalpInitPICs(VOID);
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|
||||
/* udelay.c */
|
||||
VOID NTAPI HalpInitializeClock(VOID);
|
||||
|
||||
/* pci.c */
|
||||
VOID HalpInitPciBus (VOID);
|
||||
|
||||
/* dma.c */
|
||||
VOID HalpInitDma (VOID);
|
||||
|
||||
/* Non-generic initialization */
|
||||
VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
|
||||
VOID HalpInitPhase1(VOID);
|
||||
VOID NTAPI HalpClockInterrupt(VOID);
|
||||
|
||||
//
|
||||
// KD Support
|
||||
//
|
||||
VOID
|
||||
NTAPI
|
||||
HalpCheckPowerButton(
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
HalpRegisterKdSupportFunctions(
|
||||
VOID
|
||||
);
|
||||
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
HalpSetupPciDeviceForDebugging(
|
||||
IN PVOID LoaderBlock,
|
||||
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
|
||||
);
|
||||
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
HalpReleasePciDeviceForDebugging(
|
||||
IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
|
||||
);
|
||||
|
||||
//
|
||||
// Memory routines
|
||||
//
|
||||
PVOID
|
||||
NTAPI
|
||||
HalpMapPhysicalMemory64(
|
||||
IN PHYSICAL_ADDRESS PhysicalAddress,
|
||||
IN ULONG NumberPage
|
||||
);
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
HalpUnmapVirtualAddress(
|
||||
IN PVOID VirtualAddress,
|
||||
IN ULONG NumberPages
|
||||
);
|
||||
|
||||
/* sysinfo.c */
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
HaliQuerySystemInformation(
|
||||
IN HAL_QUERY_INFORMATION_CLASS InformationClass,
|
||||
IN ULONG BufferSize,
|
||||
IN OUT PVOID Buffer,
|
||||
OUT PULONG ReturnedLength
|
||||
);
|
||||
|
||||
NTSTATUS
|
||||
NTAPI
|
||||
HaliSetSystemInformation(
|
||||
IN HAL_SET_INFORMATION_CLASS InformationClass,
|
||||
IN ULONG BufferSize,
|
||||
IN OUT PVOID Buffer
|
||||
);
|
||||
|
||||
typedef struct tagHALP_HOOKS
|
||||
{
|
||||
void (*InitPciBus)(ULONG BusNumber, PBUS_HANDLER BusHandler);
|
||||
} HALP_HOOKS, *PHALP_HOOKS;
|
||||
|
||||
extern HALP_HOOKS HalpHooks;
|
||||
extern KSPIN_LOCK HalpSystemHardwareLock;
|
||||
|
||||
#endif /* __INTERNAL_HAL_HAL_H */
|
||||
|
|
|
|||
|
|
@ -289,6 +289,10 @@ static __inline__ __attribute__((always_inline)) unsigned long _rotl(const unsig
|
|||
}
|
||||
#endif
|
||||
|
||||
#define _clz(a) \
|
||||
({ ULONG __value, __arg = (a); \
|
||||
asm ("clz\t%0, %1": "=r" (__value): "r" (__arg)); \
|
||||
__value; })
|
||||
|
||||
#endif
|
||||
/* EOF */
|
||||
|
|
|
|||
|
|
@ -16,5 +16,5 @@
|
|||
#define VIC_INT_STATUS (VIC_BASE + 0x00)
|
||||
#define VIC_INT_ENABLE (VIC_BASE + 0x10)
|
||||
#define VIC_INT_CLEAR (VIC_BASE + 0x14)
|
||||
#define VIC_SOFT_INT (VIC_BASE + 0x18
|
||||
#define VIC_SOFT_INT (VIC_BASE + 0x18)
|
||||
#define VIC_SOFT_INT_CLEAR (VIC_BASE + 0x1C)
|
||||
|
|
|
|||
|
|
@ -12,20 +12,20 @@
|
|||
// Timer Registers
|
||||
//
|
||||
#define TIMER_BASE(x) (PVOID)(0xE00E2000 + (x * 0x1000)) /* HACK: freeldr mapped it here */
|
||||
#define TIMER0_LOAD TIMER_BASE(0, 0x00)
|
||||
#define TIMER0_VALUE TIMER_BASE(0, 0x04)
|
||||
#define TIMER0_CONTROL TIMER_BASE(0, 0x08)
|
||||
#define TIMER0_INT_CLEAR TIMER_BASE(0, 0x0C)
|
||||
#define TIMER0_INT_STATUS TIMER_BASE(0, 0x10)
|
||||
#define TIMER0_INT_MASK TIMER_BASE(0, 0x14)
|
||||
#define TIMER0_BACKGROUND_LOAD TIMER_BASE(0, 0x18)
|
||||
#define TIMER1_LOAD TIMER_BASE(1, 0x00)
|
||||
#define TIMER1_VALUE TIMER_BASE(1, 0x04)
|
||||
#define TIMER1_CONTROL TIMER_BASE(1, 0x08)
|
||||
#define TIMER1_INT_CLEAR TIMER_BASE(1, 0x0C)
|
||||
#define TIMER1_INT_STATUS TIMER_BASE(1, 0x10)
|
||||
#define TIMER1_INT_MASK TIMER_BASE(1, 0x14)
|
||||
#define TIMER1_BACKGROUND_LOAD TIMER_BASE(1, 0x18)
|
||||
#define TIMER0_LOAD TIMER_BASE(0) + 0x00
|
||||
#define TIMER0_VALUE TIMER_BASE(0) + 0x04
|
||||
#define TIMER0_CONTROL TIMER_BASE(0) + 0x08
|
||||
#define TIMER0_INT_CLEAR TIMER_BASE(0) + 0x0C
|
||||
#define TIMER0_INT_STATUS TIMER_BASE(0) + 0x10
|
||||
#define TIMER0_INT_MASK TIMER_BASE(0) + 0x14
|
||||
#define TIMER0_BACKGROUND_LOAD TIMER_BASE(1) + 0x18
|
||||
#define TIMER1_LOAD TIMER_BASE(1) + 0x00
|
||||
#define TIMER1_VALUE TIMER_BASE(1) + 0x04
|
||||
#define TIMER1_CONTROL TIMER_BASE(1) + 0x08
|
||||
#define TIMER1_INT_CLEAR TIMER_BASE(1) + 0x0C
|
||||
#define TIMER1_INT_STATUS TIMER_BASE(1) + 0x10
|
||||
#define TIMER1_INT_MASK TIMER_BASE(1) + 0x14
|
||||
#define TIMER1_BACKGROUND_LOAD TIMER_BASE(1) + 0x18
|
||||
|
||||
//
|
||||
// Control Register
|
||||
|
|
@ -34,13 +34,14 @@ typedef union _SP804_CONTROL_REGISTER
|
|||
{
|
||||
struct
|
||||
{
|
||||
ULONG Wrap:1;
|
||||
ULONG OneShot:1;
|
||||
ULONG Wide:1;
|
||||
ULONG Prescale:2;
|
||||
ULONG Reserved:1;
|
||||
ULONG Interrupt:1;
|
||||
ULONG Periodic:1;
|
||||
ULONG Enabled:1;
|
||||
ULONG Unused:24;
|
||||
};
|
||||
ULONG AsUlong;
|
||||
} SP804_CONTROL_REGISTER, *PSP804_CONTROL_REGISTER;
|
||||
|
|
|
|||
Loading…
Reference in a new issue