[SDK] Add CPUID and MSR definitions for x86/x64

- Import definitions from edk2 (see https://github.com/tianocore/edk2/tree/master/MdePkg/Include/Register) - Add additional unions as well as AMD SVM CPUID
2024-12-28 10:04:49 +00:00 · 2023-08-27 11:18:40 +03:00 · 2023-08-27 11:18:40 +03:00 · 6048ebeff9
commit 6048ebeff9
parent 70f6ed8ee3
5 changed files with 11644 additions and 0 deletions
--- a/sdk/include/reactos/x86x64/Amd/Cpuid.h
+++ b/sdk/include/reactos/x86x64/Amd/Cpuid.h
@ -0,0 +1,733 @@
+/** @file
+  CPUID leaf definitions.
+
+  Provides defines for CPUID leaf indexes.  Data structures are provided for
+  registers returned by a CPUID leaf that contain one or more bit fields.
+  If a register returned is a single 32-bit value, then a data structure is
+  not provided for that register.
+
+  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
+
+**/
+
+#ifndef __AMD_CPUID_H__
+#define __AMD_CPUID_H__
+
+/**
+CPUID Signature Information
+
+@param   EAX  CPUID_SIGNATURE (0x00)
+
+@retval  EAX  Returns the highest value the CPUID instruction recognizes for
+              returning basic processor information. The value is returned is
+              processor specific.
+@retval  EBX  First 4 characters of a vendor identification string.
+@retval  ECX  Last 4 characters of a vendor identification string.
+@retval  EDX  Middle 4 characters of a vendor identification string.
+
+**/
+
+///
+/// @{ CPUID signature values returned by AMD processors
+///
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX  SIGNATURE_32 ('A', 'u', 't', 'h')
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX  SIGNATURE_32 ('e', 'n', 't', 'i')
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX  SIGNATURE_32 ('c', 'A', 'M', 'D')
+///
+/// @}
+///
+
+/**
+  CPUID Extended Processor Signature and Features
+
+  @param   EAX  CPUID_EXTENDED_CPU_SIG (0x80000001)
+
+  @retval  EAX  Extended Family, Model, Stepping Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
+  @retval  EBX  Brand Identifier
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
+  @retval  ECX  Extended Feature Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
+  @retval  EDX  Extended Feature Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
+**/
+
+/**
+  CPUID Extended Processor Signature and Features EAX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Stepping.
+    ///
+    UINT32    Stepping   : 4;
+    ///
+    /// [Bits 7:4] Base Model.
+    ///
+    UINT32    BaseModel  : 4;
+    ///
+    /// [Bits 11:8] Base Family.
+    ///
+    UINT32    BaseFamily : 4;
+    ///
+    /// [Bit 15:12] Reserved.
+    ///
+    UINT32    Reserved1  : 4;
+    ///
+    /// [Bits 19:16] Extended Model.
+    ///
+    UINT32    ExtModel   : 4;
+    ///
+    /// [Bits 27:20] Extended Family.
+    ///
+    UINT32    ExtFamily  : 8;
+    ///
+    /// [Bit 31:28] Reserved.
+    ///
+    UINT32    Reserved2  : 4;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EAX;
+
+/**
+  CPUID Extended Processor Signature and Features EBX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 27:0] Reserved.
+    ///
+    UINT32    Reserved : 28;
+    ///
+    /// [Bit 31:28] Package Type.
+    ///
+    UINT32    PkgType  : 4;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EBX;
+
+/**
+  CPUID Extended Processor Signature and Features ECX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LAHF/SAHF available in 64-bit mode.
+    ///
+    UINT32    LAHF_SAHF               : 1;
+    ///
+    /// [Bit 1] Core multi-processing legacy mode.
+    ///
+    UINT32    CmpLegacy               : 1;
+    ///
+    /// [Bit 2] Secure Virtual Mode feature.
+    ///
+    UINT32    SVM                     : 1;
+    ///
+    /// [Bit 3] Extended APIC register space.
+    ///
+    UINT32    ExtApicSpace            : 1;
+    ///
+    /// [Bit 4] LOCK MOV CR0 means MOV CR8.
+    ///
+    UINT32    AltMovCr8               : 1;
+    ///
+    /// [Bit 5] LZCNT instruction support.
+    ///
+    UINT32    LZCNT                   : 1;
+    ///
+    /// [Bit 6] SSE4A instruction support.
+    ///
+    UINT32    SSE4A                   : 1;
+    ///
+    /// [Bit 7] Misaligned SSE Mode.
+    ///
+    UINT32    MisAlignSse             : 1;
+    ///
+    /// [Bit 8] ThreeDNow Prefetch instructions.
+    ///
+    UINT32    PREFETCHW               : 1;
+    ///
+    /// [Bit 9] OS Visible Work-around support.
+    ///
+    UINT32    OSVW                    : 1;
+    ///
+    /// [Bit 10] Instruction Based Sampling.
+    ///
+    UINT32    IBS                     : 1;
+    ///
+    /// [Bit 11] Extended Operation Support.
+    ///
+    UINT32    XOP                     : 1;
+    ///
+    /// [Bit 12] SKINIT and STGI support.
+    ///
+    UINT32    SKINIT                  : 1;
+    ///
+    /// [Bit 13] Watchdog Timer support.
+    ///
+    UINT32    WDT                     : 1;
+    ///
+    /// [Bit 14] Reserved.
+    ///
+    UINT32    Reserved1               : 1;
+    ///
+    /// [Bit 15] Lightweight Profiling support.
+    ///
+    UINT32    LWP                     : 1;
+    ///
+    /// [Bit 16] 4-Operand FMA instruction support.
+    ///
+    UINT32    FMA4                    : 1;
+    ///
+    /// [Bit 17] Translation Cache Extension.
+    ///
+    UINT32    TCE                     : 1;
+    ///
+    /// [Bit 21:18] Reserved.
+    ///
+    UINT32    Reserved2               : 4;
+    ///
+    /// [Bit 22] Topology Extensions support.
+    ///
+    UINT32    TopologyExtensions      : 1;
+    ///
+    /// [Bit 23] Core Performance Counter Extensions.
+    ///
+    UINT32    PerfCtrExtCore          : 1;
+    ///
+    /// [Bit 25:24] Reserved.
+    ///
+    UINT32    Reserved3               : 2;
+    ///
+    /// [Bit 26] Data Breakpoint Extension.
+    ///
+    UINT32    DataBreakpointExtension : 1;
+    ///
+    /// [Bit 27] Performance Time-Stamp Counter.
+    ///
+    UINT32    PerfTsc                 : 1;
+    ///
+    /// [Bit 28] L3 Performance Counter Extensions.
+    ///
+    UINT32    PerfCtrExtL3            : 1;
+    ///
+    /// [Bit 29] MWAITX and MONITORX capability.
+    ///
+    UINT32    MwaitExtended           : 1;
+    ///
+    /// [Bit 31:30] Reserved.
+    ///
+    UINT32    Reserved4               : 2;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_ECX;
+
+/**
+  CPUID Extended Processor Signature and Features EDX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] x87 floating point unit on-chip.
+    ///
+    UINT32    FPU            : 1;
+    ///
+    /// [Bit 1] Virtual-mode enhancements.
+    ///
+    UINT32    VME            : 1;
+    ///
+    /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
+    ///
+    UINT32    DE             : 1;
+    ///
+    /// [Bit 3] Page-size extensions (4 MB pages).
+    ///
+    UINT32    PSE            : 1;
+    ///
+    /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
+    ///
+    UINT32    TSC            : 1;
+    ///
+    /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
+    ///
+    UINT32    MSR            : 1;
+    ///
+    /// [Bit 6] Physical-address extensions (PAE).
+    ///
+    UINT32    PAE            : 1;
+    ///
+    /// [Bit 7] Machine check exception, CR4.MCE.
+    ///
+    UINT32    MCE            : 1;
+    ///
+    /// [Bit 8] CMPXCHG8B instruction.
+    ///
+    UINT32    CMPXCHG8B      : 1;
+    ///
+    /// [Bit 9] APIC exists and is enabled.
+    ///
+    UINT32    APIC           : 1;
+    ///
+    /// [Bit 10] Reserved.
+    ///
+    UINT32    Reserved1      : 1;
+    ///
+    /// [Bit 11] SYSCALL and SYSRET instructions.
+    ///
+    UINT32    SYSCALL_SYSRET : 1;
+    ///
+    /// [Bit 12] Memory-type range registers.
+    ///
+    UINT32    MTRR           : 1;
+    ///
+    /// [Bit 13] Page global extension, CR4.PGE.
+    ///
+    UINT32    PGE            : 1;
+    ///
+    /// [Bit 14] Machine check architecture, MCG_CAP.
+    ///
+    UINT32    MCA            : 1;
+    ///
+    /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
+    ///
+    UINT32    CMOV           : 1;
+    ///
+    /// [Bit 16] Page attribute table.
+    ///
+    UINT32    PAT            : 1;
+    ///
+    /// [Bit 17] Page-size extensions.
+    ///
+    UINT32    PSE36          : 1;
+    ///
+    /// [Bit 19:18] Reserved.
+    ///
+    UINT32    Reserved2      : 2;
+    ///
+    /// [Bit 20] No-execute page protection.
+    ///
+    UINT32    NX             : 1;
+    ///
+    /// [Bit 21] Reserved.
+    ///
+    UINT32    Reserved3      : 1;
+    ///
+    /// [Bit 22] AMD Extensions to MMX instructions.
+    ///
+    UINT32    MmxExt         : 1;
+    ///
+    /// [Bit 23] MMX instructions.
+    ///
+    UINT32    MMX            : 1;
+    ///
+    /// [Bit 24] FXSAVE and FXRSTOR instructions.
+    ///
+    UINT32    FFSR           : 1;
+    ///
+    /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
+    ///
+    UINT32    FFXSR          : 1;
+    ///
+    /// [Bit 26] 1-GByte large page support.
+    ///
+    UINT32    Page1GB        : 1;
+    ///
+    /// [Bit 27] RDTSCP instructions.
+    ///
+    UINT32    RDTSCP         : 1;
+    ///
+    /// [Bit 28] Reserved.
+    ///
+    UINT32    Reserved4      : 1;
+    ///
+    /// [Bit 29] Long Mode.
+    ///
+    UINT32    LM             : 1;
+    ///
+    /// [Bit 30] 3DNow! instructions.
+    ///
+    UINT32    ThreeDNow      : 1;
+    ///
+    /// [Bit 31] AMD Extensions to 3DNow! instructions.
+    ///
+    UINT32    ThreeDNowExt   : 1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EDX;
+
+/**
+CPUID Linear Physical Address Size
+
+@param   EAX  CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
+
+@retval  EAX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
+@retval  EBX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
+@retval  ECX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
+@retval  EDX  Reserved.
+**/
+
+/**
+  CPUID Linear Physical Address Size EAX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Maximum physical byte address size in bits.
+    ///
+    UINT32    PhysicalAddressBits : 8;
+    ///
+    /// [Bits 15:8] Maximum linear byte address size in bits.
+    ///
+    UINT32    LinearAddressBits   : 8;
+    ///
+    /// [Bits 23:16] Maximum guest physical byte address size in bits.
+    ///
+    UINT32    GuestPhysAddrSize   : 8;
+    ///
+    /// [Bit 31:24] Reserved.
+    ///
+    UINT32    Reserved            : 8;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;
+
+/**
+  CPUID Linear Physical Address Size EBX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 0] Clear Zero Instruction.
+    ///
+    UINT32    CLZERO     : 1;
+    ///
+    /// [Bits 1] Instructions retired count support.
+    ///
+    UINT32    IRPerf     : 1;
+    ///
+    /// [Bits 2] Restore error pointers for XSave instructions.
+    ///
+    UINT32    XSaveErPtr : 1;
+    ///
+    /// [Bit 31:3] Reserved.
+    ///
+    UINT32    Reserved   : 29;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;
+
+/**
+  CPUID Linear Physical Address Size ECX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Number of threads - 1.
+    ///
+    UINT32    NC               : 8;
+    ///
+    /// [Bit 11:8] Reserved.
+    ///
+    UINT32    Reserved1        : 4;
+    ///
+    /// [Bits 15:12] APIC ID size.
+    ///
+    UINT32    ApicIdCoreIdSize : 4;
+    ///
+    /// [Bits 17:16] Performance time-stamp counter size.
+    ///
+    UINT32    PerfTscSize      : 2;
+    ///
+    /// [Bit 31:18] Reserved.
+    ///
+    UINT32    Reserved2        : 14;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;
+
+/**
+  CPUID AMD Processor Topology
+
+  @param   EAX  CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
+
+  @retval  EAX  Extended APIC ID described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
+  @retval  EBX  Core Identifiers described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
+  @retval  ECX  Node Identifiers described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
+  @retval  EDX  Reserved.
+**/
+#define CPUID_AMD_PROCESSOR_TOPOLOGY  0x8000001E
+
+/**
+  CPUID AMD Processor Topology EAX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Extended APIC Id.
+    ///
+    UINT32    ExtendedApicId;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
+
+/**
+  CPUID AMD Processor Topology EBX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Core Id.
+    ///
+    UINT32    CoreId         : 8;
+    ///
+    /// [Bits 15:8] Threads per core.
+    ///
+    UINT32    ThreadsPerCore : 8;
+    ///
+    /// [Bit 31:16] Reserved.
+    ///
+    UINT32    Reserved       : 16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
+
+/**
+  CPUID AMD Processor Topology ECX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Node Id.
+    ///
+    UINT32    NodeId            : 8;
+    ///
+    /// [Bits 10:8] Nodes per processor.
+    ///
+    UINT32    NodesPerProcessor : 3;
+    ///
+    /// [Bit 31:11] Reserved.
+    ///
+    UINT32    Reserved          : 21;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
+
+/**
+  CPUID Memory Encryption Information
+
+  @param   EAX  CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
+
+  @retval  EAX  Returns the memory encryption feature support status.
+  @retval  EBX  If memory encryption feature is present then return
+                the page table bit number used to enable memory encryption support
+                and reducing of physical address space in bits.
+  @retval  ECX  Returns number of encrypted guest supported simultaneously.
+  @retval  EDX  Returns minimum SEV enabled and SEV disabled ASID.
+
+  <b>Example usage</b>
+  @code
+  UINT32 Eax;
+  UINT32 Ebx;
+  UINT32 Ecx;
+  UINT32 Edx;
+
+  AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);
+  @endcode
+**/
+
+#define CPUID_MEMORY_ENCRYPTION_INFO  0x8000001F
+
+/**
+  CPUID Memory Encryption support information EAX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Secure Memory Encryption (Sme) Support
+    ///
+    UINT32    SmeBit          : 1;
+
+    ///
+    /// [Bit 1] Secure Encrypted Virtualization (Sev) Support
+    ///
+    UINT32    SevBit          : 1;
+
+    ///
+    /// [Bit 2] Page flush MSR support
+    ///
+    UINT32    PageFlushMsrBit : 1;
+
+    ///
+    /// [Bit 3] Encrypted state support
+    ///
+    UINT32    SevEsBit        : 1;
+
+    ///
+    /// [Bit 31:4] Reserved
+    ///
+    UINT32    ReservedBits    : 28;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EAX;
+
+/**
+  CPUID Memory Encryption support information EBX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 5:0] Page table bit number used to enable memory encryption
+    ///
+    UINT32    PtePosBits      : 6;
+
+    ///
+    /// [Bit 11:6] Reduction of system physical address space bits when
+    ///  memory encryption is enabled
+    ///
+    UINT32    ReducedPhysBits : 5;
+
+    ///
+    /// [Bit 31:12] Reserved
+    ///
+    UINT32    ReservedBits    : 21;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EBX;
+
+/**
+  CPUID Memory Encryption support information ECX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Number of encrypted guest supported simultaneously
+    ///
+    UINT32    NumGuests;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_ECX;
+
+/**
+  CPUID Memory Encryption support information EDX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
+    ///
+    UINT32    MinAsid;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EDX;
+
+#endif
--- a/sdk/include/reactos/x86x64/Cpuid.h
+++ b/sdk/include/reactos/x86x64/Cpuid.h
@ -0,0 +1,205 @@
+
+#define CHAR8 char
+
+#include "Intel/Cpuid.h"
+#include "Amd/Cpuid.h"
+
+// CPUID_SIGNATURE (0)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        UINT32 MaxLeaf;
+        CHAR SignatureScrambled[12];
+    };
+} CPUID_SIGNATURE_REGS;
+
+// CPUID_VERSION_INFO (1)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_VERSION_INFO_EAX Eax;
+        CPUID_VERSION_INFO_EBX Ebx;
+        CPUID_VERSION_INFO_ECX Ecx;
+        CPUID_VERSION_INFO_EDX Edx;
+    };
+} CPUID_VERSION_INFO_REGS;
+
+// CPUID_EXTENDED_FUNCTION (0x80000000)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        UINT32 MaxLeaf;
+        UINT32 ReservedEbx;
+        UINT32 ReservedEcx;
+        UINT32 ReservedEdx;
+    };
+} CPUID_EXTENDED_FUNCTION_REGS;
+
+// CPUID_THERMAL_POWER_MANAGEMENT (6)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
+        CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
+        CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
+        UINT32 ReservedEdx;
+    };
+    struct
+    {
+        UINT32 Eax;
+        UINT32 Ebx;
+        struct
+        {
+            UINT32 HardwareCoordinationFeedback : 1;
+            UINT32 ACNT2 : 1; // See https://en.wikipedia.org/wiki/CPUID
+        } Ecx;
+    } Undoc;
+} CPUID_THERMAL_POWER_MANAGEMENT_REGS;
+
+// CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        UINT32 Eax;
+        CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
+        CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
+        CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx;
+    };
+} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_REGS;
+
+// CPUID_EXTENDED_STATE (0x0D)
+// CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
+        UINT32 Ebx;
+        UINT32 Ecx;
+        UINT32 Edx;
+    };
+} CPUID_EXTENDED_STATE_MAIN_LEAF_REGS;
+
+// CPUID_EXTENDED_STATE (0x0D)
+// CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
+        struct
+        {
+            UINT32 XSaveAreaSize; // The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
+        } Ebx;
+        CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
+        struct
+        {
+            UINT32 Edx; // Reports the supported bits of the upper 32 bits of the IA32_XSS MSR.IA32_XSS[n + 32] can be set to 1 only if EDX[n] is 1.
+        } Edx;
+    };
+} CPUID_EXTENDED_STATE_SUB_LEAF_EAX_REGS;
+
+// CPUID_EXTENDED_CPU_SIG (0x80000001)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        UINT32 Signature;
+        UINT32 ReservedEbx;
+        CPUID_EXTENDED_CPU_SIG_ECX Ecx;
+        CPUID_EXTENDED_CPU_SIG_EDX Edx;
+    } Intel;
+    struct
+    {
+        CPUID_AMD_EXTENDED_CPU_SIG_EAX Eax;
+        CPUID_AMD_EXTENDED_CPU_SIG_EBX Ebx;
+        CPUID_AMD_EXTENDED_CPU_SIG_ECX Ecx;
+        CPUID_AMD_EXTENDED_CPU_SIG_EDX Edx;
+    } Amd;
+} CPUID_EXTENDED_CPU_SIG_REGS;
+
+
+// Additional AMD specific CPUID:
+// See
+// - AMD64 Architecture Programmer’s Manual Volume 2: System Programming (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf)
+// - http://www.flounder.com/cpuid_explorer2.htm#CPUID(0x8000000A)
+// - https://www.spinics.net/lists/kvm/msg279165.html
+// - https://qemu-devel.nongnu.narkive.com/zgmvxGLq/patch-0-3-svm-feature-support-for-qemu
+// - https://github.com/torvalds/linux/blob/28f20a19294da7df158dfca259d0e2b5866baaf9/arch/x86/include/asm/cpufeatures.h#L361
+
+#define CPUID_AMD_SVM_FEATURES 0x8000000A
+
+typedef union
+{
+    struct
+    {
+        UINT SVMRev : 8;     // EAX[7..0]
+        UINT Reserved : 24;  // EAX[31..8]
+    } Bits;
+
+    UINT32    Uint32;
+} CPUID_AMD_SVM_FEATURES_EAX;
+
+typedef union
+{
+    struct
+    {
+        UINT32 NP : 1; // EDX[0] Nested paging support
+        UINT32 LbrVirt : 1; // EDX[1] LBR virtualization
+        UINT32 SVML : 1; // EDX[2] SVM Lock
+        UINT32 NRIPS : 1; // EDX[3] Next RIP save on VMEXIT
+        UINT32 TscRateMsr : 1; // EDX[4] MSR based TSC ratio control
+        UINT32 VmcbClean : 1; // EDX[5] VMCB Clean bits support
+        UINT32 FlushByAsid : 1; // EDX[6] Flush by ASID support
+        UINT32 DecodeAssists : 1; // EDX[7] Decode assists support
+        UINT32 Reserved1 : 2; // EDX[9:8]   Reserved
+        UINT32 PauseFilter : 1; // EDX[10] Pause filter support
+        UINT32 Reserved2 : 1; // EDX[11] Reserved
+        UINT32 PauseFilterThreshold : 1; // EDX[12] Pause filter threshold support
+        UINT32 AVIC : 1; // EDX[13:13] Advanced Virtual Interrupt Controller
+        UINT32 Unknown14 : 1; // EDX[14] Unknown. Described in AMD doc as X2AVIC, but that was probably a typo, since x2AVIC is bit 18.
+        UINT32 VMSAVEVirt : 1; // EDX[15] MSAVE and VMLOAD Virtualization
+        UINT32 VGIF : 1; // EDX[16] Virtual Global-Interrupt Flag
+        UINT32 GMET : 1; // EDX[17] Guest Mode Execute Trap Extension
+        UINT32 x2AVIC : 1; // EDX[18] Virtual x2APIC
+        UINT32 SSSCheck : 1; // EDX[19] AKA SupervisorShadowStack
+        UINT32 V_SPEC_CTRL : 1; // EDX[20] Virtual SPEC_CTRL
+        UINT32 ROGPT : 1; // EDX[21]
+        UINT32 Unknown22 : 1; // EDX[22]
+        UINT32 HOST_MCE_OVERRIDE : 1; // EDX[23]
+        UINT32 TLBSYNC : 1; // EDX[24] TLBSYNC instruction can be intercepted
+        UINT32 VNMI : 1; // EDX[25] NMI Virtualization support
+        UINT32 IbsVirt : 1; // EDX[26] Instruction Based Sampling Virtualization
+        UINT32 LVTReadAllowed : 1; // EDX[27]
+        UINT32 Unknown28 : 1; // EDX[28]
+        UINT32 BusLockThreshold : 1; // EDX[29]
+    } Bits;
+
+    UINT32    Uint32;
+} CPUID_AMD_SVM_FEATURES_EDX;
+
+// CPUID_AMD_SVM_FEATURES (0x8000000A)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_AMD_SVM_FEATURES_EAX Eax;
+        UINT32 NumberOfSupportedASIDs;
+        UINT32 Ecx;
+        CPUID_AMD_SVM_FEATURES_EDX Edx;
+    };
+} CPUID_AMD_SVM_FEATURES_REGS;
--- a/sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h
+++ b/sdk/include/reactos/x86x64/Intel/ArchitecturalMsr.h
--- a/sdk/include/reactos/x86x64/Intel/Cpuid.h
+++ b/sdk/include/reactos/x86x64/Intel/Cpuid.h
--- a/sdk/include/reactos/x86x64/Msr.h
+++ b/sdk/include/reactos/x86x64/Msr.h
@ -0,0 +1,91 @@
+
+#define SIZE_2KB 2048
+
+#include "Intel/ArchitecturalMsr.h"
+
+typedef struct
+{
+    UINT32 Reserved0 : 2; // [1:0] Reserved
+    UINT32 InterruptWindowExiting : 1; // [2] Interrupt window exiting
+    UINT32 UseTSCOffsetting : 1; // [3] Use TSC offsetting
+    UINT32 Reserved4 : 3; // [6..4] Reserved
+    UINT32 HLTExiting : 1; // [7] HLT exiting
+    UINT32 Reserved8 : 1; // [8] Reserved
+    UINT32 INVLPG_Exiting : 1; // [9] INVLPG exiting
+    UINT32 MWAIT_Exiting : 1; // [10] MWAIT exiting
+    UINT32 RDPMC_Exiting : 1; // [11] RDPMC exiting
+    UINT32 RDTSC_Exiting : 1; // [12] RDTSC exiting
+    UINT32 CR3_Load_Exiting : 1; // [15] CR3 load exiting
+    UINT32 CR3_Store_Exiting : 1; // [16] CR3 store exiting
+    UINT32 ActivateTertiaryControls : 1; // [17] Activate tertiary controls
+    UINT32 CR8_Load_Exiting : 1; // [19] CR8 load exiting
+    UINT32 CR8_Store_Exiting : 1; // [20] CR8 store exiting
+    UINT32 Use_TPR_Shadow : 1; // [21] Use TPR shadow
+    UINT32 NMI_Window_Exiting : 1; // [22] NMI window exiting
+    UINT32 MOV_DR_Exiting : 1; // [23] MOV DR exiting
+    UINT32 Unconditional_IO_Exiting : 1; // [24] Unconditional I/O exiting
+    UINT32 Use_IO_Bitmaps : 1; // [25] Use I/O bitmaps 
+    UINT32 Monitor_Trap_Flag : 1; // [27] Monitor trap flag
+    UINT32 Use_MSR_Bitmap : 1; // [28] Use MSR bitmap
+    UINT32 MONITOR_Exiting : 1; // [29] MONITOR exiting
+    UINT32 PAUSE_Exiting : 1; // [30] PAUSE exiting
+    UINT32 ActivateSecondaryControls : 1; // [31] Activate secondary controls
+} VMX_PROCBASED_CTRLS;
+
+typedef struct
+{
+    UINT32 VirtualizeApicAccesses : 1; // [0] Virtualize APIC accesses 
+    UINT32 EPT : 1; // [1] Enable EPT
+    UINT32 DescriptorTable_Exiting : 1; // [2] Descriptor-table exiting
+    UINT32 RDTSCP : 1; // [3] Enable RDTSCP
+    UINT32 Virtualize_x2APIC : 1; // [4] Virtualize x2APIC mode
+    UINT32 VPID : 1; // [5] Enable VPID
+    UINT32 WBINVD_Exiting : 1; // [6] WBINVD exiting
+    UINT32 UnrestrictedGuest : 1; // [7] Unrestricted guest
+    UINT32 APIC_Virtualization : 1; // [8] APIC-register virtualization
+    UINT32 VirtualInterruptDelivery : 1; // [9] Virtual-interrupt delivery
+    UINT32 PAUSE_Loop_Exiting : 1; // [10] PAUSE-loop exiting
+    UINT32 RDRAND_Exiting : 1; // [11] RDRAND exiting
+    UINT32 INVPCID : 1; // [12] Enable INVPCID
+    UINT32 VM_Functions : 1; // [13] Enable VM functions
+    UINT32 VMCS_Shadowing : 1; //  [14] VMCS shadowing
+    UINT32 ENCLS_Exiting : 1; // [15] Enable ENCLS exiting
+    UINT32 RDSEED_Exiting : 1; // [16] RDSEED exiting
+    UINT32 PML : 1; // [17] Enable PML
+    UINT32 EPT_Violation : 1; // [18] EPT-violation #VE
+    UINT32 Conceal_VMX_from_PT : 1; // [19] Conceal VMX from PT
+    UINT32 XSAVES : 1; // [20] Enable XSAVES / XRSTORS
+    UINT32 PASID_Translation : 1; // [21] PASID translation
+    UINT32 ModeBasedExecutionControl : 1; // [22] Mode-based execute control for EPT
+    UINT32 SubPageWritePerm : 1; // [23] Sub-page write permissions for EPT
+    UINT32 GuestPhysicalAddr : 1; // [24] Intel PT uses guest physical addresses
+    UINT32 TSC_Scaling : 1; // [25] Use TSC scaling
+    UINT32 User_Wait : 1; // [26] Enable user wait and pause
+    UINT32 PCONFIG : 1; // [27] Enable PCONFIG
+    UINT32 ENCLV_Exiting : 1; // [28] Enable ENCLV exiting
+    UINT32 VMM_Bus_Lock_Detection : 1; // [30] VMM bus-lock detection
+    UINT32 InstructionTimeout : 1; // [31] Instruction timeout
+} VMX_PROCBASED_CTLS2;
+
+typedef union
+{
+    struct
+    {
+        VMX_PROCBASED_CTRLS Allowed0;
+        VMX_PROCBASED_CTRLS Allowed1;
+    } Bits;
+
+    UINT64    Uint64;
+} MSR_IA32_VMX_PROCBASED_CTLS_REGISTER;
+
+
+typedef union
+{
+    struct
+    {
+        VMX_PROCBASED_CTLS2 Allowed0;
+        VMX_PROCBASED_CTLS2 Allowed1;
+    } Bits;
+
+    UINT64    Uint64;
+} MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER;