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https://github.com/reactos/reactos.git
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- Fix Unix line breaks.
- Use HAL PCI bus routines in order avoid race conditions. - Use slot number to distinguish multiple device of the same kind. svn path=/trunk/; revision=6980
This commit is contained in:
Eric Kohl
parent
0dc6bcee53
commit
6010d1fd63
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@ -1,4 +1,4 @@
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/* $Id: fdo.c,v 1.4 2003/11/24 16:15:00 gvg Exp $
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/* $Id: fdo.c,v 1.5 2003/12/12 21:54:42 ekohl Exp $
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*
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* PROJECT: ReactOS PCI bus driver
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* FILE: fdo.c
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@ -7,30 +7,39 @@
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* UPDATE HISTORY:
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* 10-09-2001 CSH Created
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*/
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#include <pci.h>
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#include <ddk/ntddk.h>
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#include "pcidef.h"
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#include "pci.h"
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#define NDEBUG
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#include <debug.h>
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/*** PRIVATE *****************************************************************/
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NTSTATUS
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static NTSTATUS
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FdoLocateChildDevice(
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PPCI_DEVICE *Device,
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PFDO_DEVICE_EXTENSION DeviceExtension,
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PCI_SLOT_NUMBER SlotNumber,
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PPCI_COMMON_CONFIG PciConfig)
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{
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PLIST_ENTRY CurrentEntry;
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PPCI_DEVICE CurrentDevice;
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DPRINT("Called\n");
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CurrentEntry = DeviceExtension->DeviceListHead.Flink;
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while (CurrentEntry != &DeviceExtension->DeviceListHead) {
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CurrentDevice = CONTAINING_RECORD(CurrentEntry, PCI_DEVICE, ListEntry);
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/* If both vendor ID and device ID match, it is the same device */
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if ((PciConfig->VendorID == CurrentDevice->PciConfig.VendorID) &&
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(PciConfig->DeviceID == CurrentDevice->PciConfig.DeviceID)) {
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(PciConfig->DeviceID == CurrentDevice->PciConfig.DeviceID) &&
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(SlotNumber.u.AsULONG == CurrentDevice->SlotNumber.u.AsULONG)) {
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*Device = CurrentDevice;
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DPRINT("Done\n");
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return STATUS_SUCCESS;
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}
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@ -38,11 +47,12 @@ FdoLocateChildDevice(
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}
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*Device = NULL;
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DPRINT("Done\n");
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return STATUS_UNSUCCESSFUL;
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}
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NTSTATUS
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static NTSTATUS
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FdoEnumerateDevices(
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PDEVICE_OBJECT DeviceObject)
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{
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@ -50,9 +60,11 @@ FdoEnumerateDevices(
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PCI_COMMON_CONFIG PciConfig;
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PLIST_ENTRY CurrentEntry;
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PPCI_DEVICE Device;
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NTSTATUS Status;
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ULONG Slot;
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PCI_SLOT_NUMBER SlotNumber;
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ULONG DeviceNumber;
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ULONG FunctionNumber;
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ULONG Size;
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NTSTATUS Status;
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DPRINT("Called\n");
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@ -70,25 +82,42 @@ FdoEnumerateDevices(
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DeviceExtension->DeviceListCount = 0;
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/* Enumerate devices on the PCI bus */
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for (Slot = 0; Slot < 256; Slot++)
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{
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Size = PciGetBusData(
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DeviceExtension->BusNumber,
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Slot,
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&PciConfig,
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0,
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sizeof(PCI_COMMON_CONFIG));
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if (Size != 0)
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SlotNumber.u.AsULONG = 0;
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for (DeviceNumber = 0; DeviceNumber < PCI_MAX_DEVICES; DeviceNumber++)
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{
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SlotNumber.u.bits.DeviceNumber = DeviceNumber;
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for (FunctionNumber = 0; FunctionNumber < PCI_MAX_FUNCTION; FunctionNumber++)
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{
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DPRINT("Bus %1lu Device %2lu Func %1lu VenID 0x%04hx DevID 0x%04hx\n",
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DeviceExtension->BusNumber,
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Slot>>3,
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Slot & 0x07,
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PciConfig.VendorID,
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PciConfig.DeviceID);
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SlotNumber.u.bits.FunctionNumber = FunctionNumber;
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Status = FdoLocateChildDevice(&Device, DeviceExtension, &PciConfig);
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if (!NT_SUCCESS(Status)) {
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Size= HalGetBusData(PCIConfiguration,
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DeviceExtension->BusNumber,
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SlotNumber.u.AsULONG,
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&PciConfig,
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sizeof(PCI_COMMON_CONFIG));
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DPRINT("Size %lu\n", Size);
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if (Size < sizeof(PCI_COMMON_CONFIG))
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{
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if (FunctionNumber == 0)
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{
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break;
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}
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else
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{
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continue;
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}
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}
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DPRINT("Bus %1lu Device %2lu Func %1lu VenID 0x%04hx DevID 0x%04hx\n",
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DeviceExtension->BusNumber,
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DeviceNumber,
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FunctionNumber,
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PciConfig.VendorID,
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PciConfig.DeviceID);
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Status = FdoLocateChildDevice(&Device, DeviceExtension, SlotNumber, &PciConfig);
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if (!NT_SUCCESS(Status))
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{
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Device = (PPCI_DEVICE)ExAllocatePool(PagedPool, sizeof(PCI_DEVICE));
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if (!Device)
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{
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@ -96,9 +125,16 @@ FdoEnumerateDevices(
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return STATUS_INSUFFICIENT_RESOURCES;
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}
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RtlZeroMemory(Device, sizeof(PCI_DEVICE));
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RtlZeroMemory (Device,
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sizeof(PCI_DEVICE));
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RtlMoveMemory(&Device->PciConfig, &PciConfig, sizeof(PCI_COMMON_CONFIG));
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RtlCopyMemory (&Device->SlotNumber,
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&SlotNumber,
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sizeof(PCI_SLOT_NUMBER));
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RtlCopyMemory (&Device->PciConfig,
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&PciConfig,
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sizeof(PCI_COMMON_CONFIG));
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ExInterlockedInsertTailList(
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&DeviceExtension->DeviceListHead,
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@ -111,13 +147,15 @@ FdoEnumerateDevices(
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DeviceExtension->DeviceListCount++;
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}
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}
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}
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DPRINT("Done\n");
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return STATUS_SUCCESS;
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}
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NTSTATUS
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static NTSTATUS
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FdoQueryBusRelations(
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IN PDEVICE_OBJECT DeviceObject,
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IN PIRP Irp,
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@ -250,11 +288,13 @@ FdoQueryBusRelations(
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Irp->IoStatus.Information = (ULONG_PTR)Relations;
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DPRINT("Done\n");
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return Status;
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}
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NTSTATUS
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static NTSTATUS
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FdoStartDevice(
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IN PDEVICE_OBJECT DeviceObject,
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IN PIRP Irp)
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@ -271,14 +311,6 @@ FdoStartDevice(
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KeInitializeSpinLock(&DeviceExtension->DeviceListLock);
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DeviceExtension->DeviceListCount = 0;
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PciBusConfigType = PciGetBusConfigType();
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DPRINT("Bus configuration is %d\n", PciBusConfigType);
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if (PciBusConfigType != pbtUnknown) {
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/* At least one PCI bus is found */
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}
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/* FIXME: Find a way to get this information */
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DeviceExtension->BusNumber = 0;
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@ -286,11 +318,11 @@ FdoStartDevice(
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//Irp->IoStatus.Information = 0;
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return STATUS_SUCCESS;
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return STATUS_SUCCESS;
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}
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NTSTATUS
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static NTSTATUS
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FdoSetPower(
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IN PDEVICE_OBJECT DeviceObject,
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IN PIRP Irp,
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@ -1,4 +1,4 @@
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/* $Id: pci.c,v 1.4 2003/11/14 17:13:24 weiden Exp $
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/* $Id: pci.c,v 1.5 2003/12/12 21:54:42 ekohl Exp $
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*
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* PROJECT: ReactOS PCI Bus driver
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* FILE: pci.c
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@ -7,7 +7,11 @@
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* UPDATE HISTORY:
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* 10-09-2001 CSH Created
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*/
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#include <pci.h>
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#include <ddk/ntddk.h>
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#include "pcidef.h"
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#include "pci.h"
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#define NDEBUG
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#include <debug.h>
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@ -24,420 +28,9 @@
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/*** PUBLIC ******************************************************************/
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PCI_BUS_TYPE PciBusConfigType = pbtUnknown;
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/*** PRIVATE *****************************************************************/
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static NTSTATUS
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PciReadConfigUchar(UCHAR Bus,
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UCHAR Slot,
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UCHAR Offset,
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PUCHAR Value)
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{
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switch (PciBusConfigType)
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{
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case pbtType1:
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WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(Bus, Slot, Offset));
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*Value = READ_PORT_UCHAR((PUCHAR)0xCFC + (Offset & 3));
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return STATUS_SUCCESS;
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case pbtType2:
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
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WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
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*Value = READ_PORT_UCHAR((PUCHAR)(IOADDR(Slot, Offset)));
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
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return STATUS_SUCCESS;
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case pbtUnknown:
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break;
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}
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return STATUS_UNSUCCESSFUL;
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}
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static NTSTATUS
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PciReadConfigUshort(UCHAR Bus,
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UCHAR Slot,
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UCHAR Offset,
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PUSHORT Value)
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{
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if ((Offset & 1) != 0)
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{
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return STATUS_INVALID_PARAMETER;
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}
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switch (PciBusConfigType)
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{
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case pbtType1:
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WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(Bus, Slot, Offset));
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*Value = READ_PORT_USHORT((PUSHORT)0xCFC + (Offset & 2));
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return STATUS_SUCCESS;
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case pbtType2:
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
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WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
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*Value = READ_PORT_USHORT((PUSHORT)(IOADDR(Slot, Offset)));
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
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return STATUS_SUCCESS;
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case pbtUnknown:
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break;
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}
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return STATUS_UNSUCCESSFUL;
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}
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static NTSTATUS
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PciReadConfigUlong(UCHAR Bus,
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UCHAR Slot,
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UCHAR Offset,
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PULONG Value)
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{
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if ((Offset & 3) != 0)
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{
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return STATUS_INVALID_PARAMETER;
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}
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switch (PciBusConfigType)
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{
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case pbtType1:
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WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(Bus, Slot, Offset));
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*Value = READ_PORT_ULONG((PULONG)0xCFC);
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return STATUS_SUCCESS;
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case pbtType2:
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
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WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
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*Value = READ_PORT_ULONG((PULONG)(IOADDR(Slot, Offset)));
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
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return STATUS_SUCCESS;
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case pbtUnknown:
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break;
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}
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return STATUS_UNSUCCESSFUL;
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}
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static NTSTATUS
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PciWriteConfigUchar(UCHAR Bus,
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UCHAR Slot,
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UCHAR Offset,
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UCHAR Value)
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{
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switch (PciBusConfigType)
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{
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case pbtType1:
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WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(Bus, Slot, Offset));
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WRITE_PORT_UCHAR((PUCHAR)0xCFC + (Offset&3), Value);
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return STATUS_SUCCESS;
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case pbtType2:
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
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WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
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WRITE_PORT_UCHAR((PUCHAR)(IOADDR(Slot,Offset)), Value);
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
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return STATUS_SUCCESS;
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case pbtUnknown:
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break;
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}
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return STATUS_UNSUCCESSFUL;
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}
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static NTSTATUS
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PciWriteConfigUshort(UCHAR Bus,
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UCHAR Slot,
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UCHAR Offset,
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USHORT Value)
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{
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if ((Offset & 1) != 0)
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{
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return STATUS_INVALID_PARAMETER;
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}
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switch (PciBusConfigType)
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{
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case pbtType1:
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WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(Bus, Slot, Offset));
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WRITE_PORT_USHORT((PUSHORT)0xCFC + (Offset & 2), Value);
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return STATUS_SUCCESS;
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case pbtType2:
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
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WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
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WRITE_PORT_USHORT((PUSHORT)(IOADDR(Slot, Offset)), Value);
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
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return STATUS_SUCCESS;
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case pbtUnknown:
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break;
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}
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return STATUS_UNSUCCESSFUL;
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}
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static NTSTATUS
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PciWriteConfigUlong(UCHAR Bus,
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UCHAR Slot,
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UCHAR Offset,
|
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ULONG Value)
|
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{
|
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if ((Offset & 3) != 0)
|
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{
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return STATUS_INVALID_PARAMETER;
|
||||
}
|
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|
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switch (PciBusConfigType)
|
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{
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case pbtType1:
|
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WRITE_PORT_ULONG((PULONG)0xCF8, CONFIG_CMD(Bus, Slot, Offset));
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WRITE_PORT_ULONG((PULONG)0xCFC, Value);
|
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return STATUS_SUCCESS;
|
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case pbtType2:
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, FUNC(Slot));
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WRITE_PORT_UCHAR((PUCHAR)0xCFA, Bus);
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WRITE_PORT_ULONG((PULONG)(IOADDR(Slot, Offset)), Value);
|
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WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0);
|
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return STATUS_SUCCESS;
|
||||
case pbtUnknown:
|
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break;
|
||||
}
|
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return STATUS_UNSUCCESSFUL;
|
||||
}
|
||||
|
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|
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ULONG
|
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PciGetBusData(ULONG BusNumber,
|
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ULONG SlotNumber,
|
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PVOID Buffer,
|
||||
ULONG Offset,
|
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ULONG Length)
|
||||
{
|
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PVOID Ptr = Buffer;
|
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ULONG Address = Offset;
|
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ULONG Len = Length;
|
||||
ULONG Vendor;
|
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UCHAR HeaderType;
|
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|
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#if 0
|
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DPRINT(" BusNumber %lu\n", BusNumber);
|
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DPRINT(" SlotNumber %lu\n", SlotNumber);
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DPRINT(" Offset 0x%lx\n", Offset);
|
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DPRINT(" Length 0x%lx\n", Length);
|
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#endif
|
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|
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if ((Length == 0) || (PciBusConfigType == 0))
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return 0;
|
||||
|
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/* 0E=PCI_HEADER_TYPE */
|
||||
PciReadConfigUchar(BusNumber,
|
||||
SlotNumber & 0xF8,
|
||||
0x0E,
|
||||
&HeaderType);
|
||||
if (((HeaderType & 0x80) == 0) && ((SlotNumber & 0x07) != 0))
|
||||
return 0;
|
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|
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PciReadConfigUlong(BusNumber,
|
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SlotNumber,
|
||||
0x00,
|
||||
&Vendor);
|
||||
/* some broken boards return 0 if a slot is empty: */
|
||||
if (Vendor == 0xFFFFFFFF || Vendor == 0)
|
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return 0;
|
||||
|
||||
if ((Address & 1) && (Len >= 1))
|
||||
{
|
||||
PciReadConfigUchar(BusNumber,
|
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SlotNumber,
|
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Address,
|
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Ptr);
|
||||
Ptr = Ptr + 1;
|
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Address++;
|
||||
Len--;
|
||||
}
|
||||
|
||||
if ((Address & 2) && (Len >= 2))
|
||||
{
|
||||
PciReadConfigUshort(BusNumber,
|
||||
SlotNumber,
|
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Address,
|
||||
Ptr);
|
||||
Ptr = Ptr + 2;
|
||||
Address += 2;
|
||||
Len -= 2;
|
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}
|
||||
|
||||
while (Len >= 4)
|
||||
{
|
||||
PciReadConfigUlong(BusNumber,
|
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SlotNumber,
|
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Address,
|
||||
Ptr);
|
||||
Ptr = Ptr + 4;
|
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Address += 4;
|
||||
Len -= 4;
|
||||
}
|
||||
|
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if (Len >= 2)
|
||||
{
|
||||
PciReadConfigUshort(BusNumber,
|
||||
SlotNumber,
|
||||
Address,
|
||||
Ptr);
|
||||
Ptr = Ptr + 2;
|
||||
Address += 2;
|
||||
Len -= 2;
|
||||
}
|
||||
|
||||
if (Len >= 1)
|
||||
{
|
||||
PciReadConfigUchar(BusNumber,
|
||||
SlotNumber,
|
||||
Address,
|
||||
Ptr);
|
||||
Ptr = Ptr + 1;
|
||||
Address++;
|
||||
Len--;
|
||||
}
|
||||
|
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return Length - Len;
|
||||
}
|
||||
|
||||
|
||||
ULONG
|
||||
PciSetBusData(ULONG BusNumber,
|
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ULONG SlotNumber,
|
||||
PVOID Buffer,
|
||||
ULONG Offset,
|
||||
ULONG Length)
|
||||
{
|
||||
PVOID Ptr = Buffer;
|
||||
ULONG Address = Offset;
|
||||
ULONG Len = Length;
|
||||
ULONG Vendor;
|
||||
UCHAR HeaderType;
|
||||
|
||||
#if 0
|
||||
DPRINT(" BusNumber %lu\n", BusNumber);
|
||||
DPRINT(" SlotNumber %lu\n", SlotNumber);
|
||||
DPRINT(" Offset 0x%lx\n", Offset);
|
||||
DPRINT(" Length 0x%lx\n", Length);
|
||||
#endif
|
||||
|
||||
if ((Length == 0) || (PciBusConfigType == 0))
|
||||
return 0;
|
||||
|
||||
/* 0E=PCI_HEADER_TYPE */
|
||||
PciReadConfigUchar(BusNumber,
|
||||
SlotNumber & 0xF8,
|
||||
0x0E,
|
||||
&HeaderType);
|
||||
if (((HeaderType & 0x80) == 0) && ((SlotNumber & 0x07) != 0))
|
||||
return 0;
|
||||
|
||||
PciReadConfigUlong(BusNumber,
|
||||
SlotNumber,
|
||||
0x00,
|
||||
&Vendor);
|
||||
/* some broken boards return 0 if a slot is empty: */
|
||||
if (Vendor == 0xFFFFFFFF || Vendor == 0)
|
||||
return 0;
|
||||
|
||||
if ((Address & 1) && (Len >= 1))
|
||||
{
|
||||
PciWriteConfigUchar(BusNumber,
|
||||
SlotNumber,
|
||||
Address,
|
||||
*(PUCHAR)Ptr);
|
||||
Ptr = Ptr + 1;
|
||||
Address++;
|
||||
Len--;
|
||||
}
|
||||
|
||||
if ((Address & 2) && (Len >= 2))
|
||||
{
|
||||
PciWriteConfigUshort(BusNumber,
|
||||
SlotNumber,
|
||||
Address,
|
||||
*(PUSHORT)Ptr);
|
||||
Ptr = Ptr + 2;
|
||||
Address += 2;
|
||||
Len -= 2;
|
||||
}
|
||||
|
||||
while (Len >= 4)
|
||||
{
|
||||
PciWriteConfigUlong(BusNumber,
|
||||
SlotNumber,
|
||||
Address,
|
||||
*(PULONG)Ptr);
|
||||
Ptr = Ptr + 4;
|
||||
Address += 4;
|
||||
Len -= 4;
|
||||
}
|
||||
|
||||
if (Len >= 2)
|
||||
{
|
||||
PciWriteConfigUshort(BusNumber,
|
||||
SlotNumber,
|
||||
Address,
|
||||
*(PUSHORT)Ptr);
|
||||
Ptr = Ptr + 2;
|
||||
Address += 2;
|
||||
Len -= 2;
|
||||
}
|
||||
|
||||
if (Len >= 1)
|
||||
{
|
||||
PciWriteConfigUchar(BusNumber,
|
||||
SlotNumber,
|
||||
Address,
|
||||
*(PUCHAR)Ptr);
|
||||
Ptr = Ptr + 1;
|
||||
Address++;
|
||||
Len--;
|
||||
}
|
||||
|
||||
return Length - Len;
|
||||
}
|
||||
|
||||
|
||||
PCI_BUS_TYPE
|
||||
PciGetBusConfigType(VOID)
|
||||
{
|
||||
ULONG Value;
|
||||
|
||||
DPRINT("Called\n");
|
||||
|
||||
DPRINT("Checking configuration type 1:\n");
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xCFB, 0x01);
|
||||
Value = READ_PORT_ULONG((PULONG)0xCF8);
|
||||
WRITE_PORT_ULONG((PULONG)0xCF8, 0x80000000);
|
||||
if (READ_PORT_ULONG((PULONG)0xCF8) == 0x80000000)
|
||||
{
|
||||
WRITE_PORT_ULONG((PULONG)0xCF8, Value);
|
||||
DPRINT(" Success!\n");
|
||||
return pbtType1;
|
||||
}
|
||||
WRITE_PORT_ULONG((PULONG)0xCF8, Value);
|
||||
DPRINT(" Unsuccessful!\n");
|
||||
|
||||
DPRINT("Checking configuration type 2:\n");
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xCFB, 0x00);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xCF8, 0x00);
|
||||
WRITE_PORT_UCHAR((PUCHAR)0xCFA, 0x00);
|
||||
if (READ_PORT_UCHAR((PUCHAR)0xCF8) == 0x00 &&
|
||||
READ_PORT_UCHAR((PUCHAR)0xCFB) == 0x00)
|
||||
{
|
||||
DPRINT(" Success!\n");
|
||||
return pbtType2;
|
||||
}
|
||||
DPRINT(" Unsuccessful!\n");
|
||||
|
||||
DPRINT("No pci bus found!\n");
|
||||
return pbtUnknown;
|
||||
}
|
||||
|
||||
|
||||
NTSTATUS
|
||||
STDCALL
|
||||
PciDispatchDeviceControl(
|
||||
|
|
|
|||
|
|
@ -1,11 +1,8 @@
|
|||
/* $Id: pci.h,v 1.3 2003/11/14 17:13:24 weiden Exp $ */
|
||||
/* $Id: pci.h,v 1.4 2003/12/12 21:54:42 ekohl Exp $ */
|
||||
|
||||
#ifndef __PCI_H
|
||||
#define __PCI_H
|
||||
|
||||
#include <ddk/ntddk.h>
|
||||
#include <pcidef.h>
|
||||
|
||||
|
||||
typedef enum {
|
||||
pbtUnknown = 0,
|
||||
|
|
@ -20,6 +17,8 @@ typedef struct _PCI_DEVICE
|
|||
LIST_ENTRY ListEntry;
|
||||
// Physical Device Object of device
|
||||
PDEVICE_OBJECT Pdo;
|
||||
/* PCI Slot number */
|
||||
PCI_SLOT_NUMBER SlotNumber;
|
||||
// PCI configuration data
|
||||
PCI_COMMON_CONFIG PciConfig;
|
||||
// Flag used during enumeration to locate removed devices
|
||||
|
|
@ -103,21 +102,9 @@ FdoPowerControl(
|
|||
|
||||
/* pci.c */
|
||||
|
||||
extern PCI_BUS_TYPE PciBusConfigType;
|
||||
|
||||
PCI_BUS_TYPE
|
||||
PciGetBusConfigType(VOID);
|
||||
|
||||
ULONG
|
||||
PciGetBusData(ULONG BusNumber,
|
||||
ULONG SlotNumber,
|
||||
PVOID Buffer,
|
||||
ULONG Offset,
|
||||
ULONG Length);
|
||||
|
||||
BOOLEAN
|
||||
PciCreateUnicodeString(
|
||||
PUNICODE_STRING Destination,
|
||||
PUNICODE_STRING Destination,
|
||||
PWSTR Source,
|
||||
POOL_TYPE PoolType);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* $Id: pcidef.h,v 1.2 2001/11/01 23:17:10 ekohl Exp $
|
||||
* $Id: pcidef.h,v 1.3 2003/12/12 21:54:42 ekohl Exp $
|
||||
*
|
||||
* PCI defines and function prototypes
|
||||
* Copyright 1994, Drew Eckhardt
|
||||
|
|
@ -301,15 +301,4 @@
|
|||
|
||||
#define PCI_REGION_FLAG_MASK 0x0f /* These bits of resource flags tell us the PCI region flags */
|
||||
|
||||
|
||||
|
||||
#define CONFIG_CMD(bus, device_fn, where) \
|
||||
(0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
|
||||
|
||||
#define IOADDR(devfn, where) \
|
||||
((0xC000 | ((devfn & 0x78) << 5)) + where)
|
||||
|
||||
#define FUNC(devfn) \
|
||||
(((devfn & 7) << 1) | 0xf0)
|
||||
|
||||
#endif /* _PCIDEF_H */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $Id: pdo.c,v 1.1 2001/09/16 13:18:24 chorns Exp $
|
||||
/* $Id: pdo.c,v 1.2 2003/12/12 21:54:42 ekohl Exp $
|
||||
*
|
||||
* PROJECT: ReactOS PCI bus driver
|
||||
* FILE: pdo.c
|
||||
|
|
@ -7,7 +7,11 @@
|
|||
* UPDATE HISTORY:
|
||||
* 10-09-2001 CSH Created
|
||||
*/
|
||||
#include <pci.h>
|
||||
|
||||
#include <ddk/ntddk.h>
|
||||
|
||||
#include "pcidef.h"
|
||||
#include "pci.h"
|
||||
|
||||
#define NDEBUG
|
||||
#include <debug.h>
|
||||
|
|
|
|||
Loading…
Reference in a new issue